stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
This commit is contained in:
parent
646c4a23ca
commit
b63631536d
87 changed files with 16959 additions and 17850 deletions
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@ -520,8 +520,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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writeBursts++;
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// see if we can merge with an existing item in the write
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// queue and keep track of whether we have merged or not, as
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// there is only ever one item to merge with
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// queue and keep track of whether we have merged or not so we
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// can stop at that point and also avoid enqueueing a new
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// request
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bool merged = false;
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auto w = writeQueue.begin();
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@ -529,6 +530,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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// either of the two could be first, if they are the same
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// it does not matter which way we go
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if ((*w)->addr >= addr) {
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// the existing one starts after the new one, figure
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// out where the new one ends with respect to the
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// existing one
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if ((addr + size) >= ((*w)->addr + (*w)->size)) {
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// check if the existing one is completely
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// subsumed in the new one
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@ -550,6 +554,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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(*w)->size = (*w)->addr + (*w)->size - addr;
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}
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} else {
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// the new one starts after the current one, figure
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// out where the existing one ends with respect to the
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// new one
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if (((*w)->addr + (*w)->size) >= (addr + size)) {
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// check if the new one is completely subsumed in the
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// existing one
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File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 1.860201 # Nu
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sim_ticks 1860200687500 # Number of ticks simulated
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final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 112423 # Simulator instruction rate (inst/s)
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host_op_rate 112423 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3947369845 # Simulator tick rate (ticks/s)
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host_mem_usage 310252 # Number of bytes of host memory used
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host_seconds 471.25 # Real time elapsed on the host
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host_inst_rate 95880 # Simulator instruction rate (inst/s)
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host_op_rate 95880 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3366492305 # Simulator tick rate (ticks/s)
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host_mem_usage 308824 # Number of bytes of host memory used
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host_seconds 552.56 # Real time elapsed on the host
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sim_insts 52979577 # Number of instructions simulated
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sim_ops 52979577 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
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@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 518206 # To
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system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 445243 # Total number of read requests seen
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system.physmem.writeReqs 117437 # Total number of write requests seen
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system.physmem.cpureqs 562856 # Reqs generatd by CPU via cache - shady
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system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller
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system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller
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system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
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system.physmem.bytesRead 28495552 # Total number of bytes read from memory
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system.physmem.bytesWritten 7515968 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 55 # Number of read reqs serviced by write Q
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system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q
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system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis
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@ -336,17 +337,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_respo
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.physmem.port 1008832 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.physmem.port 36011520 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 36055668 # Total data (bytes)
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system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
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@ -360,15 +356,15 @@ system.membus.respLayer1.occupancy 3765192546 # La
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks)
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system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.iocache.tags.replacements 41685 # number of replacements
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system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
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system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor
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system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy
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system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy
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system.iocache.tags.replacements 41685 # number of replacements
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system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
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system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor
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system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy
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system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy
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system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
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system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
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@ -819,19 +815,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio
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system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
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@ -848,19 +831,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio
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system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.data_through_bus 2705756 # Total data (bytes)
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system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
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@ -905,12 +875,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 66 #
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system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2019865 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3677460 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count 5697325 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64631872 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143567348 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size 208199220 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes)
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system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks)
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@ -921,15 +891,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # La
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system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu.icache.tags.replacements 1009263 # number of replacements
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system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy
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system.cpu.icache.tags.replacements 1009263 # number of replacements
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system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits
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@ -1005,19 +975,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 338298 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.replacements 338298 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits
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@ -1185,15 +1155,15 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1401048 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1401048 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 1.842705 # Nu
|
|||
sim_ticks 1842705252000 # Number of ticks simulated
|
||||
final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 221595 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 221595 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5621199023 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308252 # Number of bytes of host memory used
|
||||
host_seconds 327.81 # Real time elapsed on the host
|
||||
host_inst_rate 308319 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 308319 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7821132493 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307864 # Number of bytes of host memory used
|
||||
host_seconds 235.61 # Real time elapsed on the host
|
||||
sim_insts 72641883 # Number of instructions simulated
|
||||
sim_ops 72641883 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory
|
||||
|
@ -58,14 +58,15 @@ system.physmem.bw_total::cpu1.data 1242973 # To
|
|||
system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 99238 # Total number of read requests seen
|
||||
system.physmem.writeReqs 44800 # Total number of write requests seen
|
||||
system.physmem.cpureqs 144082 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 6351232 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 2867200 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis
|
||||
|
@ -298,17 +299,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio
|
|||
system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 13322 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 243525 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 9218432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 35966088 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
|
||||
|
@ -322,27 +318,27 @@ system.membus.respLayer1.occupancy 771793954 # La
|
|||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 337384 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 337384 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 518817 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 493229 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 124693 # number of ReadReq hits
|
||||
|
@ -626,15 +622,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf
|
|||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.tags.replacements 41685 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy
|
||||
system.iocache.tags.replacements 41685 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
|
@ -780,10 +776,10 @@ system.cpu0.num_fp_register_writes 89168 # nu
|
|||
system.cpu0.num_mem_refs 8444409 # number of memory refs
|
||||
system.cpu0.num_load_insts 4931349 # Number of load instructions
|
||||
system.cpu0.num_store_insts 3513060 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 212988700365.392029 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles -212060383474.392029 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction -228.435339 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 229.435339 # Percentage of idle cycles
|
||||
system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed
|
||||
system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed
|
||||
|
@ -912,12 +908,12 @@ system.toL2Bus.trans_dist::UpgradeResp 17 # Tr
|
|||
system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 849315 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1370344 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 2219659 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27177600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55325386 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 82502986 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 203464200 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks)
|
||||
|
@ -942,13 +938,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
|
|||
system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -959,13 +948,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
|
|||
system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2707184 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks)
|
||||
|
@ -986,19 +968,19 @@ system.iobus.respLayer0.occupancy 9566000 # La
|
|||
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu0.icache.tags.replacements 950451 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.replacements 950451 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 246.999230 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.674980 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.517805 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482420 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194678 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321324 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 33216972 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 7763860 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 2240171 # number of ReadReq hits
|
||||
|
@ -1116,19 +1098,19 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12347.049089
|
|||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.tags.replacements 1391525 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.replacements 1391525 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.196143 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.348399 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.453270 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488664 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254587 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256745 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 4073389 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 1086662 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu2.data 2399601 # number of ReadReq hits
|
||||
|
@ -1412,10 +1394,10 @@ system.cpu1.num_fp_register_writes 24577 # nu
|
|||
system.cpu1.num_mem_refs 2116682 # number of memory refs
|
||||
system.cpu1.num_load_insts 1209934 # Number of load instructions
|
||||
system.cpu1.num_store_insts 906748 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles -715527638.238183 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 1669158056.238183 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 1.750320 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction -0.750320 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 923700977.463911 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
|
||||
|
|
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -4,11 +4,11 @@ sim_seconds 5.133763 # Nu
|
|||
sim_ticks 5133762710000 # Number of ticks simulated
|
||||
final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 199223 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 393808 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2508257843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 730904 # Number of bytes of host memory used
|
||||
host_seconds 2046.74 # Real time elapsed on the host
|
||||
host_inst_rate 156198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 308758 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1966557914 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 728732 # Number of bytes of host memory used
|
||||
host_seconds 2610.53 # Real time elapsed on the host
|
||||
sim_insts 407759186 # Number of instructions simulated
|
||||
sim_ops 806023868 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory
|
||||
|
@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To
|
|||
system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 222526 # Total number of read requests seen
|
||||
system.physmem.writeReqs 148565 # Total number of write requests seen
|
||||
system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 222526 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 148565 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 222526 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 148565 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 14241664 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 9508160 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis
|
||||
|
@ -401,39 +402,31 @@ system.membus.trans_dist::MessageReq 1642 # Tr
|
|||
system.membus.trans_dist::MessageResp 1642 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25548207 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 250293000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 583289000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.occupancy 1608355497 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
@ -441,15 +434,15 @@ system.membus.respLayer2.occupancy 3156883661 # La
|
|||
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks)
|
||||
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.iocache.tags.replacements 47574 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 47574 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
|
@ -575,26 +568,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
|
|||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -619,26 +592,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid
|
|||
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 3276058 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks)
|
||||
|
@ -968,16 +921,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1906694 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6122854 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 16266 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8200791 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61010496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207591623 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 510912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5512832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 274625863 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks)
|
||||
|
@ -992,15 +945,15 @@ system.cpu.toL2Bus.respLayer2.occupancy 12430241 # La
|
|||
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 952820 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 952820 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits
|
||||
|
@ -1077,10 +1030,10 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy
|
||||
|
@ -1161,10 +1114,10 @@ system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.
|
|||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy
|
||||
|
@ -1240,15 +1193,15 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789
|
|||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1656828 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1656828 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits
|
||||
|
@ -1360,23 +1313,23 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
|
|||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 111287 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 111287 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 50594.922506 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.467907 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125935 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.772017 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000144 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047729 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169245 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63059 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6479 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 937263 # number of ReadReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 5.304405 # Nu
|
|||
sim_ticks 5304405061000 # Number of ticks simulated
|
||||
final_tick 5304405061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 226332 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 434274 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11093442301 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 870272 # Number of bytes of host memory used
|
||||
host_seconds 478.16 # Real time elapsed on the host
|
||||
host_inst_rate 96456 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 185076 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4727720712 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 825708 # Number of bytes of host memory used
|
||||
host_seconds 1121.98 # Real time elapsed on the host
|
||||
sim_insts 108221987 # Number of instructions simulated
|
||||
sim_ops 207651289 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory
|
||||
|
@ -72,14 +72,15 @@ system.physmem.bw_total::cpu1.itb.walker 7758 # To
|
|||
system.physmem.bw_total::cpu1.inst 32140877 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 9555659 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 225885267 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 804 # Total number of read requests seen
|
||||
system.physmem.writeReqs 46736 # Total number of write requests seen
|
||||
system.physmem.cpureqs 47256 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 51456 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
@ -308,29 +309,6 @@ system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupt
|
|||
system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.physmem.port 95080 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pit.pio 33204 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1372 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.i_dont_exist.pio 33352 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.com_1.pio 26412 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu0.interrupts.pio 751802 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu0.interrupts.int_slave 2728 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu1.interrupts.int_slave 2670 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::total 1908880 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -371,58 +349,35 @@ system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interr
|
|||
system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 16602 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 16676 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.com_1.pio 13206 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1503598 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 5456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 5340 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::total 5087902 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.data_through_bus 5087902 # Total data (bytes)
|
||||
system.piobus.reqLayer0.occupancy 421716677 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer0.occupancy 49000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer1.occupancy 49000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer2.occupancy 7500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer2.occupancy 10159500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer3.occupancy 10159500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer3.occupancy 140500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer4.occupancy 1061000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer5.occupancy 1061000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer5.occupancy 97000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer6.occupancy 97000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer6.occupancy 57000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer7.occupancy 57000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer7.occupancy 30437500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer8.occupancy 30437500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer9.occupancy 586857000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer9.occupancy 1329000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer10.occupancy 1329000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer10.occupancy 33375500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer11.occupancy 33375500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer12.occupancy 23058500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer13.occupancy 23058500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
||||
|
@ -430,15 +385,15 @@ system.piobus.reqLayer15.occupancy 10500 # La
|
|||
system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer17.occupancy 473807500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer18.occupancy 473807500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer18.occupancy 3197816 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer19.occupancy 3197816 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer19.occupancy 8805500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer20.occupancy 8805500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer20.occupancy 3140084 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer21.occupancy 3140084 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer21.occupancy 421716677 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer22.occupancy 1081500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 5.139589 # Nu
|
|||
sim_ticks 5139589353000 # Number of ticks simulated
|
||||
final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 286755 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 569759 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6048900638 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 936564 # Number of bytes of host memory used
|
||||
host_seconds 849.67 # Real time elapsed on the host
|
||||
host_inst_rate 190335 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 378180 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4014985901 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 934028 # Number of bytes of host memory used
|
||||
host_seconds 1280.10 # Real time elapsed on the host
|
||||
sim_insts 243647713 # Number of instructions simulated
|
||||
sim_ops 484108731 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory
|
||||
|
@ -70,14 +70,15 @@ system.physmem.bw_total::cpu2.itb.walker 12 # To
|
|||
system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 96603 # Total number of read requests seen
|
||||
system.physmem.writeReqs 74912 # Total number of write requests seen
|
||||
system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 96603 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 74912 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 96603 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 74912 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 6182592 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4794368 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 12 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis
|
||||
|
@ -388,39 +389,31 @@ system.membus.trans_dist::MessageReq 216 # Tr
|
|||
system.membus.trans_dist::MessageResp 216 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 32713165 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 164366000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 314753000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 432000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.occupancy 793885999 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
@ -428,33 +421,33 @@ system.membus.respLayer2.occupancy 1632166487 # La
|
|||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 104154 # number of replacements
|
||||
system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 104154 # number of replacements
|
||||
system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits
|
||||
|
@ -833,15 +826,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf
|
|||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.tags.replacements 47579 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 47579 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.100447 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006278 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
|
@ -947,16 +940,16 @@ system.toL2Bus.trans_dist::UpgradeReq 745 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 966317 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3599461 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 26176 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 114965 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 4706919 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 30921472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118979348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 89784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 413728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 150404332 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 267998065 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks)
|
||||
|
@ -997,22 +990,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
|
|||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -1033,22 +1010,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid
|
|||
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 6479664 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks)
|
||||
|
@ -1107,25 +1068,25 @@ system.cpu0.num_fp_register_writes 0 # nu
|
|||
system.cpu0.num_mem_refs 14736464 # number of memory refs
|
||||
system.cpu0.num_load_insts 10677140 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4059324 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles
|
||||
system.cpu0.num_idle_cycles 1727957342.597034 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 93395662.402966 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.051278 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.948722 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 847048 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.replacements 847048 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits
|
||||
|
@ -1243,19 +1204,19 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12086.099992
|
|||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.tags.replacements 1634474 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.replacements 1634474 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 379.364018 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.391213 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.244158 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.740945 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246858 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012196 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 5614384 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 2225977 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu2.data 3715968 # number of ReadReq hits
|
||||
|
@ -1447,10 +1408,10 @@ system.cpu1.num_fp_register_writes 0 # nu
|
|||
system.cpu1.num_mem_refs 4252332 # number of memory refs
|
||||
system.cpu1.num_load_insts 2649427 # Number of load instructions
|
||||
system.cpu1.num_store_insts 1602905 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 2479239642.942777 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 126766142.057223 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.048644 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.951356 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu2.branchPred.lookups 28549199 # Number of BP lookups
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu
|
|||
sim_ticks 26877484000 # Number of ticks simulated
|
||||
final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 175198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 176456 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 51980195 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 379404 # Number of bytes of host memory used
|
||||
host_seconds 517.07 # Real time elapsed on the host
|
||||
host_inst_rate 190344 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 191711 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56473959 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375760 # Number of bytes of host memory used
|
||||
host_seconds 475.93 # Real time elapsed on the host
|
||||
sim_insts 90589798 # Number of instructions simulated
|
||||
sim_ops 91240351 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1671585 # In
|
|||
system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 15506 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 992384 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis
|
||||
|
@ -214,10 +215,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 992384 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks)
|
||||
|
@ -546,12 +547,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks)
|
||||
|
@ -560,15 +561,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1225499 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits
|
||||
|
@ -644,19 +645,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits
|
||||
|
@ -805,15 +806,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 943531 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 943531 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
|
|||
sim_ticks 147135976000 # Number of ticks simulated
|
||||
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 662214 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 666963 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1075722156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375060 # Number of bytes of host memory used
|
||||
host_seconds 136.78 # Real time elapsed on the host
|
||||
host_inst_rate 529408 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 533204 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 859987474 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 373720 # Number of bytes of host memory used
|
||||
host_seconds 171.09 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 792 # Tr
|
|||
system.membus.trans_dist::ReadResp 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 981760 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks)
|
||||
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 294271952 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
|
||||
|
@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
|
||||
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
|
||||
|
@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
|
|||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 653861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 653888 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 969395755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365508 # Number of bytes of host memory used
|
||||
host_seconds 372.90 # Real time elapsed on the host
|
||||
host_inst_rate 810264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 810297 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1201274596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365008 # Number of bytes of host memory used
|
||||
host_seconds 300.92 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 1036 # Tr
|
|||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 998592 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 722977060 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
|
@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
|
||||
|
@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
||||
|
@ -405,12 +405,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.065502 # Nu
|
|||
sim_ticks 65501881000 # Number of ticks simulated
|
||||
final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72627 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 127885 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30111215 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 386704 # Number of bytes of host memory used
|
||||
host_seconds 2175.33 # Real time elapsed on the host
|
||||
host_inst_rate 73961 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 130234 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30664297 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 385548 # Number of bytes of host memory used
|
||||
host_seconds 2136.10 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 159263 # To
|
|||
system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 30410 # Total number of read requests seen
|
||||
system.physmem.writeReqs 163 # Total number of write requests seen
|
||||
system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 30410 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 163 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 30410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 163 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 1946112 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 10432 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis
|
||||
|
@ -232,11 +233,9 @@ system.membus.trans_dist::ReadExReq 29004 # Tr
|
|||
system.membus.trans_dist::ReadExResp 29004 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1956480 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -519,12 +518,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219763 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6221783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265164480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 265229120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks)
|
||||
|
@ -533,15 +532,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1707500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 57 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 57 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits
|
||||
|
@ -617,19 +616,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 474 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 474 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19907.577759 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007490 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1993851 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1993867 # number of ReadReq hits
|
||||
|
@ -755,15 +754,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55141.851107
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2072469 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2072469 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
|
|||
sim_ticks 365989065000 # Number of ticks simulated
|
||||
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 466388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 821234 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1080412484 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 431468 # Number of bytes of host memory used
|
||||
host_seconds 338.75 # Real time elapsed on the host
|
||||
host_inst_rate 324809 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 571936 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 752437231 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382748 # Number of bytes of host memory used
|
||||
host_seconds 486.40 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
||||
|
@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 29024 # Tr
|
|||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1929536 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 731978130 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
|
||||
|
@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 318 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 318 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
|
||||
|
@ -293,15 +291,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
||||
|
@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu
|
|||
sim_ticks 202349747500 # Number of ticks simulated
|
||||
final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166059 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 187221 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66507382 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250660 # Number of bytes of host memory used
|
||||
host_seconds 3042.52 # Real time elapsed on the host
|
||||
host_inst_rate 95439 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 107602 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38223736 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246676 # Number of bytes of host memory used
|
||||
host_seconds 5293.82 # Real time elapsed on the host
|
||||
sim_insts 505237723 # Number of instructions simulated
|
||||
sim_ops 569624283 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 30890515 # To
|
|||
system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 148206 # Total number of read requests seen
|
||||
system.physmem.writeReqs 97667 # Total number of write requests seen
|
||||
system.physmem.cpureqs 245886 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 148206 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 97667 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 148206 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 97667 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 9485120 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 6250688 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis
|
||||
|
@ -297,10 +298,10 @@ system.membus.trans_dist::UpgradeReq 7 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101306 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101306 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15735808 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks)
|
||||
|
@ -628,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33804 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3504826 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3538630 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1079232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147703872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 148783104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33804 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504826 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3538630 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147703872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 148783104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks)
|
||||
|
@ -642,15 +643,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 26125731 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 15008 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 15008 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits
|
||||
|
@ -726,19 +727,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 25103.227023
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 115462 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 115462 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23019.815136 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.702509 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011145 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113526 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 13469 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 804438 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 817907 # number of ReadReq hits
|
||||
|
@ -889,15 +890,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1192719 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1192719 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu
|
|||
sim_ticks 717366012000 # Number of ticks simulated
|
||||
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 611042 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 688541 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 868024183 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246240 # Number of bytes of host memory used
|
||||
host_seconds 826.44 # Real time elapsed on the host
|
||||
host_inst_rate 1130634 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1274033 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1606137434 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243872 # Number of bytes of host memory used
|
||||
host_seconds 446.64 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 41855 # Tr
|
|||
system.membus.trans_dist::Writeback 95953 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15270528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks)
|
||||
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1434732024 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
|
||||
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits
|
||||
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3342741 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3365783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.458202 # Nu
|
|||
sim_ticks 458201684000 # Number of ticks simulated
|
||||
final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 111882 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 206882 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61997502 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341328 # Number of bytes of host memory used
|
||||
host_seconds 7390.65 # Real time elapsed on the host
|
||||
host_inst_rate 77434 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 143185 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42909026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 338808 # Number of bytes of host memory used
|
||||
host_seconds 10678.45 # Real time elapsed on the host
|
||||
sim_insts 826877109 # Number of instructions simulated
|
||||
sim_ops 1528988701 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 41005663 # To
|
|||
system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 385586 # Total number of read requests seen
|
||||
system.physmem.writeReqs 293576 # Total number of write requests seen
|
||||
system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 385586 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 293576 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 385586 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 293576 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 24677504 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 18788864 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis
|
||||
|
@ -316,11 +317,9 @@ system.membus.trans_dist::ReadExReq 206848 # Tr
|
|||
system.membus.trans_dist::ReadExResp 206848 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 43466368 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -606,12 +605,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 146337 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7664164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7810501 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 435712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311349248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 311784960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks)
|
||||
|
@ -620,15 +619,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 209959241 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 5293 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 5293 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 161845824 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 161845824 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 161845824 # number of demand (read+write) hits
|
||||
|
@ -704,19 +703,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 3994.146443
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3994.146443 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 3994.146443 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 352905 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29673.331814 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3696859 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 385269 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 9.595527 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 199076310000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 352905 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29673.331814 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3696859 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 385269 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 9.595527 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 199076310000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 21119.362848 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.841801 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8330.127165 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.841801 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8330.127165 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.644512 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006831 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.254215 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.905558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.905558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3661 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1586701 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1590362 # number of ReadReq hits
|
||||
|
@ -862,15 +861,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65139.453621
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2529980 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2529980 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
|
|||
sim_ticks 1647872849000 # Number of ticks simulated
|
||||
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 533286 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 986105 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1062778196 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304632 # Number of bytes of host memory used
|
||||
host_seconds 1550.53 # Real time elapsed on the host
|
||||
host_inst_rate 418246 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 773383 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 833516309 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254900 # Number of bytes of host memory used
|
||||
host_seconds 1977.01 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
|
||||
|
@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 206691 # Tr
|
|||
system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 43099456 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
|
||||
|
@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 348459 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 348459 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits
|
||||
|
@ -293,15 +291,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
|
||||
|
@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.139916 # Nu
|
|||
sim_ticks 139916242500 # Number of ticks simulated
|
||||
final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 84616 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29697100 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231112 # Number of bytes of host memory used
|
||||
host_seconds 4711.44 # Real time elapsed on the host
|
||||
host_inst_rate 80792 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 80792 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 28354866 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231004 # Number of bytes of host memory used
|
||||
host_seconds 4934.47 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1536462 # In
|
|||
system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 468992 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis
|
||||
|
@ -245,10 +246,10 @@ system.membus.trans_dist::ReadReq 4183 # Tr
|
|||
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 468992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks)
|
||||
|
@ -357,15 +358,15 @@ system.cpu.stage3.utilization 35.287049 # Pe
|
|||
system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits
|
||||
|
@ -447,12 +448,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 16759 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 249792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 557056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
||||
|
@ -461,19 +462,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 6540750 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
||||
|
@ -597,15 +598,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.077522 # Nu
|
|||
sim_ticks 77521581000 # Number of ticks simulated
|
||||
final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 159390 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 159390 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32899346 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233160 # Number of bytes of host memory used
|
||||
host_seconds 2356.33 # Real time elapsed on the host
|
||||
host_inst_rate 226587 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 226587 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46769350 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233048 # Number of bytes of host memory used
|
||||
host_seconds 1657.53 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 2850716 # In
|
|||
system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7442 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 7442 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 7442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 476288 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis
|
||||
|
@ -242,10 +243,10 @@ system.membus.trans_dist::ReadReq 4310 # Tr
|
|||
system.membus.trans_dist::ReadResp 4310 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3132 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 476288 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks)
|
||||
|
@ -561,12 +562,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 17190 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 310656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 571392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8148 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 17190 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 571392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks)
|
||||
|
@ -575,15 +576,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 6844000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 2147 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 2147 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 50272888 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 50272888 # number of demand (read+write) hits
|
||||
|
@ -659,19 +660,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4008.519135 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 851 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4844 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.175681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4008.519135 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 851 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4844 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.175681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.365398 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2979.019245 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 658.134493 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2979.019245 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 658.134493 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011333 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090912 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020085 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 752 # number of ReadReq hits
|
||||
|
@ -795,15 +796,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 788 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 788 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
|||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1715092 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1715091 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2440727076 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230984 # Number of bytes of host memory used
|
||||
host_seconds 232.45 # Real time elapsed on the host
|
||||
host_inst_rate 1598767 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2275187152 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229960 # Number of bytes of host memory used
|
||||
host_seconds 249.36 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 4032 # Tr
|
|||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 459136 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
|
||||
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1134670186 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
|
@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
|
||||
|
@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
|
||||
|
@ -417,12 +417,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 16299 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu
|
|||
sim_ticks 68375005500 # Number of ticks simulated
|
||||
final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 171790 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 219625 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43020256 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254724 # Number of bytes of host memory used
|
||||
host_seconds 1589.37 # Real time elapsed on the host
|
||||
host_inst_rate 121198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154946 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30350947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251080 # Number of bytes of host memory used
|
||||
host_seconds 2252.81 # Real time elapsed on the host
|
||||
sim_insts 273036725 # Number of instructions simulated
|
||||
sim_ops 349064449 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 2839868 # In
|
|||
system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7288 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7293 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 466432 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis
|
||||
|
@ -243,10 +244,10 @@ system.membus.trans_dist::UpgradeReq 5 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2821 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2821 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 466432 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks)
|
||||
|
@ -575,12 +576,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10263 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 41937 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 1374656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10263 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 41937 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 1374656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks)
|
||||
|
@ -589,15 +590,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 24379238 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 13946 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 13946 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits
|
||||
|
@ -673,19 +674,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 22057.528977
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3937.726706 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13182 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5389 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.446094 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3937.726706 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13182 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5389 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.446094 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 375.051576 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011446 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084891 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.023833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12788 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 13086 # number of ReadReq hits
|
||||
|
@ -832,15 +833,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1414 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1414 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu
|
|||
sim_ticks 525834342000 # Number of ticks simulated
|
||||
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 442791 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 566092 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 853689730 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250392 # Number of bytes of host memory used
|
||||
host_seconds 615.96 # Real time elapsed on the host
|
||||
host_inst_rate 414348 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 529728 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 798851724 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248008 # Number of bytes of host memory used
|
||||
host_seconds 658.24 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 3976 # Tr
|
|||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 437248 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
|
||||
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
|
||||
|
@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
|
||||
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
|
@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.631883 # Nu
|
|||
sim_ticks 631883288500 # Number of ticks simulated
|
||||
final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 129491 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 129491 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44882876 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237188 # Number of bytes of host memory used
|
||||
host_seconds 14078.49 # Real time elapsed on the host
|
||||
host_inst_rate 177291 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 177291 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61450789 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236780 # Number of bytes of host memory used
|
||||
host_seconds 10282.75 # Real time elapsed on the host
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_ops 1823043370 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 6776745 # To
|
|||
system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 476114 # Total number of read requests seen
|
||||
system.physmem.writeReqs 66908 # Total number of write requests seen
|
||||
system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 476114 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 66908 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 476114 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 66908 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30471232 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis
|
||||
|
@ -262,10 +263,10 @@ system.membus.trans_dist::ReadResp 409257 # Tr
|
|||
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66856 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34753344 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks)
|
||||
|
@ -581,12 +582,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20089 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159776 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3179865 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 642816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 104827200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20089 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159776 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3179865 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104184384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 104827200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks)
|
||||
|
@ -595,15 +596,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 15605000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 8334 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 8334 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits
|
||||
|
@ -679,19 +680,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 27883.100946
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 443335 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 443335 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1328.456107 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.040541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.956023 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 7293 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1053744 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1061037 # number of ReadReq hits
|
||||
|
@ -817,15 +818,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58975.018169
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1527799 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1527799 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu
|
|||
sim_ticks 2769739533000 # Number of ticks simulated
|
||||
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1559352 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2149839105 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233980 # Number of bytes of host memory used
|
||||
host_seconds 1288.35 # Real time elapsed on the host
|
||||
host_inst_rate 892879 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 892879 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1230989339 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233984 # Number of bytes of host memory used
|
||||
host_seconds 2250.01 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 408476 # Tr
|
|||
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34704448 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
|
||||
|
@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
|
||||
|
@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 442570 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 442570 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits
|
||||
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
|
||||
|
@ -427,12 +427,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.640648 # Nu
|
|||
sim_ticks 640648369500 # Number of ticks simulated
|
||||
final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 99606 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 135651 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46095119 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254320 # Number of bytes of host memory used
|
||||
host_seconds 13898.40 # Real time elapsed on the host
|
||||
host_inst_rate 107808 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 146820 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49890421 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251704 # Number of bytes of host memory used
|
||||
host_seconds 12841.11 # Real time elapsed on the host
|
||||
sim_insts 1384370590 # Number of instructions simulated
|
||||
sim_ops 1885325342 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 6603111 # To
|
|||
system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 474992 # Total number of read requests seen
|
||||
system.physmem.writeReqs 66098 # Total number of write requests seen
|
||||
system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30399488 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
|
||||
|
@ -244,10 +245,10 @@ system.membus.trans_dist::UpgradeReq 4361 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34629696 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
|
||||
|
@ -576,12 +577,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
|
||||
|
@ -590,15 +591,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 43029998 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 22329 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 22329 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
|
||||
|
@ -674,19 +675,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 442208 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 442208 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits
|
||||
|
@ -837,15 +838,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1532805 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1532805 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
|
|||
sim_ticks 2326118592000 # Number of ticks simulated
|
||||
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 575384 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 780549 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 968736790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250996 # Number of bytes of host memory used
|
||||
host_seconds 2401.19 # Real time elapsed on the host
|
||||
host_inst_rate 481372 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 653016 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 810455855 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248632 # Number of bytes of host memory used
|
||||
host_seconds 2870.14 # Real time elapsed on the host
|
||||
sim_insts 1381604339 # Number of instructions simulated
|
||||
sim_ops 1874244941 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 408063 # Tr
|
|||
system.membus.trans_dist::Writeback 66099 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34576320 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
|
||||
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
|
||||
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 441378 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 441378 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits
|
||||
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1529557 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1529557 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
|
||||
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.043769 # Nu
|
|||
sim_ticks 43769191000 # Number of ticks simulated
|
||||
final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 112888 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 112888 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55931443 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233228 # Number of bytes of host memory used
|
||||
host_seconds 782.55 # Real time elapsed on the host
|
||||
host_inst_rate 69144 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69144 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34257993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232832 # Number of bytes of host memory used
|
||||
host_seconds 1277.63 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 166688208 # To
|
|||
system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165515 # Total number of read requests seen
|
||||
system.physmem.writeReqs 113997 # Total number of write requests seen
|
||||
system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 10592960 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis
|
||||
|
@ -311,10 +312,10 @@ system.membus.trans_dist::ReadResp 34625 # Tr
|
|||
system.membus.trans_dist::Writeback 113997 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130890 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130890 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17888768 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks)
|
||||
|
@ -423,15 +424,15 @@ system.cpu.stage3.utilization 25.270124 # Pe
|
|||
system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 84371 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 84371 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits
|
||||
|
@ -513,12 +514,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172834 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577046 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 749880 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5530688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23852736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29383424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks)
|
||||
|
@ -527,19 +528,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 131178984 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 131591 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 131591 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits
|
||||
|
@ -665,15 +666,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 200251 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 200251 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.024977 # Nu
|
|||
sim_ticks 24977022500 # Number of ticks simulated
|
||||
final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 130696 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 130696 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41014411 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236320 # Number of bytes of host memory used
|
||||
host_seconds 608.98 # Real time elapsed on the host
|
||||
host_inst_rate 124025 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 124025 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38920856 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235900 # Number of bytes of host memory used
|
||||
host_seconds 641.74 # Real time elapsed on the host
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_ops 79591756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 292149475 # To
|
|||
system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 166305 # Total number of read requests seen
|
||||
system.physmem.writeReqs 114016 # Total number of write requests seen
|
||||
system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 10643520 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7297024 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis
|
||||
|
@ -309,10 +310,10 @@ system.membus.trans_dist::ReadResp 35508 # Tr
|
|||
system.membus.trans_dist::Writeback 114016 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130797 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130797 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17940544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks)
|
||||
|
@ -628,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks)
|
||||
|
@ -642,15 +643,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 141571734 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 91227 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 91227 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits
|
||||
|
@ -726,19 +727,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 17000.812278
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 132400 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 132400 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26388.752281 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.805321 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064277 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.067817 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 85619 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 34304 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 119923 # number of ReadReq hits
|
||||
|
@ -864,15 +865,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70298.942144
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 201470 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 201470 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
|
|||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 671194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 671194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1015328507 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233108 # Number of bytes of host memory used
|
||||
host_seconds 131.62 # Real time elapsed on the host
|
||||
host_inst_rate 775893 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 775893 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1173708198 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233104 # Number of bytes of host memory used
|
||||
host_seconds 113.86 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 34272 # Tr
|
|||
system.membus.trans_dist::Writeback 113982 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17864640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
|
||||
|
@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
|
||||
|
@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 131235 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 131235 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits
|
||||
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
|
||||
|
@ -427,12 +427,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.026765 # Nu
|
|||
sim_ticks 26765004500 # Number of ticks simulated
|
||||
final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 88779 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 125988 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33510752 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 255124 # Number of bytes of host memory used
|
||||
host_seconds 798.70 # Real time elapsed on the host
|
||||
host_inst_rate 102307 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 145187 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38617115 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251228 # Number of bytes of host memory used
|
||||
host_seconds 693.09 # Real time elapsed on the host
|
||||
sim_insts 70907629 # Number of instructions simulated
|
||||
sim_ops 100626876 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 200715827 # To
|
|||
system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 128790 # Total number of read requests seen
|
||||
system.physmem.writeReqs 83940 # Total number of write requests seen
|
||||
system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 8242496 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 5372160 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis
|
||||
|
@ -313,10 +314,10 @@ system.membus.trans_dist::UpgradeReq 321 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 321 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102252 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102252 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13614656 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks)
|
||||
|
@ -645,12 +646,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks)
|
||||
|
@ -659,15 +660,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 47827231 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 28871 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 28871 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits
|
||||
|
@ -743,19 +744,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 95660 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 95660 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041689 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.056307 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 26062 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33492 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits
|
||||
|
@ -910,15 +911,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 158372 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 158372 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu
|
|||
sim_ticks 132689045000 # Number of ticks simulated
|
||||
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 438025 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 621131 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 825892843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249772 # Number of bytes of host memory used
|
||||
host_seconds 160.66 # Real time elapsed on the host
|
||||
host_inst_rate 525201 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 744748 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 990262559 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247408 # Number of bytes of host memory used
|
||||
host_seconds 133.99 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 99791654 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 25532 # Tr
|
|||
system.membus.trans_dist::Writeback 83909 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13550144 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
|
||||
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 265378090 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits
|
||||
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 94693 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 94693 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits
|
||||
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu
|
|||
sim_ticks 202242260000 # Number of ticks simulated
|
||||
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 840510 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851393 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1264790801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241580 # Number of bytes of host memory used
|
||||
host_seconds 159.90 # Real time elapsed on the host
|
||||
host_inst_rate 788005 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 798208 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1185781953 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240044 # Number of bytes of host memory used
|
||||
host_seconds 170.56 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 30277 # Tr
|
|||
system.membus.trans_dist::Writeback 82868 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13721664 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
|
||||
|
@ -73,15 +73,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 404484520 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
|
||||
|
@ -151,19 +151,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 98540 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 98540 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits
|
||||
|
@ -289,15 +289,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
|
||||
|
@ -415,12 +415,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 1.017017 # Nu
|
|||
sim_ticks 1017016979500 # Number of ticks simulated
|
||||
final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 113008 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 113008 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63156510 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225148 # Number of bytes of host memory used
|
||||
host_seconds 16103.12 # Real time elapsed on the host
|
||||
host_inst_rate 89946 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 89946 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50268200 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224748 # Number of bytes of host memory used
|
||||
host_seconds 20231.82 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 64065511 # To
|
|||
system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959691 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1018058 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 1959691 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 1018058 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 1959691 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 1018058 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 125420224 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis
|
||||
|
@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1178393 # Tr
|
|||
system.membus.trans_dist::Writeback 1018058 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781298 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781298 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575936 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks)
|
||||
|
@ -428,15 +429,15 @@ system.cpu.stage3.utilization 20.138673 # Pe
|
|||
system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits
|
||||
|
@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1718 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916181 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21917899 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819557696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916181 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21917899 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819557696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks)
|
||||
|
@ -532,19 +533,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 1466500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 1926960 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 1926960 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits
|
||||
|
@ -667,15 +668,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9107355 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9107355 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.694171 # Nu
|
|||
sim_ticks 694171131000 # Number of ticks simulated
|
||||
final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 169313 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 169313 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 67701038 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228220 # Number of bytes of host memory used
|
||||
host_seconds 10253.48 # Real time elapsed on the host
|
||||
host_inst_rate 178600 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 178600 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 71414604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227828 # Number of bytes of host memory used
|
||||
host_seconds 9720.30 # Real time elapsed on the host
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_ops 1736043781 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 94013475 # To
|
|||
system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1966438 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1019710 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2986156 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 1966438 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 1019710 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 1966438 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 1019710 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 125852032 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65261440 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 561 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 561 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis
|
||||
|
@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1191259 # Tr
|
|||
system.membus.trans_dist::Writeback 1019710 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 775179 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 775179 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 191113472 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks)
|
||||
|
@ -635,12 +636,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1926 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085475 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 22087401 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825936384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 825998016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085475 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22087401 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825936384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 825998016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks)
|
||||
|
@ -649,15 +650,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1633750 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits
|
||||
|
@ -733,19 +734,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1933728 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 1933728 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.445357 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000794 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.513174 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.959325 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.959325 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6106292 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6106292 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3725037 # number of Writeback hits
|
||||
|
@ -868,15 +869,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9176123 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9176123 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
|
|||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 781919 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 781919 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1127211275 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225028 # Number of bytes of host memory used
|
||||
host_seconds 2327.32 # Real time elapsed on the host
|
||||
host_inst_rate 1731328 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1731328 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2495874089 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225024 # Number of bytes of host memory used
|
||||
host_seconds 1051.09 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1178362 # Tr
|
|||
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575360 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
|
||||
|
@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 5246772452 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
|
||||
|
@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926937 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 1926937 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits
|
||||
|
@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
|
@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.541686 # Nu
|
|||
sim_ticks 541686426500 # Number of ticks simulated
|
||||
final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 161069 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 179684 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56487595 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246340 # Number of bytes of host memory used
|
||||
host_seconds 9589.48 # Real time elapsed on the host
|
||||
host_inst_rate 146656 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163606 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 51433162 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242412 # Number of bytes of host memory used
|
||||
host_seconds 10531.85 # Real time elapsed on the host
|
||||
sim_insts 1544563023 # Number of instructions simulated
|
||||
sim_ops 1723073835 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory
|
||||
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 130020847 # To
|
|||
system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 2246464 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1100477 # Total number of write requests seen
|
||||
system.physmem.cpureqs 3346951 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 143773696 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 70430528 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 599 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis
|
||||
|
@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1420070 # Tr
|
|||
system.membus.trans_dist::Writeback 1100477 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 826393 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 826393 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 214204160 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks)
|
||||
|
@ -644,12 +645,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1564 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22987414 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 22988978 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856645824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 856695872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks)
|
||||
|
@ -658,15 +659,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1321749 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 22 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 22 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits
|
||||
|
@ -742,19 +743,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 2213775 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 2213775 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14312.491305 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.436783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000615 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.525321 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6289580 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6289609 # number of ReadReq hits
|
||||
|
@ -889,15 +890,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9598226 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9598226 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu
|
|||
sim_ticks 2391205115000 # Number of ticks simulated
|
||||
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1401168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2177389973 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243008 # Number of bytes of host memory used
|
||||
host_seconds 1098.20 # Real time elapsed on the host
|
||||
host_inst_rate 594937 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 663956 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 924522029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240640 # Number of bytes of host memory used
|
||||
host_seconds 2586.42 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1717270334 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1177898 # Tr
|
|||
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190462208 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
|
||||
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
|
||||
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926075 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 1926075 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
|
||||
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
|
||||
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
|
|||
sim_ticks 5882580526000 # Number of ticks simulated
|
||||
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 548624 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 854806 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1072884756 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295308 # Number of bytes of host memory used
|
||||
host_seconds 5482.96 # Real time elapsed on the host
|
||||
host_inst_rate 645050 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1261455450 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245540 # Number of bytes of host memory used
|
||||
host_seconds 4663.33 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
|
@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 781295 # Tr
|
|||
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190549120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
|
||||
|
@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926197 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 1926197 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
|
||||
|
@ -290,15 +288,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
|
@ -396,12 +394,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.041672 # Nu
|
|||
sim_ticks 41671895000 # Number of ticks simulated
|
||||
final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 84546 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84546 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38336000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228812 # Number of bytes of host memory used
|
||||
host_seconds 1087.02 # Real time elapsed on the host
|
||||
host_inst_rate 101828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 101828 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46172411 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228672 # Number of bytes of host memory used
|
||||
host_seconds 902.53 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 4291046 # In
|
|||
system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 316032 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis
|
||||
|
@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq 3216 # Tr
|
|||
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks)
|
||||
|
@ -351,15 +352,15 @@ system.cpu.stage3.utilization 21.629101 # Pe
|
|||
system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
|
||||
|
@ -441,12 +442,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19040 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 23593 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 758400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
|
||||
|
@ -455,19 +456,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 14868500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
|
||||
|
@ -591,15 +592,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.023492 # Nu
|
|||
sim_ticks 23492267500 # Number of ticks simulated
|
||||
final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 122951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 122951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34312389 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231868 # Number of bytes of host memory used
|
||||
host_seconds 684.66 # Real time elapsed on the host
|
||||
host_inst_rate 120531 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 120531 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33636905 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231740 # Number of bytes of host memory used
|
||||
host_seconds 698.41 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 8339084 # In
|
|||
system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5226 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 5226 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 5226 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 334464 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis
|
||||
|
@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq 3520 # Tr
|
|||
system.membus.trans_dist::ReadResp 3520 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1706 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1706 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 334464 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks)
|
||||
|
@ -557,12 +558,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22984 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4598 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 735488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 886080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks)
|
||||
|
@ -571,15 +572,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 17871250 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 9559 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 9559 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits
|
||||
|
@ -655,19 +656,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.679636 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061269 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011570 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.073379 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.073379 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8431 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8486 # number of ReadReq hits
|
||||
|
@ -791,15 +792,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52525.726887
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 158 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 158 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
|
|||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 852211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 852211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1100968725 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2022504 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2022504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2612866318 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228676 # Number of bytes of host memory used
|
||||
host_seconds 107.84 # Real time elapsed on the host
|
||||
host_seconds 45.44 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 3043 # Tr
|
|||
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 304960 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 237458632 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
|
||||
|
@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
|
||||
|
@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
|
||||
|
@ -417,12 +417,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.074201 # Nu
|
|||
sim_ticks 74201024500 # Number of ticks simulated
|
||||
final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 81530 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 89268 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35110326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249620 # Number of bytes of host memory used
|
||||
host_seconds 2113.37 # Real time elapsed on the host
|
||||
host_inst_rate 88798 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 97225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38240010 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245976 # Number of bytes of host memory used
|
||||
host_seconds 1940.40 # Real time elapsed on the host
|
||||
sim_insts 172303021 # Number of instructions simulated
|
||||
sim_ops 188656503 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1769895 # In
|
|||
system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3801 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 243200 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis
|
||||
|
@ -238,10 +239,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 243200 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks)
|
||||
|
@ -571,12 +572,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8247 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3732 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 11979 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 263808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 383680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks)
|
||||
|
@ -585,15 +586,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 6609745 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 2391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 2391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits
|
||||
|
@ -669,19 +670,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043428 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2065 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits
|
||||
|
@ -828,15 +829,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 57 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 57 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu
|
|||
sim_ticks 232072304000 # Number of ticks simulated
|
||||
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1198657 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1618778979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245268 # Number of bytes of host memory used
|
||||
host_seconds 143.36 # Real time elapsed on the host
|
||||
host_inst_rate 705973 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 773116 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 953412259 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242928 # Number of bytes of host memory used
|
||||
host_seconds 243.41 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 188185920 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 2361 # Tr
|
|||
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 220992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
|
||||
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 464144608 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
|
||||
|
@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
|
||||
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
|
||||
|
@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu
|
|||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 942019 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 942020 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1317563963 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238020 # Number of bytes of host memory used
|
||||
host_seconds 205.35 # Real time elapsed on the host
|
||||
host_inst_rate 872463 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 872464 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1220278409 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236504 # Number of bytes of host memory used
|
||||
host_seconds 221.72 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 4095 # Tr
|
|||
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 331072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
|
||||
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 541126164 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
|
||||
|
@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
|
||||
|
@ -274,15 +274,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
|
||||
|
@ -400,12 +400,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.144471 # Nu
|
|||
sim_ticks 144470654000 # Number of ticks simulated
|
||||
final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76550 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 128304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 83736451 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279024 # Number of bytes of host memory used
|
||||
host_seconds 1725.30 # Real time elapsed on the host
|
||||
host_inst_rate 75912 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 127236 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 83039301 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277792 # Number of bytes of host memory used
|
||||
host_seconds 1739.79 # Real time elapsed on the host
|
||||
sim_insts 132071192 # Number of instructions simulated
|
||||
sim_ops 221362962 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1500429 # In
|
|||
system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5340 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 5340 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 5340 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 341760 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis
|
||||
|
@ -242,11 +243,9 @@ system.membus.trans_dist::ReadExReq 1530 # Tr
|
|||
system.membus.trans_dist::ReadExResp 1530 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 341696 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -531,12 +530,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13393 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4315 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 17708 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 552320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks)
|
||||
|
@ -545,15 +544,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 10832250 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4654 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 4654 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits
|
||||
|
@ -629,19 +628,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1.748933 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067843 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009533 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3232 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3270 # number of ReadReq hits
|
||||
|
@ -781,15 +780,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 56 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 56 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
|
|||
sim_ticks 250953957000 # Number of ticks simulated
|
||||
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 679792 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1139391 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1291700674 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272716 # Number of bytes of host memory used
|
||||
host_seconds 194.28 # Real time elapsed on the host
|
||||
host_inst_rate 352771 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 591275 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 670313887 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270496 # Number of bytes of host memory used
|
||||
host_seconds 374.38 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221362963 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
|
||||
|
@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 1575 # Tr
|
|||
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 303040 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -69,15 +67,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 501907914 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
|
||||
|
@ -147,19 +145,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
|
||||
|
@ -283,15 +281,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
|
||||
|
@ -389,12 +387,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1416644 # To
|
|||
system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 469015 # To
|
|||
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 1.961841 # Nu
|
|||
sim_ticks 1961841175000 # Number of ticks simulated
|
||||
final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1094895 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1094895 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36191186298 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308248 # Number of bytes of host memory used
|
||||
host_seconds 54.21 # Real time elapsed on the host
|
||||
host_inst_rate 1272238 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42053157352 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308880 # Number of bytes of host memory used
|
||||
host_seconds 46.65 # Real time elapsed on the host
|
||||
sim_insts 59351715 # Number of instructions simulated
|
||||
sim_ops 59351715 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory
|
||||
|
@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1351188 # To
|
|||
system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 448702 # Total number of read requests seen
|
||||
system.physmem.writeReqs 121037 # Total number of write requests seen
|
||||
system.physmem.cpureqs 572905 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 28716928 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7746368 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis
|
||||
|
@ -332,16 +333,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644
|
|||
system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 39192 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1027313 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 36463296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 36531890 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes)
|
||||
|
@ -353,23 +350,23 @@ system.membus.respLayer1.occupancy 3812357322 # La
|
|||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 341780 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 341780 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits
|
||||
|
@ -652,15 +649,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf
|
|||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.tags.replacements 41698 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy
|
||||
system.iocache.tags.replacements 41698 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
|
@ -941,16 +938,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 894 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1842377 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3534341 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 5652298 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 58955328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 137106504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 205232754 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks)
|
||||
|
@ -985,19 +982,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -1014,19 +998,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2730242 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks)
|
||||
|
@ -1059,15 +1030,15 @@ system.iobus.respLayer0.occupancy 26795000 # La
|
|||
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu0.icache.tags.replacements 920572 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.replacements 920572 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits
|
||||
|
@ -1137,15 +1108,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635
|
|||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.tags.replacements 1349865 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.replacements 1349865 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits
|
||||
|
@ -1411,15 +1382,15 @@ system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # nu
|
|||
system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 284 # number of times the context was actually changed
|
||||
system.cpu1.icache.tags.replacements 79630 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.replacements 79630 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits
|
||||
|
@ -1489,15 +1460,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608
|
|||
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.tags.replacements 40890 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.replacements 40890 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 1.918473 # Nu
|
|||
sim_ticks 1918473094000 # Number of ticks simulated
|
||||
final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 813863 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 813863 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27788392408 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306196 # Number of bytes of host memory used
|
||||
host_seconds 69.04 # Real time elapsed on the host
|
||||
host_inst_rate 948634 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 948634 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32389976926 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304780 # Number of bytes of host memory used
|
||||
host_seconds 59.23 # Real time elapsed on the host
|
||||
sim_insts 56188014 # Number of instructions simulated
|
||||
sim_ops 56188014 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory
|
||||
|
@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 443419 # To
|
|||
system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 442977 # Total number of read requests seen
|
||||
system.physmem.writeReqs 115467 # Total number of write requests seen
|
||||
system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 28350528 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7389888 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis
|
||||
|
@ -329,16 +330,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 8
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 35784972 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes)
|
||||
|
@ -350,15 +347,15 @@ system.membus.respLayer1.occupancy 3745756604 # La
|
|||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.iocache.tags.replacements 41685 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy
|
||||
system.iocache.tags.replacements 41685 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
|
@ -644,19 +641,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -673,19 +657,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2706164 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
|
@ -718,15 +689,15 @@ system.iobus.respLayer0.occupancy 23509000 # La
|
|||
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 928665 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 928665 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits
|
||||
|
@ -796,19 +767,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 336065 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 336065 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits
|
||||
|
@ -966,15 +937,15 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
|
|||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1390866 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1390866 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits
|
||||
|
@ -1112,12 +1083,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -66,14 +66,15 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To
|
|||
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
@ -49,14 +49,15 @@ system.physmem.bw_total::cpu.itb.walker 82 # To
|
|||
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 662335 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851722 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25577480180 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 396424 # Number of bytes of host memory used
|
||||
host_seconds 91.21 # Real time elapsed on the host
|
||||
host_inst_rate 691261 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 888919 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26694508777 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 395580 # Number of bytes of host memory used
|
||||
host_seconds 87.39 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
|
@ -62,14 +62,15 @@ system.physmem.bw_total::cpu0.data 3386724 # To
|
|||
system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
@ -223,27 +224,27 @@ system.realview.nvmem.bw_total::total 9 # To
|
|||
system.membus.throughput 55969561 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566366 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.l2c.tags.replacements 62242 # number of replacements
|
||||
system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 62242 # number of replacements
|
||||
system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits
|
||||
|
@ -450,23 +451,23 @@ system.cpu0.num_fp_register_writes 1428 # nu
|
|||
system.cpu0.num_mem_refs 15013057 # number of memory refs
|
||||
system.cpu0.num_load_insts 8304661 # Number of load instructions
|
||||
system.cpu0.num_store_insts 6708396 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 186586201.060505 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles
|
||||
system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 850590 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.replacements 850590 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
|
||||
|
@ -512,17 +513,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.tags.replacements 623334 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.replacements 623334 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits
|
||||
|
@ -660,18 +661,18 @@ system.cpu1.num_fp_register_writes 1352 # nu
|
|||
system.cpu1.num_mem_refs 12348580 # number of memory refs
|
||||
system.cpu1.num_load_insts 7334866 # Number of load instructions
|
||||
system.cpu1.num_store_insts 5013714 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 8315278901.051629 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles -4035324022.051629 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction -0.942843 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112102 # Nu
|
|||
sim_ticks 5112102211000 # Number of ticks simulated
|
||||
final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 878832 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22473674513 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586256 # Number of bytes of host memory used
|
||||
host_seconds 227.47 # Real time elapsed on the host
|
||||
host_inst_rate 856407 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21900233108 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 584104 # Number of bytes of host memory used
|
||||
host_seconds 233.43 # Real time elapsed on the host
|
||||
sim_insts 199908396 # Number of instructions simulated
|
||||
sim_ops 409304707 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
|
||||
|
@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 63 # To
|
|||
system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
@ -195,15 +196,15 @@ system.physmem.avgGap nan # Av
|
|||
system.membus.throughput 9632725 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 49243475 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.tags.replacements 47569 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 47569 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
|
@ -277,15 +278,15 @@ system.cpu.not_idle_fraction 0.044374 # Pe
|
|||
system.cpu.idle_fraction 0.955626 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 790522 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 790522 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
|
||||
|
@ -320,10 +321,10 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy
|
||||
|
@ -368,10 +369,10 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526
|
|||
system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
|
||||
|
@ -411,15 +412,15 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu
|
|||
system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1622027 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1622027 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits
|
||||
|
@ -466,23 +467,23 @@ system.cpu.dcache.no_allocate_misses 0 # Nu
|
|||
system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.tags.replacements 105931 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.replacements 105931 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 5.196173 # Nu
|
|||
sim_ticks 5196173457000 # Number of ticks simulated
|
||||
final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 766970 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1478526 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31067837744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586132 # Number of bytes of host memory used
|
||||
host_seconds 167.25 # Real time elapsed on the host
|
||||
host_inst_rate 457062 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 881101 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 18514311716 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 585140 # Number of bytes of host memory used
|
||||
host_seconds 280.66 # Real time elapsed on the host
|
||||
sim_insts 128277551 # Number of instructions simulated
|
||||
sim_ops 247287193 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory
|
||||
|
@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To
|
|||
system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 198391 # Total number of read requests seen
|
||||
system.physmem.writeReqs 126842 # Total number of write requests seen
|
||||
system.physmem.cpureqs 326873 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 198391 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 126842 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 198391 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 126842 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 12697024 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 8117888 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis
|
||||
|
@ -358,39 +359,31 @@ system.membus.trans_dist::MessageReq 1655 # Tr
|
|||
system.membus.trans_dist::MessageResp 1655 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 530613 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 480072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 20814912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22488073 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1351024000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 256571500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 256571500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 359320500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 359320500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer3.occupancy 3310000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.occupancy 1351024000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
@ -532,26 +525,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
|
|||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
@ -576,26 +549,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid
|
|||
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 3280192 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks)
|
||||
|
@ -1032,16 +985,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584265 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5972620 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8122 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18187 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7583194 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50696064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203753837 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 242368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 606720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 255298989 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 25046000 # Number of ticks simulated
|
||||
final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25238 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25236 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98905790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225424 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 22373 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22372 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 87684145 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225308 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 766589475 # In
|
|||
system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 29952 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
|
||||
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 396 # Tr
|
|||
system.membus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29952 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
|
||||
|
@ -307,15 +308,15 @@ system.cpu.stage3.utilization 2.663047 # Pe
|
|||
system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
|
||||
|
@ -396,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
|
||||
|
@ -410,17 +411,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 512750 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
@ -535,15 +536,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 20671000 # Number of ticks simulated
|
||||
final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25591 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25589 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 83008053 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227468 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 24570 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24568 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 79697022 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227340 # Number of bytes of host memory used
|
||||
host_seconds 0.26 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 969087127 # In
|
|||
system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 488 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 31168 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis
|
||||
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 415 # Tr
|
|||
system.membus.trans_dist::ReadResp 414 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 31168 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks)
|
||||
|
@ -511,12 +512,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 416 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
|
@ -525,15 +526,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 531250 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
|
||||
|
@ -609,17 +610,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
@ -734,15 +735,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
|
|||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101141711 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224276 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
host_inst_rate 27670 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 27667 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 140894748 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224272 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 373 # Tr
|
|||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
|
||||
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 65088 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
|
||||
|
@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
@ -300,15 +300,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
|
||||
|
@ -403,12 +403,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 374 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 11933500 # Number of ticks simulated
|
||||
final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2461163 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226156 # Number of bytes of host memory used
|
||||
host_seconds 4.85 # Real time elapsed on the host
|
||||
host_inst_rate 64 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 321705 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226036 # Number of bytes of host memory used
|
||||
host_seconds 37.09 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1008254075 # In
|
|||
system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 273 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 17472 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
|
||||
|
@ -190,10 +191,10 @@ system.membus.trans_dist::ReadReq 249 # Tr
|
|||
system.membus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17472 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
|
||||
|
@ -507,12 +508,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 249 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 376 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 546 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
|
||||
|
@ -521,15 +522,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 318000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits
|
||||
|
@ -605,17 +606,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
|
||||
|
@ -724,15 +725,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 16524000 # Number of ticks simulated
|
||||
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 252355 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 251860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1611932908 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223992 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 70 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 70 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 446596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222964 # Number of bytes of host memory used
|
||||
host_seconds 37.00 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 218 # Tr
|
|||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15680 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks)
|
||||
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 33048 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
|
||||
|
@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
|
||||
|
@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
|
||||
|
@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 218 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu
|
|||
sim_ticks 16494000 # Number of ticks simulated
|
||||
final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31208 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 112083077 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244336 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 32065 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 40006 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 115159682 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240696 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In
|
|||
system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 393 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 25152 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
|
||||
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr
|
|||
system.membus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25152 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
|
||||
|
@ -563,12 +564,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
|
||||
|
@ -577,15 +578,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 485250 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits
|
||||
|
@ -661,17 +662,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
|
||||
|
@ -795,15 +796,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu
|
|||
sim_ticks 16494000 # Number of ticks simulated
|
||||
final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 66928 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 83502 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 240363471 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244336 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 36590 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45651 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 131406771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240696 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In
|
|||
system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 393 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 25152 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
|
||||
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr
|
|||
system.membus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25152 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
|
||||
|
@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
|
||||
|
@ -532,15 +533,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 485250 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits
|
||||
|
@ -616,17 +617,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
|
||||
|
@ -750,15 +751,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
|
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu
|
|||
sim_ticks 25969000 # Number of ticks simulated
|
||||
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 220478 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 273604 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1251201624 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241012 # Number of bytes of host memory used
|
||||
host_inst_rate 229244 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 284503 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1301168988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238660 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 4565 # Number of instructions simulated
|
||||
sim_ops 5672 # Number of ops (including micro ops) simulated
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 307 # Tr
|
|||
system.membus.trans_dist::ReadResp 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22400 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks)
|
||||
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 51938 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits
|
||||
|
@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
|
||||
|
@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
|
||||
|
@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 339 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 24587000 # Number of ticks simulated
|
||||
final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 41260 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41253 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174426700 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226212 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 52979 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52966 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 223940501 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224928 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 825151503 # In
|
|||
system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 455 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 29120 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 404 # Tr
|
|||
system.membus.trans_dist::ReadResp 404 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks)
|
||||
|
@ -293,15 +294,15 @@ system.cpu.stage3.utilization 2.517539 # Pe
|
|||
system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
|
||||
|
@ -382,12 +383,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
|
||||
|
@ -396,17 +397,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 543000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
@ -521,15 +522,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 21805500 # Number of ticks simulated
|
||||
final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79844 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79828 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 337538221 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228256 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 44396 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44386 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 187676879 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228012 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 5156 # Number of instructions simulated
|
||||
sim_ops 5156 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 983238174 # In
|
|||
system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 477 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30528 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 426 # Tr
|
|||
system.membus.trans_dist::ReadResp 426 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
|
||||
|
@ -495,12 +496,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 429 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
|
||||
|
@ -509,15 +510,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 573500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits
|
||||
|
@ -593,17 +594,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
|
@ -718,15 +719,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu
|
|||
sim_ticks 31633000 # Number of ticks simulated
|
||||
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 482351 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 481309 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2613274672 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225064 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 304637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 304230 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1653175117 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224940 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 388 # Tr
|
|||
system.membus.trans_dist::ReadResp 388 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28096 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
|
||||
|
@ -83,15 +83,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 63266 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
|
||||
|
@ -161,17 +161,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
@ -286,15 +286,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
|
||||
|
@ -389,12 +389,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 390 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu
|
|||
sim_ticks 18469500 # Number of ticks simulated
|
||||
final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 54927 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 54916 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 175080000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224296 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 100626 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100602 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 320728752 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223260 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1195484447 # In
|
|||
system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 446 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 28544 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
|
||||
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 399 # Tr
|
|||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks)
|
||||
|
@ -493,12 +494,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
|
||||
|
@ -507,15 +508,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 590750 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits
|
||||
|
@ -591,17 +592,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
|
||||
|
@ -719,15 +720,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 20802500 # Number of ticks simulated
|
||||
final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 39959 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39952 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155990706 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232536 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_inst_rate 86492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 86452 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 337526822 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231936 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 889123903 # In
|
|||
system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 423 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 27072 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis
|
||||
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 342 # Tr
|
|||
system.membus.trans_dist::ReadResp 342 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
|
||||
|
@ -275,15 +276,15 @@ system.cpu.stage3.utilization 2.343412 # Pe
|
|||
system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
|
||||
|
@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 345 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
|
||||
|
@ -378,17 +379,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 489750 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
@ -506,15 +507,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
||||
|
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 27800000 # Number of ticks simulated
|
||||
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 413138 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 412367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2148212772 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231400 # Number of bytes of host memory used
|
||||
host_inst_rate 441877 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 441389 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2300957264 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230904 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 308 # Tr
|
|||
system.membus.trans_dist::ReadResp 308 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 24896 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
|
||||
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 55600 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
|
||||
|
@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
|
||||
|
@ -374,12 +374,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 311 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 19639500 # Number of ticks simulated
|
||||
final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 28578 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51768 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 104294046 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245432 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_inst_rate 30549 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 55338 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 111488682 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243516 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 892894422 # In
|
|||
system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 417 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 417 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 26624 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
|
||||
|
@ -195,11 +196,9 @@ system.membus.trans_dist::ReadExReq 77 # Tr
|
|||
system.membus.trans_dist::ReadExResp 77 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 26624 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -478,12 +477,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 342 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 550 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 287 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 837 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
|
||||
|
@ -492,15 +491,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 463250 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits
|
||||
|
@ -576,17 +575,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
|
@ -704,15 +703,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 28358000 # Number of ticks simulated
|
||||
final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 90736 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 477859669 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289160 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 186481 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 337520 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 981039317 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241472 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
|
||||
|
@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 79 # Tr
|
|||
system.membus.trans_dist::ReadExResp 79 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 23104 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
@ -69,15 +67,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 56716 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
|
||||
|
@ -147,17 +145,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
@ -272,15 +270,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
|
||||
|
@ -375,12 +373,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 283 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
|
|||
sim_ticks 24404000 # Number of ticks simulated
|
||||
final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52847 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52845 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101181200 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228064 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_inst_rate 780 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 780 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1494307 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227936 # Number of bytes of host memory used
|
||||
host_seconds 16.33 # Real time elapsed on the host
|
||||
sim_insts 12745 # Number of instructions simulated
|
||||
sim_ops 12745 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1636453040 # In
|
|||
system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 974 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 974 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 62336 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis
|
||||
|
@ -205,10 +206,10 @@ system.membus.trans_dist::ReadReq 828 # Tr
|
|||
system.membus.trans_dist::ReadResp 828 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 146 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 62336 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks)
|
||||
|
@ -452,41 +453,7 @@ system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::total 10798 # Type of FU issued
|
||||
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IntAlu 14327 65.73% 65.75% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IntMult 2 0.01% 65.76% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IntDiv 0 0.00% 65.76% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatMult 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdMult 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdShift 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::MemRead 5217 23.94% 89.71% # Type of FU issued
|
||||
system.cpu.iq.FU_type::MemWrite 2242 10.29% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type::total 21796 # Type of FU issued
|
||||
system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.rate 0.446557 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested
|
||||
|
@ -662,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 830 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1252 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1952 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks)
|
||||
|
@ -676,17 +643,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 1029500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements::0 6 # number of replacements
|
||||
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.icache.tags.replacements::total 6 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements::0 6 # number of replacements
|
||||
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.icache.tags.replacements::total 6 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits
|
||||
|
@ -762,19 +729,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009464 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003623 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
@ -889,17 +856,17 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements::0 0 # number of replacements
|
||||
system.cpu.dcache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.dcache.tags.replacements::total 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements::0 0 # number of replacements
|
||||
system.cpu.dcache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.dcache.tags.replacements::total 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
|
|||
sim_ticks 27282000 # Number of ticks simulated
|
||||
final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 50184 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50180 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 90285398 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232468 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_inst_rate 96636 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 96628 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 173854426 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231852 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 699068983 # In
|
|||
system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 436 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 27904 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis
|
||||
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 351 # Tr
|
|||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27840 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
|
||||
|
@ -275,15 +276,15 @@ system.cpu.stage3.utilization 5.274443 # Pe
|
|||
system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
|
||||
|
@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 354 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 600 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 876 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
||||
|
@ -378,17 +379,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 507000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
@ -503,15 +504,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
|
||||
|
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
|
|||
sim_ticks 26524500 # Number of ticks simulated
|
||||
final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52714 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52709 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 96835127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234512 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
host_inst_rate 95044 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174603061 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232868 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
|
||||
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 808309299 # In
|
|||
system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 482 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30848 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
|
||||
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 399 # Tr
|
|||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30848 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
|
||||
|
@ -472,12 +473,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 401 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
|
||||
|
@ -486,15 +487,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 570000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits
|
||||
|
@ -570,17 +571,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
@ -695,15 +696,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
|
||||
|
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu
|
|||
sim_ticks 41368000 # Number of ticks simulated
|
||||
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 479032 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 478642 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1304958787 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231320 # Number of bytes of host memory used
|
||||
host_inst_rate 554996 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 554737 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1512828488 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230824 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 331 # Tr
|
|||
system.membus.trans_dist::ReadResp 331 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 26624 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
|
||||
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 82736 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
|
||||
|
@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
|
||||
|
@ -375,12 +375,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 333 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
||||
|
|
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -4,9 +4,9 @@ sim_seconds 0.000653 # Nu
|
|||
sim_ticks 652606500 # Number of ticks simulated
|
||||
final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 176079756 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355636 # Number of bytes of host memory used
|
||||
host_seconds 3.71 # Real time elapsed on the host
|
||||
host_tick_rate 158104978 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355504 # Number of bytes of host memory used
|
||||
host_seconds 4.13 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory
|
||||
|
@ -84,41 +84,41 @@ system.membus.trans_dist::UpgradeReq 57414 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 48586 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3092 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1086481 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 43.9 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 47.7 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 13254 # number of replacements
|
||||
system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 149317 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 13254 # number of replacements
|
||||
system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 149317 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits
|
||||
|
@ -690,24 +690,24 @@ system.toL2Bus.trans_dist::UpgradeReq 28719 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 13912273 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks)
|
||||
|
@ -731,15 +731,15 @@ system.toL2Bus.respLayer7.utilization 24.2 # La
|
|||
system.cpu0.num_reads 98977 # number of read accesses completed
|
||||
system.cpu0.num_writes 53590 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.l1c.tags.replacements 21970 # number of replacements
|
||||
system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use
|
||||
system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
|
||||
system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks.
|
||||
system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks.
|
||||
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor
|
||||
system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.tags.replacements 21970 # number of replacements
|
||||
system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use
|
||||
system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
|
||||
system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks.
|
||||
system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks.
|
||||
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor
|
||||
system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits
|
||||
system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits
|
||||
system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits
|
||||
|
@ -846,15 +846,15 @@ system.cpu0.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu1.num_reads 99824 # number of read accesses completed
|
||||
system.cpu1.num_writes 53636 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.l1c.tags.replacements 22223 # number of replacements
|
||||
system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use
|
||||
system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks.
|
||||
system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks.
|
||||
system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks.
|
||||
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor
|
||||
system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.tags.replacements 22223 # number of replacements
|
||||
system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use
|
||||
system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks.
|
||||
system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks.
|
||||
system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks.
|
||||
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor
|
||||
system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits
|
||||
system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits
|
||||
system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits
|
||||
|
@ -961,15 +961,15 @@ system.cpu1.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu2.num_reads 99336 # number of read accesses completed
|
||||
system.cpu2.num_writes 53403 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.l1c.tags.replacements 22214 # number of replacements
|
||||
system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use
|
||||
system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks.
|
||||
system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks.
|
||||
system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks.
|
||||
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor
|
||||
system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.tags.replacements 22214 # number of replacements
|
||||
system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use
|
||||
system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks.
|
||||
system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks.
|
||||
system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks.
|
||||
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor
|
||||
system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits
|
||||
system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits
|
||||
system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits
|
||||
|
@ -1076,15 +1076,15 @@ system.cpu2.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53536 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.l1c.tags.replacements 22464 # number of replacements
|
||||
system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use
|
||||
system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks.
|
||||
system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks.
|
||||
system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks.
|
||||
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor
|
||||
system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.tags.replacements 22464 # number of replacements
|
||||
system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use
|
||||
system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks.
|
||||
system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks.
|
||||
system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks.
|
||||
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor
|
||||
system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits
|
||||
system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits
|
||||
system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits
|
||||
|
@ -1191,15 +1191,15 @@ system.cpu3.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu4.num_reads 99830 # number of read accesses completed
|
||||
system.cpu4.num_writes 54064 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.l1c.tags.replacements 22082 # number of replacements
|
||||
system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use
|
||||
system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks.
|
||||
system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks.
|
||||
system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks.
|
||||
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor
|
||||
system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.tags.replacements 22082 # number of replacements
|
||||
system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use
|
||||
system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks.
|
||||
system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks.
|
||||
system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks.
|
||||
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor
|
||||
system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits
|
||||
system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits
|
||||
system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits
|
||||
|
@ -1306,15 +1306,15 @@ system.cpu4.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu5.num_reads 99630 # number of read accesses completed
|
||||
system.cpu5.num_writes 53500 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.l1c.tags.replacements 22051 # number of replacements
|
||||
system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use
|
||||
system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks.
|
||||
system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks.
|
||||
system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks.
|
||||
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor
|
||||
system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.tags.replacements 22051 # number of replacements
|
||||
system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use
|
||||
system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks.
|
||||
system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks.
|
||||
system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks.
|
||||
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor
|
||||
system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits
|
||||
system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits
|
||||
system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits
|
||||
|
@ -1421,15 +1421,15 @@ system.cpu5.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu6.num_reads 99897 # number of read accesses completed
|
||||
system.cpu6.num_writes 53584 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.l1c.tags.replacements 22385 # number of replacements
|
||||
system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use
|
||||
system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks.
|
||||
system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
|
||||
system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks.
|
||||
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor
|
||||
system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.tags.replacements 22385 # number of replacements
|
||||
system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use
|
||||
system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks.
|
||||
system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
|
||||
system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks.
|
||||
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor
|
||||
system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits
|
||||
system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits
|
||||
system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits
|
||||
|
@ -1536,15 +1536,15 @@ system.cpu6.l1c.no_allocate_misses 0 # Nu
|
|||
system.cpu7.num_reads 99207 # number of read accesses completed
|
||||
system.cpu7.num_writes 53401 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.l1c.tags.replacements 22143 # number of replacements
|
||||
system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use
|
||||
system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks.
|
||||
system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks.
|
||||
system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks.
|
||||
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor
|
||||
system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy
|
||||
system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy
|
||||
system.cpu7.l1c.tags.replacements 22143 # number of replacements
|
||||
system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use
|
||||
system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks.
|
||||
system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks.
|
||||
system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks.
|
||||
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor
|
||||
system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy
|
||||
system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy
|
||||
system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits
|
||||
system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits
|
||||
system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits
|
||||
|
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 29067628326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231288 # Number of bytes of host memory used
|
||||
host_seconds 3.44 # Real time elapsed on the host
|
||||
host_tick_rate 12102739985 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228608 # Number of bytes of host memory used
|
||||
host_seconds 8.26 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
|
||||
system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
|
||||
|
@ -15,14 +15,15 @@ system.physmem.bw_read::cpu 2133311360 # To
|
|||
system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3333300 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 3333300 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 213331136 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis
|
||||
|
@ -169,18 +170,15 @@ system.physmem.avgGap 30000.29 # Av
|
|||
system.membus.throughput 2133311360 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
|
||||
system.membus.pkt_count_system.monitor-master 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 213331136 # Total data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
|
||||
system.cpu.numPackets 3333300 # Number of packets generated
|
||||
system.cpu.numRetries 0 # Number of retries
|
||||
system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
|
||||
system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
|
||||
|
@ -519,5 +517,8 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi
|
|||
system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
|
||||
system.cpu.numPackets 3333300 # Number of packets generated
|
||||
system.cpu.numRetries 0 # Number of retries
|
||||
system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 14083896029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231304 # Number of bytes of host memory used
|
||||
host_seconds 7.10 # Real time elapsed on the host
|
||||
host_tick_rate 8032030639 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228596 # Number of bytes of host memory used
|
||||
host_seconds 12.45 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
|
||||
|
@ -26,18 +26,15 @@ system.membus.trans_dist::ReadReq 1 # Tr
|
|||
system.membus.trans_dist::ReadResp 1 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
|
||||
system.membus.pkt_count_system.monitor-master 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 213329216 # Total data (bytes)
|
||||
system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
|
||||
system.cpu.numPackets 3333269 # Number of packets generated
|
||||
system.cpu.numRetries 1 # Number of retries
|
||||
system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
|
||||
system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
|
||||
|
@ -376,5 +373,8 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% #
|
|||
system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
|
||||
system.cpu.numPackets 3333269 # Number of packets generated
|
||||
system.cpu.numRetries 1 # Number of retries
|
||||
system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
Loading…
Reference in a new issue