gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
Andreas Hansson b63631536d stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00

435 lines
49 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.567335 # Number of seconds simulated
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1598767 # Simulator instruction rate (inst/s)
host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2275187152 # Simulator tick rate (ticks/s)
host_mem_usage 229960 # Number of bytes of host memory used
host_seconds 249.36 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 809285 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4032 # Transaction distribution
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 459136 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754490 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.write_hits 73520730 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520765 # DTB write accesses
system.cpu.dtb.data_hits 168275220 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275276 # DTB accesses
system.cpu.itb.fetch_hits 398664666 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664839 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 1134670186 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664609 # Number of instructions committed
system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365921 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275276 # number of memory refs
system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1134670186 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.tags.replacements 1769 # number of replacements
system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
system.cpu.icache.overall_misses::total 3673 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 764 # number of replacements
system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------