b63631536d
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
935 lines
106 KiB
Plaintext
935 lines
106 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.631883 # Number of seconds simulated
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sim_ticks 631883288500 # Number of ticks simulated
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final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 177291 # Simulator instruction rate (inst/s)
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host_op_rate 177291 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 61450789 # Simulator tick rate (ticks/s)
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host_mem_usage 236780 # Number of bytes of host memory used
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host_seconds 10282.75 # Real time elapsed on the host
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sim_insts 1823043370 # Number of instructions simulated
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sim_ops 1823043370 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 30295168 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30471232 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 473362 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 476113 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 278634 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 47944246 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 48222880 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 278634 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 278634 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 6776745 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6776745 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 6776745 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 476114 # Total number of read requests accepted by DRAM controller
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system.physmem.writeReqs 66908 # Total number of write requests accepted by DRAM controller
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system.physmem.readBursts 476114 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.writeBursts 66908 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
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system.physmem.bytesRead 30471232 # Total number of bytes read from memory
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system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 29852 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 29789 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 29768 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 29869 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 29858 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 29771 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 29890 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 29915 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 29796 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 29583 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 29509 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 29637 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 4160 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 4142 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 4099 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 4262 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 4226 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 4233 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 4335 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 4247 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 4241 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 4100 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 631883258500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 476114 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 66908 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 408378 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 66892 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 126 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 166584 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 208.562071 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 137.103843 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 536.299000 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 52740 31.66% 31.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 42613 25.58% 57.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 39946 23.98% 81.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 25368 15.23% 96.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 277 0.17% 96.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 122 0.07% 96.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 95 0.06% 96.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 87 0.05% 96.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 83 0.05% 96.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 94 0.06% 96.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 111 0.07% 96.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 115 0.07% 97.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 83 0.05% 97.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-961 77 0.05% 97.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 81 0.05% 97.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 76 0.05% 97.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 74 0.04% 97.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 77 0.05% 97.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 82 0.05% 97.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 2 0.00% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1729 1 0.00% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2049 3 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3201 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3264-3265 2 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 166584 # Bytes accessed per row activation
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system.physmem.totQLat 1351239750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 14292404750 # Sum of mem lat for all requests
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system.physmem.totBusLat 2380120000 # Total cycles spent in databus access
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system.physmem.totBankLat 10561045000 # Total cycles spent in bank access
|
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system.physmem.avgQLat 2838.60 # Average queueing delay per request
|
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system.physmem.avgBankLat 22185.95 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 30024.55 # Average memory access latency
|
|
system.physmem.avgRdBW 48.22 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 48.22 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.43 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.02 # Average read queue length over time
|
|
system.physmem.avgWrQLen 11.01 # Average write queue length over time
|
|
system.physmem.readRowHits 326147 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 50200 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 1163642.10 # Average gap between requests
|
|
system.membus.throughput 54999625 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 409258 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 409257 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66856 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66856 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019135 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1019135 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 34753344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 34753344 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4527448500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
system.cpu.branchPred.lookups 388901077 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 255997466 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 25785874 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 315302493 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 258353491 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 81.938296 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 57247417 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 6895 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 522159380 # DTB read hits
|
|
system.cpu.dtb.read_misses 590851 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 522750231 # DTB read accesses
|
|
system.cpu.dtb.write_hits 283002528 # DTB write hits
|
|
system.cpu.dtb.write_misses 50162 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 283052690 # DTB write accesses
|
|
system.cpu.dtb.data_hits 805161908 # DTB hits
|
|
system.cpu.dtb.data_misses 641013 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 805802921 # DTB accesses
|
|
system.cpu.itb.fetch_hits 394748041 # ITB hits
|
|
system.cpu.itb.fetch_misses 630 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 394748671 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 39 # Number of system calls
|
|
system.cpu.numCycles 1263766578 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 409917284 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 3274493634 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 388901077 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 315600908 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 630100236 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 157853545 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 75868728 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 6965 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 394748041 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 11243258 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1247472116 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.624903 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.139302 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 617371880 49.49% 49.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 57447684 4.61% 54.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 43286408 3.47% 57.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 71838123 5.76% 63.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 129156368 10.35% 73.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 46178870 3.70% 77.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 41219816 3.30% 80.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 7663689 0.61% 81.30% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 233309278 18.70% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1247472116 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.307732 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.591059 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 438201536 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 62209215 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 606414230 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9080438 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 131566697 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 31709739 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 12402 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 3193700667 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 46294 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 131566697 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 467502237 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 27351671 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 28189 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 585846018 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 35177304 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 3094945067 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 15191 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 109722880 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 743716097 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 351305913 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 69009362 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 8819654 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2623113984 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 93 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2159995607 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 17916537 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 800006156 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 726205656 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 54 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1247472116 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.731498 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.803359 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 450995748 36.15% 36.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 196797874 15.78% 51.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 251286832 20.14% 72.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 120757727 9.68% 81.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 104717605 8.39% 90.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 79196335 6.35% 96.50% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 24309118 1.95% 98.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 17642931 1.41% 99.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1767946 0.14% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1247472116 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 1146304 3.11% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 25641829 69.66% 72.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 10023004 27.23% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1234267096 57.14% 57.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 17095 0.00% 57.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 27851364 1.29% 58.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 589311123 27.28% 86.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 293086828 13.57% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2159995607 # Type of FU issued
|
|
system.cpu.iq.rate 1.709173 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 36811137 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.017042 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5471089482 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 3335131409 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1989836434 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 151101522 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 88062076 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 73609987 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2119354134 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 77449858 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 62153092 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 232646071 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 31940 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 75814 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 140511017 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 4421 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2886 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 131566697 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 13318869 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 540046 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2986589244 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 731786 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 743716097 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 351305913 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 134266 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1522 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 75814 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 25780444 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 27789 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 25808233 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2065907774 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 522750367 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 94087833 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 363475167 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 805803501 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 277598296 # Number of branches executed
|
|
system.cpu.iew.exec_stores 283053134 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.634723 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2065776472 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2063446421 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1180901001 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1753223374 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.632775 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.673560 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 960640976 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 25773841 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1115905419 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.800321 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.507651 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 496848865 44.52% 44.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 228666687 20.49% 65.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 119877587 10.74% 75.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 58838951 5.27% 81.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 50501288 4.53% 85.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 24162159 2.17% 87.72% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19119877 1.71% 89.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 16606359 1.49% 90.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 101283646 9.08% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1115905419 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 721864922 # Number of memory references committed
|
|
system.cpu.commit.loads 511070026 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 266706457 # Number of branches committed
|
|
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 101283646 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3978613943 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6070825883 # The number of ROB writes
|
|
system.cpu.timesIdled 341889 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 16294462 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.693218 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.693218 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.442548 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.442548 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2627733458 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1496469824 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 78811377 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 52661114 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 165896459 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 1470295 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20089 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159776 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3179865 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104184384 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 104827200 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 15605000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 8334 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 394735107 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 394735107 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 394735107 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 12934 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 12934 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 12934 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 12934 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 12934 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 12934 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 381722499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 381722499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 381722499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 381722499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 381722499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 381722499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 394748041 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 394748041 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 394748041 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 394748041 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 394748041 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 394748041 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29513.104917 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 29513.104917 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 29513.104917 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 29513.104917 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 646 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 49.692308 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2889 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2889 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2889 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2889 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2889 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2889 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10045 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 10045 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 10045 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 10045 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 10045 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 10045 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 280085749 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 280085749 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 280085749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 280085749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 280085749 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 280085749 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27883.100946 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27883.100946 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 443335 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 1328.456107 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.040541 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.956023 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 7293 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1053744 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1061037 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 95986 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 95986 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 7293 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1058533 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1065826 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 7293 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1058533 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1065826 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2752 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 406506 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 409258 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66856 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66856 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2752 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 473362 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 476114 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2752 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 473362 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 476114 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197100250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29768533500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 29965633750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5039202250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5039202250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 197100250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 34807735750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 35004836000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 197100250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 34807735750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 35004836000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10045 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460250 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1470295 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 95986 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 95986 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 71645 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 71645 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 10045 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1531895 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1541940 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 10045 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1531895 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1541940 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.273967 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278381 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.278351 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933157 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.933157 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.273967 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.309004 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.308776 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.273967 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.309004 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.308776 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71620.730378 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73230.243834 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73219.420879 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75373.971670 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75373.971670 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71620.730378 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73533.016486 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 73521.963227 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71620.730378 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73533.016486 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 73521.963227 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66908 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2752 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406506 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 409258 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66856 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66856 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2752 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 473362 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 476114 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 473362 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 476114 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162299250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24552049500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24714348750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4233681750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4233681750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162299250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28785731250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 28948030500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162299250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28785731250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 28948030500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278351 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933157 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933157 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.308776 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.308776 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58975.018169 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60397.754277 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60388.187280 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63325.382165 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63325.382165 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1527799 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 209733012 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 667806372 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 667806372 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 667806372 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 667806372 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1925786 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1925786 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1061884 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1061884 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2987670 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2987670 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2987670 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2987670 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 76327323000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 76327323000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 44999711104 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 44999711104 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 121327034104 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 121327034104 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 121327034104 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 121327034104 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 459999146 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 459999146 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 25 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 25 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 670794042 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 670794042 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 670794042 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 670794042 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004186 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004186 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.004454 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.004454 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.004454 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.004454 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39634.374224 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 39634.374224 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42377.238101 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 42377.238101 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 40609.248714 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 40609.248714 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 18768 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.086455 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 95986 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 95986 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465536 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 465536 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990239 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 990239 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1455775 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1455775 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1455775 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1455775 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460250 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1460250 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71645 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 71645 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1531895 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1531895 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1531895 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1531895 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41766827000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 41766827000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5159100250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5159100250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46925927250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 46925927250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46925927250 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 46925927250 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28602.518062 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28602.518062 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72009.215577 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72009.215577 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|