b63631536d
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
394 lines
45 KiB
Plaintext
394 lines
45 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000041 # Number of seconds simulated
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sim_ticks 41368000 # Number of ticks simulated
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final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 554996 # Simulator instruction rate (inst/s)
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host_op_rate 554737 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1512828488 # Simulator tick rate (ticks/s)
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host_mem_usage 230824 # Number of bytes of host memory used
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host_seconds 0.03 # Real time elapsed on the host
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sim_insts 15162 # Number of instructions simulated
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sim_ops 15162 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 643589248 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 331 # Transaction distribution
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system.membus.trans_dist::ReadResp 331 # Transaction distribution
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system.membus.trans_dist::ReadExReq 85 # Transaction distribution
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system.membus.trans_dist::ReadExResp 85 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 26624 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 82736 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 15162 # Number of instructions committed
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system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 385 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
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system.cpu.num_int_insts 12219 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
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system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 3683 # number of memory refs
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system.cpu.num_load_insts 2231 # Number of load instructions
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system.cpu.num_store_insts 1452 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 82736 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.tags.replacements 0 # number of replacements
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system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
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system.cpu.icache.overall_hits::total 14928 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
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system.cpu.icache.overall_misses::total 280 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 0 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
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system.cpu.l2cache.overall_hits::total 2 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
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system.cpu.l2cache.overall_misses::total 416 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 3529 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 138 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|