b63631536d
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
1407 lines
162 KiB
Plaintext
1407 lines
162 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.860201 # Number of seconds simulated
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sim_ticks 1860200687500 # Number of ticks simulated
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final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 95880 # Simulator instruction rate (inst/s)
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host_op_rate 95880 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3366492305 # Simulator tick rate (ticks/s)
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host_mem_usage 308824 # Number of bytes of host memory used
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host_seconds 552.56 # Real time elapsed on the host
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sim_insts 52979577 # Number of instructions simulated
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sim_ops 52979577 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller
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system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller
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system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
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system.physmem.bytesRead 28495552 # Total number of bytes read from memory
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system.physmem.bytesWritten 7515968 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q
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system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
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system.physmem.totGap 1860195209000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 445243 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 117437 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation
|
|
system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 2225940000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 5135405000 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 13733.29 # Average queueing delay per request
|
|
system.physmem.avgBankLat 11535.36 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 30268.66 # Average memory access latency
|
|
system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.15 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.01 # Average read queue length over time
|
|
system.physmem.avgWrQLen 9.67 # Average write queue length over time
|
|
system.physmem.readRowHits 430049 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 94886 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3305955.80 # Average gap between requests
|
|
system.membus.throughput 19401806 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 295958 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295878 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 117437 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 178 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 178 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 156851 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 156851 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 80 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 36055668 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 13856452 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9922890 # DTB read hits
|
|
system.cpu.dtb.read_misses 41426 # DTB read misses
|
|
system.cpu.dtb.read_acv 537 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 941977 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6601888 # DTB write hits
|
|
system.cpu.dtb.write_misses 10414 # DTB write misses
|
|
system.cpu.dtb.write_acv 409 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 338180 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16524778 # DTB hits
|
|
system.cpu.dtb.data_misses 51840 # DTB misses
|
|
system.cpu.dtb.data_acv 946 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1280157 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1306702 # ITB hits
|
|
system.cpu.itb.fetch_misses 37996 # ITB misses
|
|
system.cpu.itb.fetch_acv 1078 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1344698 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 120724090 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued
|
|
system.cpu.iq.rate 0.470686 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3525562 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 8925380 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6627529 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.466818 # Inst execution rate
|
|
system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 27713014 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56170363 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15470219 # Number of memory references committed
|
|
system.cpu.commit.loads 9092306 # Number of loads committed
|
|
system.cpu.commit.membars 226376 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8439998 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52019946 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740578 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 141757103 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 128582546 # The number of ROB writes
|
|
system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52979577 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated
|
|
system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 73899188 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 40322867 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 166085 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167427 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.iobus.throughput 1454551 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 2705756 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 1009263 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7487431 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 7487431 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7487431 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1065872 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1065872 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1065872 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1065872 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1065872 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1065872 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14976021459 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 14976021459 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 14976021459 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 14976021459 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 14976021459 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 14976021459 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 8553303 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8553303 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 8553303 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8553303 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 8553303 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8553303 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124615 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.124615 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.124615 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.124615 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.124615 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.124615 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14050.487731 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14050.487731 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14050.487731 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14050.487731 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 8372 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 45.010753 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55880 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 55880 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 55880 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 55880 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 55880 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 55880 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009992 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1009992 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1009992 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1009992 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1009992 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1009992 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12273344851 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12273344851 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12273344851 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12273344851 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12273344851 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12273344851 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118082 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.118082 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.118082 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12151.922838 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12151.922838 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 338298 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 840831 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 840831 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 185623 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 185623 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 994809 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1012411 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2007220 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 994809 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1012411 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2007220 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 273792 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 288856 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115439 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 115439 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389231 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404295 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389231 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404295 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1289741743 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17221594730 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18511336473 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285497 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 285497 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9397410357 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9397410357 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1289741743 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 26619005087 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 27908746830 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1289741743 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 26619005087 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 27908746830 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009873 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1100580 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2110453 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 840831 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 840831 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 301062 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 301062 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1009873 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1401642 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2411515 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1009873 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1401642 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2411515 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014917 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248771 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.136869 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383439 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383439 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014917 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277696 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014917 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277696 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 85617.481612 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62900.284632 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 64084.999006 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7513.078947 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7513.078947 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81405.853802 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81405.853802 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69030.650466 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69030.650466 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 75925 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 75925 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273792 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 288855 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115439 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115439 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389231 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404294 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389231 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404294 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1098682007 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13807789270 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14906471277 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7972002643 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7972002643 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1098682007 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21779791913 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 22878473920 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1098682007 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21779791913 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 22878473920 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333925000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333925000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882616000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882616000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216541000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216541000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248771 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136869 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383439 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383439 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.167651 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.167651 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72939.122817 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50431.675396 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51605.377359 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69058.140169 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1401048 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 186169 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 11406177 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11406177 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 11406177 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11406177 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1806828 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1806828 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1943975 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1943975 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22707 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22707 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3750803 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 840831 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191976 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1909
|
|
system.cpu.kern.mode_good::user 1739
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
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