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test: update stats

Browse source 
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
This commit is contained in:
Steve Reinhardt 2013-10-16 10:44:12 -04:00
parent b10ff075b1
commit 10e6450120
140 changed files with 10571 additions and 10525 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -101,6 +101,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@ -544,6 +545,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

4
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 10:33:13
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 16 2013 01:34:33
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second

18
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.902739 # Nu
sim_ticks 1902738973500 # Number of ticks simulated
final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 97410 # Simulator instruction rate (inst/s)
host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3267297836 # Simulator tick rate (ticks/s)
host_mem_usage 312988 # Number of bytes of host memory used
host_seconds 582.36 # Real time elapsed on the host
host_inst_rate 132013 # Simulator instruction rate (inst/s)
host_op_rate 132013 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4427958303 # Simulator tick rate (ticks/s)
host_mem_usage 313120 # Number of bytes of host memory used
host_seconds 429.71 # Real time elapsed on the host
sim_insts 56727331 # Number of instructions simulated
sim_ops 56727331 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory
@ -867,8 +867,8 @@ system.cpu0.rename.IQFullEvents 638131 # Nu
system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 71847381 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 384293 # Number of floating rename lookups
system.cpu0.rename.int_rename_lookups 72093935 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 128190 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed
@ -1552,8 +1552,8 @@ system.cpu1.rename.IQFullEvents 55937 # Nu
system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 12790175 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 140614 # Number of floating rename lookups
system.cpu1.rename.int_rename_lookups 12872049 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 52940 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed

1
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -101,6 +101,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

4
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 10:33:00
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 16 2013 01:34:33
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second

14
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.860201 # Nu
sim_ticks 1860200687500 # Number of ticks simulated
final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 95880 # Simulator instruction rate (inst/s)
host_op_rate 95880 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3366492305 # Simulator tick rate (ticks/s)
host_mem_usage 308824 # Number of bytes of host memory used
host_seconds 552.56 # Real time elapsed on the host
host_inst_rate 133673 # Simulator instruction rate (inst/s)
host_op_rate 133673 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4693486883 # Simulator tick rate (ticks/s)
host_mem_usage 310052 # Number of bytes of host memory used
host_seconds 396.34 # Real time elapsed on the host
sim_insts 52979577 # Number of instructions simulated
sim_ops 52979577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
@ -557,8 +557,8 @@ system.cpu.rename.IQFullEvents 505660 # Nu
system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 79531258 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed

1
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
View file

@ -259,6 +259,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

4
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 10:34:17
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 16 2013 01:34:47
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second

14
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.842705 # Nu
sim_ticks 1842705252000 # Number of ticks simulated
final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 308319 # Simulator instruction rate (inst/s)
host_op_rate 308319 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7821132493 # Simulator tick rate (ticks/s)
host_mem_usage 307864 # Number of bytes of host memory used
host_seconds 235.61 # Real time elapsed on the host
host_inst_rate 260475 # Simulator instruction rate (inst/s)
host_op_rate 260475 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6607474809 # Simulator tick rate (ticks/s)
host_mem_usage 309028 # Number of bytes of host memory used
host_seconds 278.88 # Real time elapsed on the host
sim_insts 72641883 # Number of instructions simulated
sim_ops 72641883 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory
@ -1513,8 +1513,8 @@ system.cpu2.rename.IQFullEvents 231189 # Nu
system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 43768405 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 162967 # Number of floating rename lookups
system.cpu2.rename.int_rename_lookups 43874902 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 52705 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed

1
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -127,6 +127,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 08:14:57
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:31:27
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second

14
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.524310 # Nu
sim_ticks 2524309551500 # Number of ticks simulated
final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 67450 # Simulator instruction rate (inst/s)
host_op_rate 86789 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2823365435 # Simulator tick rate (ticks/s)
host_mem_usage 397608 # Number of bytes of host memory used
host_seconds 894.08 # Real time elapsed on the host
host_inst_rate 55803 # Simulator instruction rate (inst/s)
host_op_rate 71803 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2335855340 # Simulator tick rate (ticks/s)
host_mem_usage 401408 # Number of bytes of host memory used
host_seconds 1080.68 # Real time elapsed on the host
sim_insts 60305560 # Number of instructions simulated
sim_ops 77596391 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
@ -758,8 +758,8 @@ system.cpu.rename.LSQFullEvents 4066422 # Nu
system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed

4
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -25,7 +25,7 @@ load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem
memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@ -127,6 +127,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@ -602,6 +603,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 07:58:48
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:18:35
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second

54
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

@ -4,31 +4,13 @@ sim_seconds 1.104038 # Nu
sim_ticks 1104038330000 # Number of ticks simulated
final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 67767 # Simulator instruction rate (inst/s)
host_op_rate 87238 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1214516577 # Simulator tick rate (ticks/s)
host_mem_usage 404472 # Number of bytes of host memory used
host_seconds 909.04 # Real time elapsed on the host
host_inst_rate 65967 # Simulator instruction rate (inst/s)
host_op_rate 84921 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1182267512 # Simulator tick rate (ticks/s)
host_mem_usage 404512 # Number of bytes of host memory used
host_seconds 933.83 # Real time elapsed on the host
sim_insts 61602211 # Number of instructions simulated
sim_ops 79302243 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
@ -485,6 +467,24 @@ system.physmem.writeRowHits 98940 # Nu
system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes
system.physmem.avgGap 155904.23 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 62410733 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 7306749 # Transaction distribution
system.membus.trans_dist::ReadResp 7306749 # Transaction distribution
@ -1252,8 +1252,8 @@ system.cpu0.rename.LSQFullEvents 1152507 # Nu
system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 175756522 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 34236 # Number of floating rename lookups
system.cpu0.rename.int_rename_lookups 161860177 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 4025 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed
@ -1823,8 +1823,8 @@ system.cpu1.rename.LSQFullEvents 3042854 # Nu
system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 302462653 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups
system.cpu1.rename.int_rename_lookups 280703259 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 6508 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed

3
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -25,7 +25,7 @@ load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem
memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@ -127,6 +127,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 07:59:33
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:15:54
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second

38
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

@ -4,25 +4,13 @@ sim_seconds 2.524310 # Nu
sim_ticks 2524309551500 # Number of ticks simulated
final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66090 # Simulator instruction rate (inst/s)
host_op_rate 85039 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2766442256 # Simulator tick rate (ticks/s)
host_mem_usage 401396 # Number of bytes of host memory used
host_seconds 912.48 # Real time elapsed on the host
host_inst_rate 65403 # Simulator instruction rate (inst/s)
host_op_rate 84155 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2737677908 # Simulator tick rate (ticks/s)
host_mem_usage 401408 # Number of bytes of host memory used
host_seconds 922.06 # Real time elapsed on the host
sim_insts 60305560 # Number of instructions simulated
sim_ops 77596391 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
@ -440,6 +428,18 @@ system.physmem.writeRowHits 94229 # Nu
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
system.physmem.avgGap 158662.04 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54917647 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
@ -713,8 +713,8 @@ system.cpu.rename.LSQFullEvents 4066422 # Nu
system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed

3
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
View file

@ -25,7 +25,7 @@ load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@ -347,6 +347,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 09:26:23
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:10:22
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second

38
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
View file

@ -4,13 +4,25 @@ sim_seconds 2.403596 # Nu
sim_ticks 2403595690000 # Number of ticks simulated
final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 160402 # Simulator instruction rate (inst/s)
host_op_rate 206018 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6390741250 # Simulator tick rate (ticks/s)
host_mem_usage 398660 # Number of bytes of host memory used
host_seconds 376.11 # Real time elapsed on the host
host_inst_rate 196358 # Simulator instruction rate (inst/s)
host_op_rate 252199 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7823307249 # Simulator tick rate (ticks/s)
host_mem_usage 401444 # Number of bytes of host memory used
host_seconds 307.24 # Real time elapsed on the host
sim_insts 60328186 # Number of instructions simulated
sim_ops 77484426 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
@ -360,18 +372,6 @@ system.physmem.writeRowHits 40077 # Nu
system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes
system.physmem.avgGap 172524.57 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55673401 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 13817014 # Transaction distribution
system.membus.trans_dist::ReadResp 13817014 # Transaction distribution
@ -1617,8 +1617,8 @@ system.cpu2.rename.LSQFullEvents 890462 # Nu
system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 159360013 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 27348 # Number of floating rename lookups
system.cpu2.rename.int_rename_lookups 148242103 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 3218 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
View file

@ -127,6 +127,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@ -602,6 +603,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 09:05:36
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:34:20
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.548576 # Nu
sim_ticks 2548576209000 # Number of ticks simulated
final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 60580 # Simulator instruction rate (inst/s)
host_op_rate 77951 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2559708219 # Simulator tick rate (ticks/s)
host_mem_usage 399668 # Number of bytes of host memory used
host_seconds 995.65 # Real time elapsed on the host
host_inst_rate 64501 # Simulator instruction rate (inst/s)
host_op_rate 82996 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2725389479 # Simulator tick rate (ticks/s)
host_mem_usage 403492 # Number of bytes of host memory used
host_seconds 935.12 # Real time elapsed on the host
sim_insts 60316464 # Number of instructions simulated
sim_ops 77611603 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
@ -1088,8 +1088,8 @@ system.cpu0.rename.LSQFullEvents 2115247 # Nu
system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 231623806 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 43568 # Number of floating rename lookups
system.cpu0.rename.int_rename_lookups 214169305 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 4937 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed
@ -1776,8 +1776,8 @@ system.cpu1.rename.LSQFullEvents 2033878 # Nu
system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 236708688 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 47158 # Number of floating rename lookups
system.cpu1.rename.int_rename_lookups 219276243 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 5446 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed

7
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
@ -128,6 +128,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@ -1356,7 +1357,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/andreas/m5/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1376,7 +1377,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

10
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:57:32
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5133817564000 because m5_exit instruction encountered
Exiting @ tick 5149801602000 because m5_exit instruction encountered

2574
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

10
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -220,8 +220,8 @@ voltage_domain=system.voltage_domain
[system.e820_table]
type=X86E820Table
children=entries0 entries1 entries2
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
children=entries0 entries1 entries2 entries3
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
[system.e820_table.entries0]
type=X86E820Entry
@ -241,6 +241,12 @@ addr=1048576
range_type=1
size=133169152
[system.e820_table.entries3]
type=X86E820Entry
addr=4294901760
range_type=2
size=65536
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0

71
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
View file

@ -1,57 +1,42 @@
Real time: Sep/22/2013 07:54:54
Profiler Stats
--------------
Elapsed_time_in_seconds: 689
Elapsed_time_in_minutes: 11.4833
Elapsed_time_in_hours: 0.191389
Elapsed_time_in_days: 0.00797454
Virtual_time_in_seconds: 688.52
Virtual_time_in_minutes: 11.4753
Virtual_time_in_hours: 0.191256
Virtual_time_in_days: 0.00796898
Ruby_current_time: 10608810122
Ruby_current_time: 10608984467
Ruby_start_time: 0
Ruby_cycles: 10608810122
mbytes_resident: 589.816
mbytes_total: 810.262
resident_ratio: 0.727933
Ruby_cycles: 10608984467
Busy Controller Counts:
L1Cache-0:10 L1Cache-1:9
L2Cache-0:0
L2Cache-0:1
Directory-0:0
DMA-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826690 average: 1.00012 | standard deviation: 0.0109671 | 0 154808066 18624 ]
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154865725 average: 1.00012 | standard deviation: 0.0109654 | 0 154847102 18623 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
latency: [binsize: 8 max: 146 count: 154826689 average: 3.40667 | standard deviation: 3.89546 | 152128107 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.16019 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
latency: ST: [binsize: 8 max: 146 count: 9754590 average: 4.6097 | standard deviation: 10.5962 | 9399926 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
latency: IFETCH: [binsize: 8 max: 145 count: 128502469 average: 3.10882 | standard deviation: 1.62805 | 127704898 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
latency: RMW_Read: [binsize: 8 max: 143 count: 526560 average: 6.05821 | standard deviation: 8.42496 | 454441 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343870 average: 5.61917 | standard deviation: 7.40449 | 302009 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average: 3 | standard deviation: 0 | 0 0 0 343870 ]
hit latency: [binsize: 1 max: 3 count: 152128107 average: 3 | standard deviation: 0 | 0 0 0 152128107 ]
hit latency: LD: [binsize: 1 max: 3 count: 13922963 average: 3 | standard deviation: 0 | 0 0 0 13922963 ]
hit latency: ST: [binsize: 1 max: 3 count: 9399926 average: 3 | standard deviation: 0 | 0 0 0 9399926 ]
hit latency: IFETCH: [binsize: 1 max: 3 count: 127704898 average: 3 | standard deviation: 0 | 0 0 0 127704898 ]
hit latency: RMW_Read: [binsize: 1 max: 3 count: 454441 average: 3 | standard deviation: 0 | 0 0 0 454441 ]
hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302009 average: 3 | standard deviation: 0 | 0 0 0 302009 ]
hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average: 3 | standard deviation: 0 | 0 0 0 343870 ]
miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4571 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
miss latency: ST: [binsize: 8 max: 146 count: 354664 average: 47.2728 | standard deviation: 34.6308 | 0 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5323 | standard deviation: 11.026 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
miss latency: RMW_Read: [binsize: 8 max: 143 count: 72119 average: 25.3288 | standard deviation: 9.37846 | 0 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5153 | standard deviation: 6.61955 | 0 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
latency: [binsize: 8 max: 146 count: 154865724 average: 3.40663 | standard deviation: 3.89597 | 152167065 0 2401413 123717 793 1 0 0 0 77289 1392 70 170 88137 4539 155 157 714 112 ]
latency: LD: [binsize: 8 max: 144 count: 15359723 average: 5.00324 | standard deviation: 7.16109 | 13927349 0 1353226 47181 696 0 0 0 0 9514 194 17 27 20186 1048 50 27 160 48 ]
latency: ST: [binsize: 8 max: 146 count: 9756253 average: 4.61012 | standard deviation: 10.5987 | 9401531 0 199293 31091 52 0 0 0 0 62477 1152 44 130 56479 3272 89 110 469 64 ]
latency: IFETCH: [binsize: 8 max: 140 count: 128535441 average: 3.1088 | standard deviation: 1.62806 | 127737856 0 781770 369 6 0 0 0 0 4126 24 8 11 10975 181 16 20 79 ]
latency: RMW_Read: [binsize: 8 max: 140 count: 526545 average: 6.05786 | standard deviation: 8.42243 | 454428 0 43164 27522 7 1 0 0 0 1003 18 1 2 364 31 0 0 4 ]
latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343881 average: 5.61911 | standard deviation: 7.40549 | 302020 0 23960 17554 32 0 0 0 0 169 4 0 0 133 7 0 0 2 ]
latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343881 average: 3 | standard deviation: 0 | 0 0 0 343881 ]
hit latency: [binsize: 1 max: 3 count: 152167065 average: 3 | standard deviation: 0 | 0 0 0 152167065 ]
hit latency: LD: [binsize: 1 max: 3 count: 13927349 average: 3 | standard deviation: 0 | 0 0 0 13927349 ]
hit latency: ST: [binsize: 1 max: 3 count: 9401531 average: 3 | standard deviation: 0 | 0 0 0 9401531 ]
hit latency: IFETCH: [binsize: 1 max: 3 count: 127737856 average: 3 | standard deviation: 0 | 0 0 0 127737856 ]
hit latency: RMW_Read: [binsize: 1 max: 3 count: 454428 average: 3 | standard deviation: 0 | 0 0 0 454428 ]
hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302020 average: 3 | standard deviation: 0 | 0 0 0 302020 ]
hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343881 average: 3 | standard deviation: 0 | 0 0 0 343881 ]
miss latency: [binsize: 8 max: 146 count: 2698659 average: 26.3349 | standard deviation: 18.3306 | 0 0 2401413 123717 793 1 0 0 0 77289 1392 70 170 88137 4539 155 157 714 112 ]
miss latency: LD: [binsize: 8 max: 144 count: 1432374 average: 24.4813 | standard deviation: 11.4669 | 0 0 1353226 47181 696 0 0 0 0 9514 194 17 27 20186 1048 50 27 160 48 ]
miss latency: ST: [binsize: 8 max: 146 count: 354722 average: 47.2848 | standard deviation: 34.6376 | 0 0 199293 31091 52 0 0 0 0 62477 1152 44 130 56479 3272 89 110 469 64 ]
miss latency: IFETCH: [binsize: 8 max: 140 count: 797585 average: 20.5333 | standard deviation: 11.0294 | 0 0 781770 369 6 0 0 0 0 4126 24 8 11 10975 181 16 20 79 ]
miss latency: RMW_Read: [binsize: 8 max: 140 count: 72117 average: 25.3262 | standard deviation: 9.36709 | 0 0 43164 27522 7 1 0 0 0 1003 18 1 2 364 31 0 0 4 ]
miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5155 | standard deviation: 6.62905 | 0 0 23960 17554 32 0 0 0 0 169 4 0 0 133 7 0 0 2 ]
Request vs. RubySystem State Profile
--------------------------------
@ -60,10 +45,10 @@ Request vs. RubySystem State Profile
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 15 count: 11145866 average: 0.602427 | standard deviation: 1.43356 | 9466902 2991 1616 2582 1666934 2480 317 253 407 1077 12 18 80 196 0 1 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 15 count: 6232784 average: 1.04523 | standard deviation: 1.76212 | 4606142 1096 355 706 1619950 2278 313 251 380 1006 12 18 80 196 0 1 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4782799 average: 0.0411809 | standard deviation: 0.401372 | 4731531 1706 955 1706 46644 155 4 2 27 69 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 130283 average: 0.0224435 | standard deviation: 0.272229 | 129229 189 306 170 340 47 0 0 0 2 ]
Total_delay_cycles: [binsize: 1 max: 15 count: 11146337 average: 0.602409 | standard deviation: 1.43347 | 9467254 3019 1636 2634 1666996 2474 322 244 418 1037 10 19 80 193 0 1 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 15 count: 6232935 average: 1.0452 | standard deviation: 1.76202 | 4606233 1132 350 702 1620005 2287 321 242 393 967 10 19 80 193 0 1 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783100 average: 0.041195 | standard deviation: 0.40134 | 4731792 1686 982 1765 46636 142 1 2 25 69 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 130302 average: 0.0227472 | standard deviation: 0.27339 | 129229 201 304 167 355 45 0 0 0 1 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

1
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
View file

@ -3,7 +3,6 @@ warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0x8086
warn: instruction 'wbinvd' unimplemented
warn: instruction 'wbinvd' unimplemented

8
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:43:05
gem5 started Sep 22 2013 07:43:21
gem5 compiled Oct 16 2013 01:55:52
gem5 started Oct 16 2013 01:57:05
gem5 executing on zizzer
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5304405061000 because m5_exit instruction encountered
Exiting @ tick 5304492233500 because m5_exit instruction encountered

30
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.304492 # Nu
sim_ticks 5304492233500 # Number of ticks simulated
final_tick 5304492233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 162344 # Simulator instruction rate (inst/s)
host_op_rate 311496 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7955466900 # Simulator tick rate (ticks/s)
host_mem_usage 830548 # Number of bytes of host memory used
host_seconds 666.77 # Real time elapsed on the host
host_inst_rate 155930 # Simulator instruction rate (inst/s)
host_op_rate 299191 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7641192165 # Simulator tick rate (ticks/s)
host_mem_usage 831032 # Number of bytes of host memory used
host_seconds 694.20 # Real time elapsed on the host
sim_insts 108246430 # Number of instructions simulated
sim_ops 207697456 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory
@ -564,16 +564,18 @@ system.cpu0.numWorkItemsStarted 0 # nu
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 91841555 # Number of instructions committed
system.cpu0.committedOps 177241434 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 167241249 # Number of integer alu accesses
system.cpu0.num_int_alu_accesses 167144917 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 2106041 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 16306998 # number of instructions that are conditional controls
system.cpu0.num_int_insts 167241249 # number of integer instructions
system.cpu0.num_int_insts 167144917 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 412874422 # number of times the integer registers were read
system.cpu0.num_int_register_writes 208905412 # number of times the integer registers were written
system.cpu0.num_int_register_reads 315702148 # number of times the integer registers were read
system.cpu0.num_int_register_writes 141403252 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 97172274 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 67502160 # number of times the CC registers were written
system.cpu0.num_mem_refs 19838885 # number of memory refs
system.cpu0.num_load_insts 12792113 # Number of load instructions
system.cpu0.num_store_insts 7046772 # Number of store instructions
@ -588,16 +590,18 @@ system.cpu1.numWorkItemsStarted 0 # nu
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 16404875 # Number of instructions committed
system.cpu1.committedOps 30456022 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 29860682 # Number of integer alu accesses
system.cpu1.num_int_alu_accesses 29781645 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 684501 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2123636 # number of instructions that are conditional controls
system.cpu1.num_int_insts 29860682 # number of integer instructions
system.cpu1.num_int_insts 29781645 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 77387317 # number of times the integer registers were read
system.cpu1.num_int_register_writes 33910763 # number of times the integer registers were written
system.cpu1.num_int_register_reads 60931294 # number of times the integer registers were read
system.cpu1.num_int_register_writes 23868275 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 16456023 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 10042488 # number of times the CC registers were written
system.cpu1.num_mem_refs 7344657 # number of memory refs
system.cpu1.num_load_insts 4252428 # Number of load instructions
system.cpu1.num_store_insts 3092229 # Number of store instructions

11
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
View file

@ -4,8 +4,9 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
end_pfn_map = 32768
kernel direct mapping tables up to 8000000 @ 8000-a000
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
@ -21,9 +22,9 @@ Processor #1
I/O APIC #2 at 0xFEC00000.
Setting APIC routing to flat
Processors: 2
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
PERCPU: Allocating 34160 bytes of per cpu data
Built 1 zonelists. Total pages: 30616
Built 1 zonelists. Total pages: 30615
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@ -34,7 +35,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
Memory: 122008k/131072k available (3699k kernel code, 8512k reserved, 1767k data, 248k init)
Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

7
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
mem_ranges=0:134217727
@ -333,6 +333,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@ -1407,7 +1408,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/andreas/m5/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1427,7 +1428,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

10854
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
View file

File diff suppressed because it is too large Load diff

2918
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
View file

File diff suppressed because it is too large Load diff

1
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 08:20:51
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 01:59:02
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu
sim_ticks 26877484000 # Number of ticks simulated
final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 190344 # Simulator instruction rate (inst/s)
host_op_rate 191711 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56473959 # Simulator tick rate (ticks/s)
host_mem_usage 375760 # Number of bytes of host memory used
host_seconds 475.93 # Real time elapsed on the host
host_inst_rate 158705 # Simulator instruction rate (inst/s)
host_op_rate 159844 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47086787 # Simulator tick rate (ticks/s)
host_mem_usage 380172 # Number of bytes of host memory used
host_seconds 570.81 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory
@ -333,8 +333,8 @@ system.cpu.rename.LSQFullEvents 4597767 # Nu
system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 499912232 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 925 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed

1
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

10
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:21:35
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:42:09
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -18,12 +16,12 @@ All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
info: Increasing stack size by one page.
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
info: Increasing stack size by one page.
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 65501881000 because target called exit()
Exiting @ tick 65497052500 because target called exit()

1323
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:52:30
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:43:36
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

20
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 992711 # Simulator instruction rate (inst/s)
host_op_rate 1748005 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1061587108 # Simulator tick rate (ticks/s)
host_mem_usage 424044 # Number of bytes of host memory used
host_seconds 159.15 # Real time elapsed on the host
host_inst_rate 1229454 # Simulator instruction rate (inst/s)
host_op_rate 2164871 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1314755229 # Simulator tick rate (ticks/s)
host_mem_usage 378084 # Number of bytes of host memory used
host_seconds 128.50 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186175 # number of integer instructions
system.cpu.num_int_insts 278169482 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions

6
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:32:00
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:48:06
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

20
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
sim_ticks 365989065000 # Number of ticks simulated
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 324809 # Simulator instruction rate (inst/s)
host_op_rate 571936 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 752437231 # Simulator tick rate (ticks/s)
host_mem_usage 382748 # Number of bytes of host memory used
host_seconds 486.40 # Real time elapsed on the host
host_inst_rate 746941 # Simulator instruction rate (inst/s)
host_op_rate 1315244 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1730329772 # Simulator tick rate (ticks/s)
host_mem_usage 386536 # Number of bytes of host memory used
host_seconds 211.51 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186175 # number of integer instructions
system.cpu.num_int_insts 278169482 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions

1
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 07:58:36
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:08:48
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu
sim_ticks 202349747500 # Number of ticks simulated
final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 95439 # Simulator instruction rate (inst/s)
host_op_rate 107602 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38223736 # Simulator tick rate (ticks/s)
host_mem_usage 246676 # Number of bytes of host memory used
host_seconds 5293.82 # Real time elapsed on the host
host_inst_rate 125600 # Simulator instruction rate (inst/s)
host_op_rate 141606 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50303215 # Simulator tick rate (ticks/s)
host_mem_usage 251352 # Number of bytes of host memory used
host_seconds 4022.61 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory
@ -416,8 +416,8 @@ system.cpu.rename.LSQFullEvents 8947899 # Nu
system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed

1
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

35
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,15 +1,28 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 02:08:50
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *********info: Increasing stack size by one page.
****************************************
**********************************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
******
58924 words stored in 3784810 bytes
@ -21,18 +34,8 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@ -72,11 +75,9 @@ info: Increasing stack size by one page.
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
info: Increasing stack size by one page.
info: Increasing stack size by one page.
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 458275427000 because target called exit()
Exiting @ tick 458276279000 because target called exit()

1616
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:21:35
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:44:23
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

20
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu
sim_ticks 885229328000 # Number of ticks simulated
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1006678 # Simulator instruction rate (inst/s)
host_op_rate 1861461 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1077718973 # Simulator tick rate (ticks/s)
host_mem_usage 296180 # Number of bytes of host memory used
host_seconds 821.39 # Real time elapsed on the host
host_inst_rate 1293065 # Simulator instruction rate (inst/s)
host_op_rate 2391022 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1384315331 # Simulator tick rate (ticks/s)
host_mem_usage 251216 # Number of bytes of host memory used
host_seconds 639.47 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317562 # number of integer instructions
system.cpu.num_int_insts 1526605510 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written
system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions

6
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:48:16
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:41:23
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

20
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
sim_ticks 1647872849000 # Number of ticks simulated
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 418246 # Simulator instruction rate (inst/s)
host_op_rate 773383 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 833516309 # Simulator tick rate (ticks/s)
host_mem_usage 254900 # Number of bytes of host memory used
host_seconds 1977.01 # Real time elapsed on the host
host_inst_rate 788676 # Simulator instruction rate (inst/s)
host_op_rate 1458350 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1571742015 # Simulator tick rate (ticks/s)
host_mem_usage 258676 # Number of bytes of host memory used
host_seconds 1048.44 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317562 # number of integer instructions
system.cpu.num_int_insts 1526605510 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written
system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions

1
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

4
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 09:53:14
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 16 2013 01:34:33
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.077522 # Nu
sim_ticks 77521581000 # Number of ticks simulated
final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 226587 # Simulator instruction rate (inst/s)
host_op_rate 226587 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46769350 # Simulator tick rate (ticks/s)
host_mem_usage 233048 # Number of bytes of host memory used
host_seconds 1657.53 # Real time elapsed on the host
host_inst_rate 201802 # Simulator instruction rate (inst/s)
host_op_rate 201802 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41653613 # Simulator tick rate (ticks/s)
host_mem_usage 236024 # Number of bytes of host memory used
host_seconds 1861.10 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory
@ -350,8 +350,8 @@ system.cpu.rename.IQFullEvents 25268 # Nu
system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 306415899 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 273002223 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 413955402 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 165462719 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed

1
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 08:27:24
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:05:47
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu
sim_ticks 68375005500 # Number of ticks simulated
final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 121198 # Simulator instruction rate (inst/s)
host_op_rate 154946 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 30350947 # Simulator tick rate (ticks/s)
host_mem_usage 251080 # Number of bytes of host memory used
host_seconds 2252.81 # Real time elapsed on the host
host_inst_rate 143200 # Simulator instruction rate (inst/s)
host_op_rate 183074 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 35860683 # Simulator tick rate (ticks/s)
host_mem_usage 256516 # Number of bytes of host memory used
host_seconds 1906.68 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory
@ -362,8 +362,8 @@ system.cpu.rename.LSQFullEvents 10191603 # Nu
system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed

1
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,10 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 09:53:14
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 15 2013 18:56:50
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.631883 # Nu
sim_ticks 631883288500 # Number of ticks simulated
final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 177291 # Simulator instruction rate (inst/s)
host_op_rate 177291 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61450789 # Simulator tick rate (ticks/s)
host_mem_usage 236780 # Number of bytes of host memory used
host_seconds 10282.75 # Real time elapsed on the host
host_inst_rate 151695 # Simulator instruction rate (inst/s)
host_op_rate 151695 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 52578725 # Simulator tick rate (ticks/s)
host_mem_usage 240040 # Number of bytes of host memory used
host_seconds 12017.85 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
@ -370,8 +370,8 @@ system.cpu.rename.IQFullEvents 15191 # Nu
system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 3493818421 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 85375087 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed

1
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 08:57:23
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:40:46
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.640648 # Nu
sim_ticks 640648369500 # Number of ticks simulated
final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 107808 # Simulator instruction rate (inst/s)
host_op_rate 146820 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49890421 # Simulator tick rate (ticks/s)
host_mem_usage 251704 # Number of bytes of host memory used
host_seconds 12841.11 # Real time elapsed on the host
host_inst_rate 92518 # Simulator instruction rate (inst/s)
host_op_rate 125998 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42814979 # Simulator tick rate (ticks/s)
host_mem_usage 256100 # Number of bytes of host memory used
host_seconds 14963.18 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
@ -363,8 +363,8 @@ system.cpu.rename.LSQFullEvents 52259250 # Nu
system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 12321480350 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 90240197 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed

1
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

4
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 09:57:43
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 16 2013 01:34:33
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.024977 # Nu
sim_ticks 24977022500 # Number of ticks simulated
final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 124025 # Simulator instruction rate (inst/s)
host_op_rate 124025 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38920856 # Simulator tick rate (ticks/s)
host_mem_usage 235900 # Number of bytes of host memory used
host_seconds 641.74 # Real time elapsed on the host
host_inst_rate 179872 # Simulator instruction rate (inst/s)
host_op_rate 179872 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56446381 # Simulator tick rate (ticks/s)
host_mem_usage 238148 # Number of bytes of host memory used
host_seconds 442.49 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
@ -417,8 +417,8 @@ system.cpu.rename.IQFullEvents 2492 # Nu
system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed

1
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 09:04:25
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:08:44
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026765 # Nu
sim_ticks 26765004500 # Number of ticks simulated
final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 102307 # Simulator instruction rate (inst/s)
host_op_rate 145187 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38617115 # Simulator tick rate (ticks/s)
host_mem_usage 251228 # Number of bytes of host memory used
host_seconds 693.09 # Real time elapsed on the host
host_inst_rate 122306 # Simulator instruction rate (inst/s)
host_op_rate 173568 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46166163 # Simulator tick rate (ticks/s)
host_mem_usage 255896 # Number of bytes of host memory used
host_seconds 579.75 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory
@ -432,8 +432,8 @@ system.cpu.rename.LSQFullEvents 4627273 # Nu
system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 530166885 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7695 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 476867094 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3452 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed

1
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,10 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 10:05:25
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 15 2013 19:07:40
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.694171 # Nu
sim_ticks 694171131000 # Number of ticks simulated
final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 178600 # Simulator instruction rate (inst/s)
host_op_rate 178600 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 71414604 # Simulator tick rate (ticks/s)
host_mem_usage 227828 # Number of bytes of host memory used
host_seconds 9720.30 # Real time elapsed on the host
host_inst_rate 145628 # Simulator instruction rate (inst/s)
host_op_rate 145628 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 58230614 # Simulator tick rate (ticks/s)
host_mem_usage 230068 # Number of bytes of host memory used
host_seconds 11921.07 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
@ -424,8 +424,8 @@ system.cpu.rename.IQFullEvents 1826446 # Nu
system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3899178783 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1242537 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 3900278198 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 143121 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 168 # count of serializing insts renamed

1
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

6
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 08:11:07
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:37:44
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.541686 # Nu
sim_ticks 541686426500 # Number of ticks simulated
final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 146656 # Simulator instruction rate (inst/s)
host_op_rate 163606 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51433162 # Simulator tick rate (ticks/s)
host_mem_usage 242412 # Number of bytes of host memory used
host_seconds 10531.85 # Real time elapsed on the host
host_inst_rate 133850 # Simulator instruction rate (inst/s)
host_op_rate 149320 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46941984 # Simulator tick rate (ticks/s)
host_mem_usage 248124 # Number of bytes of host memory used
host_seconds 11539.49 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory
@ -433,8 +433,8 @@ system.cpu.rename.LSQFullEvents 60088597 # Nu
system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 9782199775 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 333 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 862 # count of serializing insts renamed

6
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 07:00:18
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:38:48
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

20
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1114602 # Simulator instruction rate (inst/s)
host_op_rate 1736651 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1054547884 # Simulator tick rate (ticks/s)
host_mem_usage 286860 # Number of bytes of host memory used
host_seconds 2698.79 # Real time elapsed on the host
host_inst_rate 1357896 # Simulator instruction rate (inst/s)
host_op_rate 2115724 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1284732870 # Simulator tick rate (ticks/s)
host_mem_usage 240864 # Number of bytes of host memory used
host_seconds 2215.25 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862527 # number of integer instructions
system.cpu.num_int_insts 4684368009 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions

6
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,8 @@
Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:22:01
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:55:52
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

20
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
sim_ticks 5882580526000 # Number of ticks simulated
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 645050 # Simulator instruction rate (inst/s)
host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1261455450 # Simulator tick rate (ticks/s)
host_mem_usage 245540 # Number of bytes of host memory used
host_seconds 4663.33 # Real time elapsed on the host
host_inst_rate 876676 # Simulator instruction rate (inst/s)
host_op_rate 1365940 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1714420225 # Simulator tick rate (ticks/s)
host_mem_usage 249312 # Number of bytes of host memory used
host_seconds 3431.24 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862527 # number of integer instructions
system.cpu.num_int_insts 4684368009 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions

1
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

4
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 24 2013 03:08:53
gem5 started Sep 28 2013 10:24:35
gem5 compiled Oct 15 2013 18:24:51
gem5 started Oct 16 2013 01:34:33
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second

14
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.023492 # Nu
sim_ticks 23492267500 # Number of ticks simulated
final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 120531 # Simulator instruction rate (inst/s)
host_op_rate 120531 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33636905 # Simulator tick rate (ticks/s)
host_mem_usage 231740 # Number of bytes of host memory used
host_seconds 698.41 # Real time elapsed on the host
host_inst_rate 158745 # Simulator instruction rate (inst/s)
host_op_rate 158745 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44301493 # Simulator tick rate (ticks/s)
host_mem_usage 233720 # Number of bytes of host memory used
host_seconds 530.28 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory
@ -346,8 +346,8 @@ system.cpu.rename.IQFullEvents 398899 # Nu
system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 150534218 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7060874 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 733 # count of serializing insts renamed

1
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

8
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -1,14 +1,10 @@
Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 07:58:15
gem5 started Sep 22 2013 09:14:29
gem5 compiled Oct 16 2013 01:36:42
gem5 started Oct 16 2013 02:15:41
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

14
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.074201 # Nu
sim_ticks 74201024500 # Number of ticks simulated
final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 88798 # Simulator instruction rate (inst/s)
host_op_rate 97225 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38240010 # Simulator tick rate (ticks/s)
host_mem_usage 245976 # Number of bytes of host memory used
host_seconds 1940.40 # Real time elapsed on the host
host_inst_rate 115322 # Simulator instruction rate (inst/s)
host_op_rate 126267 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49662501 # Simulator tick rate (ticks/s)
host_mem_usage 251448 # Number of bytes of host memory used
host_seconds 1494.11 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory
@ -358,8 +358,8 @@ system.cpu.rename.LSQFullEvents 3662384 # Nu
system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1564582781 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17300681 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed

1
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192

8
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,12 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:39:37
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

489
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.144337 # Nu
sim_ticks 144337151000 # Number of ticks simulated
final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 53269 # Simulator instruction rate (inst/s)
host_op_rate 89284 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 58216660 # Simulator tick rate (ticks/s)
host_mem_usage 281036 # Number of bytes of host memory used
host_seconds 2479.31 # Real time elapsed on the host
host_inst_rate 71990 # Simulator instruction rate (inst/s)
host_op_rate 120663 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 78676444 # Simulator tick rate (ticks/s)
host_mem_usage 280564 # Number of bytes of host memory used
host_seconds 1834.57 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory
@ -215,14 +215,14 @@ system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% #
system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation
system.physmem.totQLat 12663500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 119173500 # Sum of mem lat for all requests
system.physmem.totQLat 12694000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests
system.physmem.totBusLat 26815000 # Total cycles spent in databus access
system.physmem.totBankLat 79695000 # Total cycles spent in bank access
system.physmem.avgQLat 2361.27 # Average queueing delay per request
system.physmem.avgQLat 2366.96 # Average queueing delay per request
system.physmem.avgBankLat 14860.15 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22221.42 # Average memory access latency
system.physmem.avgMemAccLat 22227.11 # Average memory access latency
system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s
@ -251,110 +251,109 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040
system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 343040 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 6992500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 50918345 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.branchPred.lookups 18643049 # Number of BP lookups
system.cpu.branchPred.condPredicted 18643049 # Number of conditional branches predicted
system.cpu.branchPred.lookups 18643050 # Number of BP lookups
system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11410311 # Number of BTB lookups
system.cpu.branchPred.BTBHits 10785937 # Number of BTB hits
system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups
system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.527984 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 288958648 # number of cpu cycles simulated
system.cpu.numCycles 288958646 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 206693383 # Number of instructions fetch has processed
system.cpu.fetch.Branches 18643049 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 12105441 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 54202283 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 15520862 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 177854698 # Number of cycles fetch has spent blocked
system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed
system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 22344440 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 223501 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 269290807 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.269558 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.757533 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 216527174 80.41% 80.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2635919 0.98% 83.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31978830 11.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 269290807 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 36876726 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 166835214 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 41579224 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10227847 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 13771796 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 335978319 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 13771796 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44930870 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 116571073 # Number of cycles rename is blocking
system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 51278615 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 329616563 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10879 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 26000887 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 22678374 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 382329747 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 917574423 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 909394709 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8179714 # Number of floating rename lookups
system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 122900297 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 104883276 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 84491863 # Number of loads inserted to the mem dependence unit.
system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 58238424 # Number of conflicting loads.
system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 322680217 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 260554825 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 118516 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 100936987 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 209936629 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 269290807 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.967559 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.344978 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 143216984 53.18% 53.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 55392011 20.57% 73.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 34136175 12.68% 86.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 19056796 7.08% 93.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10890988 4.04% 97.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4174840 1.55% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1812715 0.67% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 476750 0.18% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 269290807 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 129590 4.77% 4.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available
@ -388,8 +387,8 @@ system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 162062843 62.20% 62.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 788599 0.30% 62.97% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued
@ -417,25 +416,25 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 65458478 25.12% 91.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 260554825 # Type of FU issued
system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued
system.cpu.iq.rate 0.901703 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2717985 # FU busy when requested
system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 788349726 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 420314001 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 255192171 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 259602149 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18922789 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 27842276 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed
@ -444,57 +443,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 13771796 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 85093935 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5458597 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 322684485 # Number of instructions dispatched to IQ
system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 84491863 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2689496 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 258780587 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64687693 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1774238 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 87035311 # number of memory reference insts executed
system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed
system.cpu.iew.exec_branches 14266808 # Number of branches executed
system.cpu.iew.exec_stores 22347618 # Number of stores executed
system.cpu.iew.exec_rate 0.895563 # Inst execution rate
system.cpu.iew.wb_sent 258140928 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 257541852 # cumulative count of insts written-back
system.cpu.iew.wb_producers 206006710 # num instructions producing a value
system.cpu.iew.wb_consumers 369206768 # num instructions consuming a value
system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back
system.cpu.iew.wb_producers 206006775 # num instructions producing a value
system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 101393272 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 255519011 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.866328 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.656610 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 156315570 61.18% 61.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12048530 4.72% 93.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4172669 1.63% 95.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1048603 0.41% 97.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6974170 2.73% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 255519011 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -503,14 +502,14 @@ system.cpu.commit.loads 56649587 # Nu
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 12326938 # Number of branches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
system.cpu.commit.function_calls 797818 # Number of function calls committed.
system.cpu.commit.bw_lim_events 6974170 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 571301497 # The number of ROB reads
system.cpu.rob.rob_writes 659310607 # The number of ROB writes
system.cpu.timesIdled 5931768 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19667841 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 571301422 # The number of ROB reads
system.cpu.rob.rob_writes 659310799 # The number of ROB writes
system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
@ -518,11 +517,13 @@ system.cpu.cpi 2.187901 # CP
system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads
system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 554180321 # number of integer regfile reads
system.cpu.int_regfile_writes 293821719 # number of integer regfile writes
system.cpu.int_regfile_reads 451358394 # number of integer regfile reads
system.cpu.int_regfile_writes 233998694 # number of integer regfile writes
system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads
system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes
system.cpu.misc_regfile_reads 133360565 # number of misc regfile reads
system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads
system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes
system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution
@ -547,50 +548,50 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L
system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 4647 # number of replacements
system.cpu.icache.tags.tagsinuse 1626.526470 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22335617 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3378.042498 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526470 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 22335617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22335617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22335617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22335617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22335617 # number of overall hits
system.cpu.icache.overall_hits::total 22335617 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits
system.cpu.icache.overall_hits::total 22335618 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses
system.cpu.icache.overall_misses::total 8823 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 351986000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 351986000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 351986000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 351986000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 351986000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 351986000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22344440 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22344440 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22344440 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22344440 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22344440 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22344440 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39894.140315 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 39894.140315 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 39894.140315 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 39894.140315 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
@ -611,34 +612,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6769
system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6769 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262790750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 262790750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262790750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 262790750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262790750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 262790750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38822.684296 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38822.684296 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor
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@ -710,17 +711,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.622780 #
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@ -742,19 +743,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5364
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency
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@ -807,22 +808,22 @@ system.cpu.dcache.demand_misses::cpu.data 2608 # n
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@ -831,14 +832,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000039
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency
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@ -865,14 +866,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2156
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133772345 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
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@ -881,14 +882,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033
system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68653.225806 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60229.801892 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60229.801892 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

8
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -1,12 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:46:06
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

20
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 399836 # Simulator instruction rate (inst/s)
host_op_rate 670162 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 397783827 # Simulator tick rate (ticks/s)
host_mem_usage 267400 # Number of bytes of host memory used
host_seconds 330.31 # Real time elapsed on the host
host_inst_rate 1210449 # Simulator instruction rate (inst/s)
host_op_rate 2028822 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1204235272 # Simulator tick rate (ticks/s)
host_mem_usage 265804 # Number of bytes of host memory used
host_seconds 109.11 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339554 # number of integer instructions
system.cpu.num_int_insts 219019986 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 616959402 # number of times the integer registers were read
system.cpu.num_int_register_writes 257598047 # number of times the integer registers were written
system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions

8
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -1,12 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:51:48
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

20
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
sim_ticks 250953957000 # Number of ticks simulated
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 290889 # Simulator instruction rate (inst/s)
host_op_rate 487557 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 552730735 # Simulator tick rate (ticks/s)
host_mem_usage 274892 # Number of bytes of host memory used
host_seconds 454.03 # Real time elapsed on the host
host_inst_rate 789102 # Simulator instruction rate (inst/s)
host_op_rate 1322606 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1499404446 # Simulator tick rate (ticks/s)
host_mem_usage 274284 # Number of bytes of host memory used
host_seconds 167.37 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
@ -50,16 +50,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339554 # number of integer instructions
system.cpu.num_int_insts 219019986 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 616959402 # number of times the integer registers were read
system.cpu.num_int_register_writes 257598047 # number of times the integer registers were written
system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions

6
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
mem_ranges=0:134217727
@ -1029,7 +1029,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/andreas/m5/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1049,7 +1049,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

8
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:03:55
gem5 executing on steam
gem5 compiled Oct 16 2013 01:35:57
gem5 started Oct 16 2013 01:42:07
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5112126311000 because m5_exit instruction encountered

20
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.112126 # Nu
sim_ticks 5112126311000 # Number of ticks simulated
final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1020096 # Simulator instruction rate (inst/s)
host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 26083435490 # Simulator tick rate (ticks/s)
host_mem_usage 587152 # Number of bytes of host memory used
host_seconds 195.99 # Real time elapsed on the host
host_inst_rate 1595516 # Simulator instruction rate (inst/s)
host_op_rate 3266720 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40796695114 # Simulator tick rate (ticks/s)
host_mem_usage 587608 # Number of bytes of host memory used
host_seconds 125.31 # Real time elapsed on the host
sim_insts 199929810 # Number of instructions simulated
sim_ops 409343980 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
@ -259,16 +259,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199929810 # Number of instructions committed
system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses
system.cpu.num_int_alu_accesses 374364740 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 2307717 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls
system.cpu.num_int_insts 374506599 # number of integer instructions
system.cpu.num_int_insts 374364740 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read
system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written
system.cpu.num_int_register_reads 682285995 # number of times the integer registers were read
system.cpu.num_int_register_writes 323369548 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 233715170 # number of times the CC registers were read
system.cpu.num_cc_register_writes 157233581 # number of times the CC registers were written
system.cpu.num_mem_refs 35660913 # number of memory refs
system.cpu.num_load_insts 27238816 # Number of load instructions
system.cpu.num_store_insts 8422097 # Number of store instructions

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