10e6450120
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
28 lines
1.2 KiB
Text
Executable file
28 lines
1.2 KiB
Text
Executable file
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 15 2013 18:24:51
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gem5 started Oct 15 2013 19:07:40
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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info: Increasing stack size by one page.
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spec_init
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Loading Input Data
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Input data 1048576 bytes in length
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Compressing Input Data, level 7
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Compressed data 198546 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 9
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Compressed data 198677 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 694171131000 because target called exit()
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