Stats: Update stats for use of two-level builder
This patch updates the name of the l2 stats.
This commit is contained in:
Andreas Hansson
parent
3cf733bcc0
commit
a850fc916f
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@ -38,198 +38,198 @@ system.physmem.bw_total::cpu.inst 519335 # To
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system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.replacements 338398 # number of replacements
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system.l2c.tagsinuse 65348.140689 # Cycle average of tags in use
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system.l2c.total_refs 2559915 # Total number of references to valid blocks.
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system.l2c.sampled_refs 403567 # Sample count of references to valid blocks.
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system.l2c.avg_refs 6.343222 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.997133 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu.data 827771 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1835554 # number of ReadReq hits
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system.l2c.Writeback_hits::writebacks 841020 # number of Writeback hits
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system.l2c.Writeback_hits::total 841020 # number of Writeback hits
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system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
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system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
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system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
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system.l2c.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 185546 # number of ReadExReq hits
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system.l2c.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu.data 1013317 # number of demand (read+write) hits
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system.l2c.demand_hits::total 2021100 # number of demand (read+write) hits
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system.l2c.overall_hits::cpu.inst 1007783 # number of overall hits
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system.l2c.overall_hits::cpu.data 1013317 # number of overall hits
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system.l2c.overall_hits::total 2021100 # number of overall hits
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system.l2c.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu.data 273854 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 289009 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 54 # number of UpgradeReq misses
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system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
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system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
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system.l2c.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 115395 # number of ReadExReq misses
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system.l2c.demand_misses::cpu.inst 15155 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu.data 389249 # number of demand (read+write) misses
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system.l2c.demand_misses::total 404404 # number of demand (read+write) misses
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system.l2c.overall_misses::cpu.inst 15155 # number of overall misses
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system.l2c.overall_misses::cpu.data 389249 # number of overall misses
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system.l2c.overall_misses::total 404404 # number of overall misses
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system.l2c.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles
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system.l2c.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles
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system.l2c.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles
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system.l2c.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles
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system.l2c.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles
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system.l2c.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles
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system.l2c.overall_miss_latency::total 21292255995 # number of overall miss cycles
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system.l2c.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 2425504 # number of demand (read+write) accesses
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system.l2c.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 2425504 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses
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system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
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system.l2c.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses
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system.l2c.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses
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system.l2c.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.166730 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.166730 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency
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system.l2c.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency
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system.l2c.demand_avg_miss_latency::total 52650.952995 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 52650.952995 # average overall miss latency
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.writebacks::writebacks 75968 # number of writebacks
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system.l2c.writebacks::total 75968 # number of writebacks
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system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
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system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
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system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
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system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
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system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
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system.l2c.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses
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system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
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system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 404403 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles
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system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses
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system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
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system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses
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system.l2c.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 338398 # number of replacements
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system.cpu.l2cache.tagsinuse 65348.140689 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2559915 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 403567 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 6.343222 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.997133 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 827771 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 1835554 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 841020 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 841020 # number of Writeback hits
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system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
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system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
|
||||
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 185546 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1013317 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2021100 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1007783 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1013317 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2021100 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 273854 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 289009 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 54 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 15155 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 389249 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 404404 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 15155 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 389249 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 404404 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21292255995 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2425504 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2425504 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.166730 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.166730 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 75968 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 75968 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 404403 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.tagsinuse 1.309507 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -61,273 +61,273 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25
|
|||
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 64349 # number of replacements
|
||||
system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1931844 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 129748 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 14.889201 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 609524 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
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|
||||
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|
||||
system.l2c.writebacks::total 59057 # number of writebacks
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
|
||||
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|
||||
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|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
|
||||
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|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 64349 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
|
||||
system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits
|
||||
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|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits
|
||||
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|
||||
system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
|
||||
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|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
|
||||
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|
||||
system.cpu.l2cache.demand_misses::total 156282 # number of demand (read+write) misses
|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 156282 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59057 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
|
|
@ -61,273 +61,273 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25
|
|||
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 64349 # number of replacements
|
||||
system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1931844 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 129748 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 14.889201 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 609524 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 977692 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 502174 # number of overall hits
|
||||
system.l2c.overall_hits::total 1576793 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 156282 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 12366 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 143849 # number of overall misses
|
||||
system.l2c.overall_misses::total 156282 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 59057 # number of writebacks
|
||||
system.l2c.writebacks::total 59057 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 64349 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
|
||||
system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1576793 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 12176 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
|
|
@ -46,249 +46,249 @@ system.physmem.bw_total::cpu.itb.walker 74 # To
|
|||
system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 109190 # number of replacements
|
||||
system.l2c.tagsinuse 64839.015299 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3984882 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 173424 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 22.977685 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.989365 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2515284 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1610495 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1610495 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 158131 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1505908 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2673415 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 103321 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 8437 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 1055749 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1505908 # number of overall hits
|
||||
system.l2c.overall_hits::total 2673415 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 35983 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 52753 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3384 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 130218 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 16718 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 166201 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 182971 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 46 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 16718 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 166201 # number of overall misses
|
||||
system.l2c.overall_misses::total 182971 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 9598796997 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 103367 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 8443 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 1072467 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1672109 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2856386 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 103367 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 8443 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 1072467 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1672109 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2856386 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000711 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.015588 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.026004 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.020542 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.909433 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.909433 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.451599 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.451599 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.000711 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.015588 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.099396 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.064057 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.000711 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.015588 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.099396 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.064057 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.130435 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53087.002034 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 53390.267571 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 53293.224992 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11322.399527 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 11322.399527 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.512103 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52123.512103 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52460.756060 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52460.756060 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 98965 # number of writebacks
|
||||
system.l2c.writebacks::total 98965 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 16717 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 35981 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 52750 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 3384 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 3384 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 130218 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 130218 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 16717 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 166199 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 182968 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 16717 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 166199 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 182968 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1856000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 683651500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1481312999 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 2167060499 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 135806000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 135806000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5218894001 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5218894001 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1856000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 683651500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6700207000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 7385954500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1856000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 683651500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6700207000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 7385954500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 109190 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64839.015299 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3984882 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 173424 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 22.977685 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.989365 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2515284 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1610495 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1610495 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 337 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 158131 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1505908 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2673415 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 103321 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 8437 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1055749 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1505908 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2673415 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 35983 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 52753 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 3384 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 130218 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 16718 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166201 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 182971 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 16718 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166201 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 182971 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 9598796997 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103367 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 8443 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1072467 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1672109 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2856386 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103367 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 8443 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1072467 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1672109 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2856386 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000711 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015588 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026004 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.020542 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909433 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909433 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.451599 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.451599 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000711 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015588 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.099396 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.064057 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000711 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015588 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.099396 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.064057 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.130435 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53087.002034 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53390.267571 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53293.224992 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11322.399527 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11322.399527 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52123.512103 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52123.512103 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52460.756060 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52460.756060 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98965 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98965 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16717 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35981 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 52750 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3384 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3384 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130218 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130218 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16717 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 166199 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 182968 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16717 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 166199 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 182968 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1856000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683651500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1481312999 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2167060499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135806000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135806000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5218894001 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5218894001 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1856000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683651500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6700207000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7385954500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1856000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683651500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6700207000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7385954500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47573 # number of replacements
|
||||
system.iocache.tagsinuse 0.184801 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -38,86 +38,86 @@ system.physmem.bw_total::cpu.inst 469015 # To
|
|||
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 992301 # number of replacements
|
||||
system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2433239 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.301014 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1718026 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 833491 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 833491 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 187229 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 998458 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1905255 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.inst 906797 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 998458 # number of overall hits
|
||||
system.l2c.overall_hits::total 1905255 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 117117 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1058163 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.inst 13406 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 1044757 # number of overall misses
|
||||
system.l2c.overall_misses::total 1058163 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2963418 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2963418 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.357075 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.357075 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 74291 # number of writebacks
|
||||
system.l2c.writebacks::total 74291 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 992301 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74291 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41686 # number of replacements
|
||||
system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -38,176 +38,176 @@ system.physmem.bw_total::cpu.inst 442760 # To
|
|||
system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 336257 # number of replacements
|
||||
system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2448454 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 401419 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 6.099497 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 814985 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1731448 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 835257 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 187565 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.inst 916463 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1002550 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1919013 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.inst 916463 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1002550 # number of overall hits
|
||||
system.l2c.overall_hits::total 1919013 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 271966 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 285255 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 13 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 116861 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 388827 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 402116 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.inst 13289 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 388827 # number of overall misses
|
||||
system.l2c.overall_misses::total 402116 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 20916229000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2321129 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2321129 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.173242 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.173242 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52015.410976 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52015.410976 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 74180 # number of writebacks
|
||||
system.l2c.writebacks::total 74180 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 402116 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 336257 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 65308.063316 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2448454 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 401419 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.099497 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.996522 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 814985 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1731448 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 835257 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 835257 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187565 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 916463 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1002550 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1919013 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 916463 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1002550 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1919013 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 271966 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 116861 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 388827 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 402116 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 388827 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 402116 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20916229000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2321129 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2321129 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.173242 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.173242 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52015.410976 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52015.410976 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74180 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 402116 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.tagsinuse 1.347775 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -61,114 +61,114 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9
|
|||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 62243 # number of replacements
|
||||
system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1669922 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 127628 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 13.084292 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 592643 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 113739 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 480510 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1330017 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 7507 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3129 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 838871 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 480510 # number of overall hits
|
||||
system.l2c.overall_hits::total 1330017 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 20483 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 133468 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 153951 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 10604 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 143339 # number of overall misses
|
||||
system.l2c.overall_misses::total 153951 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1483968 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 57863 # number of writebacks
|
||||
system.l2c.writebacks::total 57863 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 62243 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
|
|
@ -61,244 +61,244 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8
|
|||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 62933 # number of replacements
|
||||
system.l2c.tagsinuse 51862.510726 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1683379 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 128318 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 13.118806 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.791359 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 370308 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1226888 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 596416 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 596416 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 113846 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 844195 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 484154 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1340734 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 8836 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3549 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 844195 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 484154 # number of overall hits
|
||||
system.l2c.overall_hits::total 1340734 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 10261 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 20880 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2845 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 133824 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses
|
||||
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|
||||
system.l2c.demand_misses::cpu.inst 10613 # number of demand (read+write) misses
|
||||
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|
||||
system.l2c.demand_misses::total 154704 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 4 # number of overall misses
|
||||
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|
||||
system.l2c.overall_misses::cpu.inst 10613 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 144085 # number of overall misses
|
||||
system.l2c.overall_misses::total 154704 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles
|
||||
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|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8049111500 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1495438 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1495438 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.103451 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.103451 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
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|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52029.110430 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52029.110430 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 58379 # number of writebacks
|
||||
system.l2c.writebacks::total 58379 # number of writebacks
|
||||
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|
||||
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|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses
|
||||
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|
||||
system.l2c.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses
|
||||
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|
||||
system.l2c.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses
|
||||
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|
||||
system.l2c.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses
|
||||
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|
||||
system.l2c.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 154704 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 62933 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
|
|
@ -46,114 +46,114 @@ system.physmem.bw_total::cpu.itb.walker 63 # To
|
|||
system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 106561 # number of replacements
|
||||
system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3456533 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 170680 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 20.251541 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1538130 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1538130 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 777957 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1454603 # number of overall hits
|
||||
system.l2c.overall_hits::total 2241838 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 179910 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 13342 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 166561 # number of overall misses
|
||||
system.l2c.overall_misses::total 179910 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 98533 # number of writebacks
|
||||
system.l2c.writebacks::total 98533 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 106561 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 179910 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98533 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47570 # number of replacements
|
||||
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -42,214 +42,214 @@ system.physmem.bw_total::cpu.itb.walker 62 # To
|
|||
system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 86330 # number of replacements
|
||||
system.l2c.tagsinuse 64759.737076 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3491284 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 151054 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 23.112821 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.988155 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2068208 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1543462 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1543462 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 302 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 778172 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1481001 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2268886 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 6719 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 2994 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 778172 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1481001 # number of overall hits
|
||||
system.l2c.overall_hits::total 2268886 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 28353 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 41237 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 112514 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 12879 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 140867 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 153751 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 12879 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 140867 # number of overall misses
|
||||
system.l2c.overall_misses::total 153751 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8011639500 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2422637 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2422637 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.063464 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.063464 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52107.885477 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52107.885477 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 79675 # number of writebacks
|
||||
system.l2c.writebacks::total 79675 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 153751 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 86330 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor
|
||||
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|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits
|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits
|
||||
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|
||||
system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses
|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency
|
||||
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|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 79675 # number of writebacks
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
|
||||
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|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles
|
||||
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|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses
|
||||
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|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47503 # number of replacements
|
||||
system.iocache.tagsinuse 0.108744 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
Loading…
Reference in a new issue