stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM controller.
This commit is contained in:
Andreas Hansson
parent
a00383a40a
commit
8b4b1dcb86
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -4,11 +4,11 @@ sim_seconds 5.304497 # Nu
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sim_ticks 5304496750000 # Number of ticks simulated
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final_tick 5304496750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 125034 # Simulator instruction rate (inst/s)
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host_op_rate 239740 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6206530470 # Simulator tick rate (ticks/s)
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host_mem_usage 832476 # Number of bytes of host memory used
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host_seconds 854.66 # Real time elapsed on the host
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host_inst_rate 156851 # Simulator instruction rate (inst/s)
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host_op_rate 300747 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7785889362 # Simulator tick rate (ticks/s)
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host_mem_usage 816820 # Number of bytes of host memory used
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host_seconds 681.30 # Real time elapsed on the host
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sim_insts 106862058 # Number of instructions simulated
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sim_ops 204897478 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -199,6 +199,38 @@ system.physmem.wrQLenPdf::28 0 # Wh
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.totQLat 0 # Total ticks spent queuing
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system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 0 # Total ticks spent in databus transfers
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 0.139926 # Nu
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sim_ticks 139926186500 # Number of ticks simulated
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final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 138827 # Simulator instruction rate (inst/s)
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host_op_rate 138827 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48726388 # Simulator tick rate (ticks/s)
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host_mem_usage 236592 # Number of bytes of host memory used
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host_seconds 2871.67 # Real time elapsed on the host
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host_inst_rate 124689 # Simulator instruction rate (inst/s)
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host_op_rate 124689 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 43764124 # Simulator tick rate (ticks/s)
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host_mem_usage 271420 # Number of bytes of host memory used
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host_seconds 3197.28 # Real time elapsed on the host
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sim_insts 398664595 # Number of instructions simulated
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sim_ops 398664595 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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@ -154,79 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation
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system.physmem.totQLat 59880500 # Total ticks spent queuing
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system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation
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system.physmem.totQLat 59527000 # Total ticks spent queuing
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system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 101103750 # Total ticks spent accessing banks
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system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst
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system.physmem.totBankLat 103757500 # Total ticks spent accessing banks
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system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst
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system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s
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@ -235,15 +216,15 @@ system.physmem.peakBW 12800.00 # Th
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
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system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 6130 # Number of row buffer hits during reads
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system.physmem.readRowHits 5962 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads
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system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 19094720.66 # Average gap between requests
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system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state
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system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 3351710 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
|
||||
|
|
@ -257,7 +238,7 @@ system.membus.data_through_bus 468992 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 53489673 # Number of BP lookups
|
||||
|
|
@ -273,22 +254,22 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754637 # DTB read hits
|
||||
system.cpu.dtb.read_hits 94754639 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754658 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521124 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 94754660 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521131 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73521159 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275761 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73521166 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275770 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275817 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611324 # ITB hits
|
||||
system.cpu.dtb.data_accesses 168275826 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611322 # ITB hits
|
||||
system.cpu.itb.fetch_misses 44520 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 48655844 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 48655842 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -307,13 +288,13 @@ system.cpu.numWorkItemsStarted 0 # nu
|
|||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -324,12 +305,12 @@ system.cpu.execution_unit.executions 205475782 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.159695 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.159696 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -350,27 +331,27 @@ system.cpu.ipc_total 1.424553 # IP
|
|||
system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
|
||||
|
|
@ -378,44 +359,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 322
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 97226551 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 97226551 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606790 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4534 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606787 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4535 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -424,36 +405,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
|
||||
|
|
@ -471,21 +452,21 @@ system.cpu.toL2Bus.data_through_bus 557056 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id
|
||||
|
|
@ -520,17 +501,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -555,17 +536,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -585,17 +566,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -607,27 +588,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
|
||||
|
|
@ -639,28 +620,28 @@ system.cpu.dcache.tags.tag_accesses 336554588 # Nu
|
|||
system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254255 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254239 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20963 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20979 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -671,25 +652,25 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218
|
|||
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -697,12 +678,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu
|
|||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16827 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
|
|
@ -711,14 +692,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -727,14 +708,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.041680 # Number of seconds simulated
|
||||
sim_ticks 41680207000 # Number of ticks simulated
|
||||
final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.041684 # Number of seconds simulated
|
||||
sim_ticks 41683573000 # Number of ticks simulated
|
||||
final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 131207 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 131207 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59505524 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234284 # Number of bytes of host memory used
|
||||
host_seconds 700.44 # Real time elapsed on the host
|
||||
host_inst_rate 119929 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 119929 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 54395175 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269084 # Number of bytes of host memory used
|
||||
host_seconds 766.31 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 41680133000 # Total gap between requests
|
||||
system.physmem.totGap 41683192000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -154,65 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 34070750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 37971250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 67663750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 68832500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -221,16 +216,16 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 0.06 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4195 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4086 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 8440691.17 # Average gap between requests
|
||||
system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 7582304 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 8441310.65 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 7581692 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
|
|
@ -241,9 +236,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 13412627 # Number of BP lookups
|
||||
|
|
@ -259,18 +254,18 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 19996265 # DTB read hits
|
||||
system.cpu.dtb.read_hits 19996264 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 19996275 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501862 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 19996274 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501866 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6501885 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498127 # DTB hits
|
||||
system.cpu.dtb.write_accesses 6501889 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498130 # DTB hits
|
||||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498160 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 26498163 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956950 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -288,18 +283,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 83360415 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 83367147 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -310,12 +305,12 @@ system.cpu.execution_unit.executions 57404027 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.699836 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.692506 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -327,36 +322,36 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
|
|
@ -378,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n
|
|||
system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11399 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses
|
||||
|
|
@ -396,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145
|
|||
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -422,26 +417,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520
|
|||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
|
|
@ -457,19 +452,19 @@ system.cpu.toL2Bus.data_through_bus 758400 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
|
||||
|
|
@ -507,17 +502,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -542,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -572,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -594,31 +589,31 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
|
||||
|
|
@ -626,28 +621,28 @@ system.cpu.dcache.tags.tag_accesses 52996825 # Nu
|
|||
system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488450 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488456 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8851 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8845 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -658,25 +653,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301
|
|||
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001272 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001272 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -684,12 +679,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu
|
|||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
|
|
@ -698,14 +693,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -714,14 +709,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 25485000 # Number of ticks simulated
|
||||
final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25552000 # Number of ticks simulated
|
||||
final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24806 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24805 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98922905 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229760 # Number of bytes of host memory used
|
||||
host_seconds 0.26 # Real time elapsed on the host
|
||||
host_inst_rate 78801 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 78787 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 314994021 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262608 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
|
|||
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 753384344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 421895232 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1175279576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 753384344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 753384344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 753384344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 421895232 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1175279576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 751408892 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 420788979 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1172197871 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 751408892 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 751408892 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 751408892 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 420788979 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1172197871 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 25470500 # Total gap between requests
|
||||
system.physmem.totGap 25537500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -154,54 +154,77 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 294.095238 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 157.496730 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 421.391602 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 37 44.05% 44.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 14 16.67% 60.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 5 5.95% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 5 5.95% 72.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 4 4.76% 77.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 5 5.95% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 1 1.19% 84.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576 1 1.19% 85.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 2 2.38% 88.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 1 1.19% 89.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832 1 1.19% 90.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896 2 2.38% 92.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960 1 1.19% 94.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216 2 2.38% 96.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1792 1 1.19% 97.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 1 1.19% 98.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240 1 1.19% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2272250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12262250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 54 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 317.629630 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 196.201768 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 327.982069 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 16 29.63% 29.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 16 29.63% 59.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 7 12.96% 72.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 4 7.41% 79.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1 1.85% 81.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1 1.85% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 3.70% 87.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7 12.96% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 54 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2560250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12605250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 7645000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 4844.88 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 16300.64 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 7700000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5458.96 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 16417.91 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26145.52 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1177.79 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26876.87 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1177.79 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 9.20 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 9.20 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 9.18 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 9.18 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.48 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 385 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 378 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.09 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 54308.10 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.09 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 54450.96 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1175279576 # Throughput (bytes/s)
|
||||
system.membus.throughput 1172197871 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -214,8 +237,8 @@ system.membus.data_through_bus 29952 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4371250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1632 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
|
||||
|
|
@ -230,18 +253,18 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1184 # DTB read hits
|
||||
system.cpu.dtb.read_hits 1183 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1191 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 893 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 1190 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 890 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 896 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2077 # DTB hits
|
||||
system.cpu.dtb.write_accesses 893 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2073 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2087 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 2083 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 915 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -259,18 +282,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 50971 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 51105 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5174 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 5177 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9741 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9744 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 2976 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 2973 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2152 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -281,12 +304,12 @@ system.cpu.execution_unit.executions 4448 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11596 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 43595 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7376 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 14.470974 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 469 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 14.431073 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1183 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
||||
|
|
@ -298,36 +321,36 @@ system.cpu.committedInsts 6390 # Nu
|
|||
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 7.976682 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 7.997653 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 7.976682 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.125365 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 7.997653 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.125037 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.125365 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 46047 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.125037 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 46181 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 9.660395 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 47078 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 9.635065 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 47212 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 7.637676 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 46810 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 7.617650 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 46944 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 8.163465 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 49637 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.617174 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 46513 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 8.746150 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.utilization 8.142060 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 49775 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1330 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.602485 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 46641 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 142.311081 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 142.169993 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.169993 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069419 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069419 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
|
||||
|
|
@ -346,12 +369,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n
|
|||
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 355 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24550250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24550250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24550250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24550250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24550250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24550250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25349750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25349750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25349750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25349750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25349750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25349750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
||||
|
|
@ -364,12 +387,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978
|
|||
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69155.633803 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69155.633803 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -390,26 +413,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302
|
|||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20718250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20718250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20718250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20718250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20718250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20718250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21532500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21532500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21532500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21532500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21532500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21532500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1177790857 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -424,21 +447,21 @@ system.cpu.toL2Bus.data_through_bus 30016 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 508750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 274750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.093004 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 198.925679 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.347593 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.205920 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.719759 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004340 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001731 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006071 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
|
||||
|
|
@ -462,17 +485,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20399750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27865000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4857750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4857750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20399750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12323000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32722750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20399750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12323000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32722750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21214000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6927250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 28141250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4931500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4931500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21214000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11858750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 33072750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21214000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11858750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 33072750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -495,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -525,17 +548,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16625250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6283250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22908500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3954250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3954250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16625250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10237500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26862750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16625250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10237500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26862750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17443000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5745750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23188750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4029500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4029500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17443000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9775250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27218250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17443000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9775250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27218250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -547,27 +570,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.493430 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.450623 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.450623 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025256 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025256 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
|
||||
|
|
@ -590,14 +613,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
|
|||
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7909250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7909250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21376500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21376500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29285750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29285750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29285750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29285750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7371250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7371250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21672250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21672250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29043500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29043500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -614,19 +637,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65516.219239 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65516.219239 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.730769 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -646,14 +669,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7566750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7566750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4935250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4935250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12502000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12502000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12502000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12502000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7028750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7028750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5009000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5009000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12037750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12037750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12037750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12037750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -662,14 +685,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79650 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79650 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 11990500 # Number of ticks simulated
|
||||
final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 12006500 # Number of ticks simulated
|
||||
final_tick 12006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 21306 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 21301 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 106974940 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229436 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 60243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 60220 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 302796832 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264400 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 12032 # Nu
|
|||
system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1003461073 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 453692507 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1457153580 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1003461073 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1003461073 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1003461073 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 453692507 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1457153580 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1002123850 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 453087911 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1455211760 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1002123850 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1002123850 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1002123850 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 453087911 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1455211760 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 273 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 11901000 # Total gap between requests
|
||||
system.physmem.totGap 11917000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -154,51 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 42 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 339.809524 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 162.784505 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 471.889985 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 23 54.76% 54.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 1 2.38% 57.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 3 7.14% 64.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 1 2.38% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 2 4.76% 71.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 2 4.76% 76.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 2 4.76% 80.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 1 2.38% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 2 4.76% 88.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960 1 2.38% 90.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088 1 2.38% 92.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280 1 2.38% 95.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664 1 2.38% 97.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112 1 2.38% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 42 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1695750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7213250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 24 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 464 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 290.487911 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 387.347726 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 6 25.00% 25.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 4 16.67% 41.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 3 12.50% 54.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1 4.17% 58.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 8.33% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 8.33% 75.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6 25.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 24 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1638000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7265500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 4152500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6211.54 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15210.62 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 4262500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6000.00 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15613.55 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26422.16 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1457.15 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26613.55 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1455.21 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1457.15 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1455.21 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.38 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.37 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.60 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 231 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 225 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 84.62 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43593.41 # Average gap between requests
|
||||
system.physmem.pageHitRate 84.62 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 43652.01 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1457153580 # Throughput (bytes/s)
|
||||
system.membus.throughput 1455211760 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 249 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
|
|
@ -211,7 +236,7 @@ system.membus.data_through_bus 17472 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2552500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1176 # Number of BP lookups
|
||||
|
|
@ -227,18 +252,18 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 707 # DTB read hits
|
||||
system.cpu.dtb.read_hits 710 # DTB read hits
|
||||
system.cpu.dtb.read_misses 31 # DTB read misses
|
||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 738 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 741 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 368 # DTB write hits
|
||||
system.cpu.dtb.write_misses 20 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 388 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 1075 # DTB hits
|
||||
system.cpu.dtb.data_hits 1078 # DTB hits
|
||||
system.cpu.dtb.data_misses 51 # DTB misses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1126 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 1129 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1065 # ITB hits
|
||||
system.cpu.itb.fetch_misses 30 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -256,10 +281,10 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 23982 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 24014 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 4347 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken
|
||||
|
|
@ -271,11 +296,11 @@ system.cpu.fetch.PendingTrapStallCycles 1022 # Nu
|
|||
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 7720 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.908161 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.314945 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 7722 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.907925 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.314691 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6511 84.34% 84.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6513 84.34% 84.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -287,10 +312,10 @@ system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 7720 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049037 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.292344 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5485 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rateDist::total 7722 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.048971 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.291955 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5487 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1153 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking
|
||||
|
|
@ -300,52 +325,52 @@ system.cpu.decode.BranchMispred 81 # Nu
|
|||
system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5584 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 5585 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1062 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 1063 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5897 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 4276 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6670 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6663 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 4279 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6674 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6667 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 2508 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 2511 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 955 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 468 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 956 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 469 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 4960 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 4966 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 4040 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 4045 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 2335 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1384 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 7720 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.523316 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.238697 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 7722 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.523828 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.238657 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 6098 78.99% 78.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 566 7.33% 86.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 399 5.17% 91.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 262 3.39% 94.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 199 2.58% 97.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 121 1.57% 99.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 6098 78.97% 78.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 565 7.32% 86.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 401 5.19% 91.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 263 3.41% 94.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 200 2.59% 97.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 120 1.55% 99.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7720 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7722 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
|
||||
|
|
@ -381,57 +406,57 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 2861 70.82% 70.82% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 783 19.38% 90.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 395 9.78% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 2864 70.80% 70.80% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 785 19.41% 90.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 4040 # Type of FU issued
|
||||
system.cpu.iq.rate 0.168460 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 4045 # Type of FU issued
|
||||
system.cpu.iq.rate 0.168443 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010891 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15885 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7299 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3649 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15897 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 4077 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 4082 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 540 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 541 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 174 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 175 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
|
|
@ -440,42 +465,42 @@ system.cpu.iew.iewIdleCycles 0 # Nu
|
|||
system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 5302 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 5308 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 955 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 468 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 956 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 469 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 3849 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 742 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 190 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 336 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 1127 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 643 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 1130 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 644 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 388 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.160495 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3735 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3655 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1708 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2206 # num instructions consuming a value
|
||||
system.cpu.iew.exec_rate 0.160531 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3658 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1710 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2211 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.152406 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.774252 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.152328 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 2720 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 7226 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.356490 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.198597 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 7228 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.356392 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.198445 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 6357 87.97% 87.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 6359 87.98% 87.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle
|
||||
|
|
@ -487,7 +512,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 7226 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 7228 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -500,23 +525,23 @@ system.cpu.commit.int_insts 2367 # Nu
|
|||
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 12212 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11099 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 12220 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11111 # The number of ROB writes
|
||||
system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16262 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 16292 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 10.046921 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.046921 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.099533 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.099533 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4665 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2823 # number of integer regfile writes
|
||||
system.cpu.cpi 10.060327 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.060327 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.099400 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.099400 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4672 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2825 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1457153580 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1455211760 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
|
|
@ -531,19 +556,19 @@ system.cpu.toL2Bus.data_through_bus 17472 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 316000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 315500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 93.236237 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 93.163170 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 93.163170 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.045490 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.045490 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
|
||||
|
|
@ -562,12 +587,12 @@ system.cpu.icache.demand_misses::cpu.inst 250 # n
|
|||
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 250 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17655999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17655999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17655999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17655999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17655999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17655999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17591499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17591499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17591499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17591499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17591499 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17591499 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses
|
||||
|
|
@ -580,12 +605,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.234742
|
|||
system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70623.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70623.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70623.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70623.996000 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -606,36 +631,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188
|
|||
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162749 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13162749 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162749 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13162749 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162749 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13162749 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13162249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13162249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13162249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70014.622340 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70014.622340 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 122.122128 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 122.028433 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.433851 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.360563 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.667870 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002849 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
|
|
@ -653,17 +678,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12974000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4692750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17666750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1665750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6358500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19332500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12974000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6358500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19332500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12973500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4680750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17654250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1693750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1693750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12973500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6374500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12973500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6374500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19348000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -686,17 +711,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69010.638298 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76930.327869 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70950.803213 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69406.250000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69406.250000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70815.018315 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70815.018315 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -716,17 +741,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10604500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3946250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14550750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1371750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1371750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10604500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5318000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15922500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10604500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5318000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15922500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10603500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3934250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14537750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1399750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1399750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10603500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5334000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15937500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10603500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5334000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15937500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -738,81 +763,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.914894 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64692.622951 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58436.746988 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57156.250000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57156.250000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 45.667407 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 45.630537 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.630537 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011140 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011140 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1989 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1989 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 546 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 546 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 758 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 758 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 758 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 758 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 759 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 759 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 759 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 759 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 194 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 194 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7226000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7226000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5211250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12437250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12437250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12437250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12437250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 196 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 196 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 196 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 196 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5323250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5323250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13287250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13287250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13287250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13287250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 952 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 952 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 952 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 952 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.171733 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.171733 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 955 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 955 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 955 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 955 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173979 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.173979 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63946.902655 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63946.902655 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64336.419753 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64336.419753 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64109.536082 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64109.536082 # average overall miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
||||
|
|
@ -821,14 +846,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.250000
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 109 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 109 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 109 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 111 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
|
||||
|
|
@ -837,30 +862,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4753750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4753750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1691250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1691250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6445000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6445000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6445000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6445000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6461000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6461000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6461000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6461000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77930.327869 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77930.327869 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70468.750000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70468.750000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16981000 # Number of ticks simulated
|
||||
final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 17056000 # Number of ticks simulated
|
||||
final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 39940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 49834 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 147693403 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267784 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 29277 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36530 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 108745688 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308972 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu
|
|||
system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 392 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 16923500 # Total gap between requests
|
||||
system.physmem.totGap 16998500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3153000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 4223500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 5403750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.54 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.49 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 332 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 326 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43172.19 # Average gap between requests
|
||||
system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 43363.52 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1473647017 # Throughput (bytes/s)
|
||||
system.membus.throughput 1467166979 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -213,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25024 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2481 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
|
||||
|
|
@ -399,10 +420,10 @@ system.cpu.itb.inst_accesses 0 # IT
|
|||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 33963 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 34113 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
||||
|
|
@ -411,26 +432,26 @@ system.cpu.fetch.SquashCycles 1612 # Nu
|
|||
system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
||||
|
|
@ -440,7 +461,7 @@ system.cpu.decode.BranchMispred 159 # Nu
|
|||
system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
|
||||
|
|
@ -457,7 +478,7 @@ system.cpu.rename.CommittedMaps 5673 # Nu
|
|||
system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
|
||||
|
|
@ -469,23 +490,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
|
||||
|
|
@ -555,10 +576,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
||||
system.cpu.iq.rate 0.262668 # Inst issue rate
|
||||
system.cpu.iq.rate 0.261513 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
|
|
@ -599,35 +620,35 @@ system.cpu.iew.exec_nop 0 # nu
|
|||
system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.250950 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.249846 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3883 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -640,23 +661,23 @@ system.cpu.commit.int_insts 4976 # Nu
|
|||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23234 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 23225 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23415 # The number of ROB writes
|
||||
system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39210 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -671,19 +692,19 @@ system.cpu.toL2Bus.data_through_bus 27904 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
||||
|
|
@ -702,12 +723,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n
|
|||
system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 363 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
||||
|
|
@ -720,12 +741,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441
|
|||
system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -746,39 +767,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290
|
|||
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
|
||||
|
|
@ -802,17 +823,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -835,17 +856,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -871,17 +892,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -893,27 +914,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
|
||||
|
|
@ -942,16 +963,16 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n
|
|||
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -974,16 +995,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.172883
|
|||
system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -1010,14 +1031,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1026,14 +1047,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16981000 # Number of ticks simulated
|
||||
final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 17056000 # Number of ticks simulated
|
||||
final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45620 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56920 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 168691831 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267756 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 53685 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 66982 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 199380443 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308976 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu
|
|||
system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 392 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 16923500 # Total gap between requests
|
||||
system.physmem.totGap 16998500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3153000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 4223500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 5403750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.54 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.49 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 332 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 326 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43172.19 # Average gap between requests
|
||||
system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 43363.52 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1473647017 # Throughput (bytes/s)
|
||||
system.membus.throughput 1467166979 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -213,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25024 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2481 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
|
||||
|
|
@ -312,10 +333,10 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 33963 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 34113 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
||||
|
|
@ -324,26 +345,26 @@ system.cpu.fetch.SquashCycles 1612 # Nu
|
|||
system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
||||
|
|
@ -353,7 +374,7 @@ system.cpu.decode.BranchMispred 159 # Nu
|
|||
system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
|
||||
|
|
@ -370,7 +391,7 @@ system.cpu.rename.CommittedMaps 5673 # Nu
|
|||
system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
|
||||
|
|
@ -382,23 +403,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
|
||||
|
|
@ -468,10 +489,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
||||
system.cpu.iq.rate 0.262668 # Inst issue rate
|
||||
system.cpu.iq.rate 0.261513 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
|
|
@ -512,35 +533,35 @@ system.cpu.iew.exec_nop 0 # nu
|
|||
system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.250950 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.249846 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3883 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -553,23 +574,23 @@ system.cpu.commit.int_insts 4976 # Nu
|
|||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23234 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 23225 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23415 # The number of ROB writes
|
||||
system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39210 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -584,19 +605,19 @@ system.cpu.toL2Bus.data_through_bus 27904 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
||||
|
|
@ -615,12 +636,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n
|
|||
system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 363 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
||||
|
|
@ -633,12 +654,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441
|
|||
system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -659,39 +680,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290
|
|||
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
|
||||
|
|
@ -715,17 +736,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -748,17 +769,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -784,17 +805,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -806,27 +827,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
|
||||
|
|
@ -855,16 +876,16 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n
|
|||
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -887,16 +908,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.172883
|
|||
system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -923,14 +944,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -939,14 +960,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 24975000 # Number of ticks simulated
|
||||
final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 42229 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 181364329 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230516 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 86020 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 86001 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 369354314 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263428 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 303 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
|
|
@ -154,34 +154,59 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3167500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 267.093333 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 186.339521 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 256.296765 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 18 24.00% 24.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 29 38.67% 62.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9 12.00% 74.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 8 10.67% 85.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 4 5.33% 90.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1 1.33% 92.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 1.33% 93.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 5 6.67% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3086250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13542500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 8112500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 8181250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6782.97 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 17980.77 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 29763.74 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -190,14 +215,14 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 9.11 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 348 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 344 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 75.60 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 54712.09 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined
|
||||
system.physmem.pageHitRate 75.60 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1165965966 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 404 # Transaction distribution
|
||||
|
|
@ -212,8 +237,8 @@ system.membus.data_through_bus 29120 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4258000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1156 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted
|
||||
|
|
@ -294,24 +319,24 @@ system.cpu.stage0.utilization 7.303157 # Pe
|
|||
system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 47184 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 5.539429 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 47063 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 5.781666 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 150.508435 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 150.508435 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073490 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073490 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
|
||||
|
|
@ -330,12 +355,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n
|
|||
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25364500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25364500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25364500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25364500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25364500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25364500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
|
||||
|
|
@ -348,12 +373,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871
|
|||
system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72470 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 72470 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72470 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 72470 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72470 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 72470 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -374,24 +399,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
|
|||
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23031000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23031000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23031000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23031000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23031000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23031000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
|
||||
|
|
@ -408,21 +433,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 538000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 225500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 208.255183 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.186433 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.068750 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004644 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id
|
||||
|
|
@ -446,17 +471,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22685500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6903000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29588500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3846500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3846500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22685500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10749500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 33435000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22685500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10749500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 33435000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -479,17 +504,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -509,17 +534,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18705000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5824500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24529500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18705000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9029000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27734000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18705000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9029000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27734000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -531,27 +556,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 90.278621 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 90.278621 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022041 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022041 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
|
||||
|
|
@ -574,14 +599,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n
|
|||
system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 450 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7687000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7687000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21761250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21761250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29448250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29448250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29448250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29448250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -598,14 +623,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517
|
|||
system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65440.555556 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65440.555556 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
|
||||
|
|
@ -630,14 +655,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6996500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6996500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3900500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3900500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10897000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10897000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10897000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10897000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -646,14 +671,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
sim_ticks 21898500 # Number of ticks simulated
|
||||
final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 21918500 # Number of ticks simulated
|
||||
final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 38049 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38045 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 161516903 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231544 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 56826 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 241494238 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266500 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 5156 # Number of instructions simulated
|
||||
sim_ops 5156 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu
|
|||
system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 477 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 979062493 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 415005594 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1394068087 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 979062493 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 979062493 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 979062493 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 415005594 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1394068087 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 477 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 21819000 # Total gap between requests
|
||||
system.physmem.totGap 21839000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -154,52 +154,77 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 118 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 230.508475 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 147.858901 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 317.434070 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 46 38.98% 38.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 20 16.95% 55.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 19 16.10% 72.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 8 6.78% 78.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 7 5.93% 84.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 3 2.54% 87.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 4 3.39% 90.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 2 1.69% 92.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576 2 1.69% 94.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 1 0.85% 94.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 1 0.85% 95.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832 1 0.85% 96.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 2 1.69% 98.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920 1 0.85% 99.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368 1 0.85% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 118 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2620250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13667750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2715000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 8662500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5493.19 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 18160.38 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 8676250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28653.56 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1394.07 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1394.07 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 10.89 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.89 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 10.88 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 359 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 357 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 45742.14 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.26 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 45784.07 # Average gap between requests
|
||||
system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1394068087 # Throughput (bytes/s)
|
||||
system.membus.throughput 1392796040 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 426 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 426 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
|
|
@ -212,7 +237,7 @@ system.membus.data_through_bus 30528 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2174 # Number of BP lookups
|
||||
|
|
@ -243,40 +268,40 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 43798 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 43838 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 8822 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 1344 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 14432 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.913456 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.225567 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 11219 77.74% 77.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1317 9.13% 86.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 104 0.72% 87.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 131 0.91% 88.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 115 0.80% 91.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 150 1.04% 92.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing
|
||||
|
|
@ -285,9 +310,9 @@ system.cpu.decode.BranchMispred 43 # Nu
|
|||
system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
|
||||
|
|
@ -314,23 +339,23 @@ system.cpu.iq.iqSquashedInstsIssued 39 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 14432 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.574626 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.242806 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10849 75.17% 75.17% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1422 9.85% 85.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 891 6.17% 91.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 553 3.83% 95.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 355 2.46% 97.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 226 1.57% 99.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 89 0.62% 99.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 14432 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
|
||||
|
|
@ -400,10 +425,10 @@ system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8293 # Type of FU issued
|
||||
system.cpu.iq.rate 0.189347 # Inst issue rate
|
||||
system.cpu.iq.rate 0.189174 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 160 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31213 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
||||
|
|
@ -444,35 +469,35 @@ system.cpu.iew.exec_nop 1512 # nu
|
|||
system.cpu.iew.exec_refs 3186 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1344 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1079 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.180648 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.180483 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7455 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2921 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 4197 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.170213 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 13564 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.428561 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.209396 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 11162 82.29% 82.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 999 7.37% 89.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 630 4.64% 94.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 315 2.32% 96.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 149 1.10% 97.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 94 0.69% 98.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 13564 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5813 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -485,23 +510,23 @@ system.cpu.commit.int_insts 5111 # Nu
|
|||
system.cpu.commit.function_calls 87 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 24172 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 24245 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 22333 # The number of ROB writes
|
||||
system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 29366 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5156 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
|
||||
system.cpu.cpi 8.494569 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 8.494569 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.117722 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.117722 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 10743 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5234 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 148 # number of misc regfile reads
|
||||
system.cpu.toL2Bus.throughput 1402835811 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
|
|
@ -518,17 +543,17 @@ system.cpu.toL2Bus.reqLayer0.occupancy 240000 # La
|
|||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 227500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 161.632436 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
|
||||
|
|
@ -547,12 +572,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n
|
|||
system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 451 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
|
||||
|
|
@ -565,12 +590,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517
|
|||
system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -591,39 +616,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338
|
|||
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses
|
||||
|
|
@ -644,17 +669,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 477 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -677,17 +702,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -707,17 +732,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19597750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5909750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25507500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19597750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9093000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 28690750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19597750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9093000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 28690750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -729,27 +754,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 91.712882 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
|
|
@ -772,14 +797,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n
|
|||
system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 510 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10190250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10190250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22575249 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22575249 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32765499 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32765499 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32765499 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32765499 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -796,14 +821,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559
|
|||
system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64246.076471 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64246.076471 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
||||
|
|
@ -828,14 +853,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142
|
|||
system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866249 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866249 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10987499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10987499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10987499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10987499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -844,14 +869,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18905500 # Number of ticks simulated
|
||||
final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 19079500 # Number of ticks simulated
|
||||
final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 44009 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44004 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 143620144 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227496 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_inst_rate 82615 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 82599 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 272039638 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262500 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu
|
|||
system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 446 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 18777000 # Total gap between requests
|
||||
system.physmem.totGap 18951000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -154,55 +154,77 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3018500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2851500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 6710000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 6902500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.80 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.69 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 368 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 358 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 42100.90 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 42491.03 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1509825183 # Throughput (bytes/s)
|
||||
system.membus.throughput 1496055976 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
|
|
@ -213,19 +235,19 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.9 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2238 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 2235 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 603 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 1850 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 602 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 32.540541 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
|
|
@ -246,84 +268,84 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 9 # Number of system calls
|
||||
system.cpu.numCycles 37812 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 38160 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2263 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2098 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2094 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1987 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11308 # Number of instructions processed by rename
|
||||
system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18166 # Number of integer rename lookups
|
||||
system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 575 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 8901 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
|
||||
|
|
@ -331,7 +353,7 @@ system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available
|
||||
|
|
@ -367,50 +389,50 @@ system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5476 61.52% 61.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1796 20.18% 81.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8904 # Type of FU issued
|
||||
system.cpu.iq.rate 0.235481 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 8901 # Type of FU issued
|
||||
system.cpu.iq.rate 0.233255 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -426,7 +448,7 @@ system.cpu.iew.iewIdleCycles 0 # Nu
|
|||
system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 10362 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
|
||||
|
|
@ -437,43 +459,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 8500 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3202 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1351 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1524 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.224876 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8158 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 4220 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6682 # num instructions consuming a value
|
||||
system.cpu.iew.exec_refs 3201 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1350 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1523 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.222746 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8155 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 4217 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6678 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5792 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -486,22 +508,22 @@ system.cpu.commit.int_insts 5698 # Nu
|
|||
system.cpu.commit.function_calls 103 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 21334 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21446 # The number of ROB writes
|
||||
system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 21343 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21442 # The number of ROB writes
|
||||
system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 13476 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7049 # number of integer regfile writes
|
||||
system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 13470 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7047 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
|
|
@ -516,111 +538,111 @@ system.cpu.toL2Bus.data_through_bus 28992 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 3979 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 3979 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1372 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1372 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1372 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 442 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1814 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1814 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1814 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243660 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.243660 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked
|
||||
system.cpu.icache.tags.tag_accesses 3971 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 3971 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1369 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1369 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1369 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1369 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1369 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1369 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 441 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1810 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1810 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1810 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243646 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.243646 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 72.166667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
|
||||
|
|
@ -647,17 +669,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24063500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 28138000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3590250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3590250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 24063500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7664750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31728250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 24063500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7664750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31728250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -680,17 +702,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -710,17 +732,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6423750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6423750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -732,27 +754,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
|
||||
|
|
@ -775,14 +797,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n
|
|||
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 435 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7365250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7365250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19851746 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19851746 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 27216996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 27216996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 27216996 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 27216996 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -799,14 +821,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165841
|
|||
system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62567.806897 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
|
|
@ -833,12 +855,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 102
|
|||
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -849,12 +871,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 20892500 # Number of ticks simulated
|
||||
final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 20970500 # Number of ticks simulated
|
||||
final_tick 20970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24019 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24017 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 94189663 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236900 # Number of bytes of host memory used
|
||||
host_seconds 0.22 # Real time elapsed on the host
|
||||
host_inst_rate 71497 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71482 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 281347268 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269780 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu
|
|||
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 882000906 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 408955437 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1290956343 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 882000906 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 882000906 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 882000906 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 408955437 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1290956343 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 423 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 20823000 # Total gap between requests
|
||||
system.physmem.totGap 20901000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -154,53 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3229250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 48 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 337.333333 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 221.579222 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 300.401245 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 13 27.08% 27.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 9 18.75% 45.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 6 12.50% 58.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 7 14.58% 72.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 6 12.50% 85.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 4.17% 89.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 5 10.42% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 48 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3113750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11732500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 6490000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 6503750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 7361.11 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15375.30 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 27736.41 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1290.96 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1290.96 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 10.12 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 10.09 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.09 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 343 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 339 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 49226.95 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 49411.35 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1295775996 # Throughput (bytes/s)
|
||||
system.membus.throughput 1290956343 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 342 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 342 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
|
|
@ -211,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 18.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3929500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 18.7 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1636 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
|
||||
|
|
@ -226,7 +249,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT
|
|||
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 41786 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 41942 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -248,12 +271,12 @@ system.cpu.execution_unit.executions 3957 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9659 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 14.945197 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35694 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6248 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 14.896762 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 715 # Number of Load instructions committed
|
||||
system.cpu.comStores 673 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1115 # Number of Branches instructions committed
|
||||
|
|
@ -265,39 +288,39 @@ system.cpu.committedInsts 5327 # Nu
|
|||
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 7.873475 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 7.873475 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.127009 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.127009 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 37302 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 11.062896 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 38748 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 7.615278 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 38908 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 7.233799 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 40966 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.327023 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38785 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 7.527061 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 142.644710 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.644710 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069651 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069651 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2807 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2807 # Number of data accesses
|
||||
|
|
@ -313,12 +336,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n
|
|||
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 366 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25482750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25482750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25482750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25482750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25482750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25482750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
|
||||
|
|
@ -331,12 +354,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938
|
|||
system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69625 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69625 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69625 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69625 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69625 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69625 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -357,26 +380,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
|
|||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20711750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20711750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20711750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20711750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20711750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20711750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1300112062 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
|
|
@ -391,21 +414,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 485750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 216250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 169.087834 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.075458 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.012376 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004336 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005160 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
|
||||
|
|
@ -432,17 +455,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20393250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4031000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24424250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6031750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6031750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20393250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10062750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30456000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20393250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10062750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30456000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -465,17 +488,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -495,17 +518,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16781250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20157250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5037250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5037250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16781250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 25194500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16781250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25194500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -517,27 +540,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 85.369033 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.369033 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
|
||||
|
|
@ -560,14 +583,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n
|
|||
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4594750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4594750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29091500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 29091500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33686250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33686250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33686250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33686250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -584,19 +607,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499
|
|||
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 71068.037975 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 71068.037975 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.548387 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -616,14 +639,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
|||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4097500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4097500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6115250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6115250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10212750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10212750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10212750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10212750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -632,14 +655,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 19970500 # Number of ticks simulated
|
||||
final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 20069500 # Number of ticks simulated
|
||||
final_tick 20069500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4162 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 7540 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15448311 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248568 # Number of bytes of host memory used
|
||||
host_seconds 1.29 # Real time elapsed on the host
|
||||
host_inst_rate 42536 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 77054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 158640887 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 283320 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17472 # Nu
|
|||
system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 414 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 870574753 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 449637510 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1320212262 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 870574753 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 870574753 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 870574753 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 449637510 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1320212262 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 415 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 19922000 # Total gap between requests
|
||||
system.physmem.totGap 20021000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -154,50 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2039250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 240.676056 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 152.837127 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 281.987222 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 26 36.62% 36.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 26 36.62% 73.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8 11.27% 84.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2 2.82% 87.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 2.82% 90.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 2.82% 92.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 5 7.04% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2360500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12135500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 7617500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 7700000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5687.95 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 18554.22 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 29242.17 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1323.40 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1323.40 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 10.39 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 10.34 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.34 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 312 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 307 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 48004.82 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1326756967 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 48243.37 # Average gap between requests
|
||||
system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1320212262 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 338 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 337 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 77 # Transaction distribution
|
||||
|
|
@ -212,8 +238,8 @@ system.membus.data_through_bus 26496 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 19.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3871750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 19.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 3084 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted
|
||||
|
|
@ -226,49 +252,49 @@ system.cpu.branchPred.usedRAS 207 # Nu
|
|||
system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 39942 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 40140 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 10289 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 5352 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 21899 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.150509 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.666400 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 18060 82.47% 82.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 216 0.99% 83.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.02% 85.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 181 0.83% 85.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 200 0.91% 86.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 159 0.73% 88.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 2442 11.15% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 21899 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.076831 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.352118 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 11081 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 5247 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 3583 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking
|
||||
system.cpu.rename.IdleCycles 11446 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 3331 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking
|
||||
|
|
@ -296,23 +322,23 @@ system.cpu.iq.iqSquashedInstsIssued 290 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 21899 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.777524 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.652832 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 16413 74.95% 74.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1539 7.03% 81.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1092 4.99% 86.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 724 3.31% 90.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 698 3.19% 93.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 576 2.63% 96.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 581 2.65% 98.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 21899 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available
|
||||
|
|
@ -382,10 +408,10 @@ system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 17027 # Type of FU issued
|
||||
system.cpu.iq.rate 0.426293 # Inst issue rate
|
||||
system.cpu.iq.rate 0.424190 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 56416 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
||||
|
|
@ -405,7 +431,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 #
|
|||
system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewBlockCycles 3086 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch
|
||||
|
|
@ -426,27 +452,27 @@ system.cpu.iew.exec_nop 0 # nu
|
|||
system.cpu.iew.exec_refs 3127 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1623 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1273 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.403685 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.401694 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 15646 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 10128 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 15579 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.389786 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 20042 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.486329 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.342699 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 16474 82.20% 82.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 364 1.82% 97.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle
|
||||
|
|
@ -454,7 +480,7 @@ system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 20042 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5380 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -467,17 +493,17 @@ system.cpu.commit.int_insts 9653 # Nu
|
|||
system.cpu.commit.function_calls 106 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 40049 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 40103 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 42426 # The number of ROB writes
|
||||
system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 18241 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 7.460967 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.460967 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.134031 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.134031 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 20727 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 12358 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
||||
|
|
@ -485,7 +511,7 @@ system.cpu.cc_regfile_reads 8004 # nu
|
|||
system.cpu.cc_regfile_writes 4850 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 7135 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1326590099 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
|
||||
|
|
@ -500,19 +526,19 @@ system.cpu.toL2Bus.data_through_bus 26624 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 458250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 235500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 130.897576 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 130.897576 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
||||
|
|
@ -531,12 +557,12 @@ system.cpu.icache.demand_misses::cpu.inst 371 # n
|
|||
system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 371 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25180750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25180750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25180750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25180750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25180750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25180750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses
|
||||
|
|
@ -549,12 +575,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.187374
|
|||
system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67621.967655 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67621.967655 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67872.641509 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67872.641509 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -575,39 +601,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 274
|
|||
system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19639000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19639000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19639000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19639000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19639000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19639000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19745750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19745750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19745750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19745750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19745750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19745750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71675.182482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71675.182482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 163.766589 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 163.708534 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.016356 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.750233 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.966386 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.742148 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003997 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004996 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses
|
||||
|
|
@ -631,17 +657,17 @@ system.cpu.l2cache.demand_misses::total 415 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 415 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19353500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5004000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24357500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5417000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5417000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10421000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29774500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19353500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10421000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29774500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19460250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5265000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24725250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5444500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5444500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19460250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10709500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30169750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19460250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10709500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30169750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -664,17 +690,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995204 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -694,17 +720,17 @@ system.cpu.l2cache.demand_mshr_misses::total 415
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15927500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4205500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20133000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4457500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4457500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15927500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8663000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24590500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15927500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8663000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24590500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16034750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4466500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20501250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4485000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4485000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16034750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8951500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24986250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16034750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8951500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24986250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -716,27 +742,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 83.239431 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 83.267922 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.239431 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020322 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020322 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.267922 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020329 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020329 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
|
||||
|
|
@ -759,14 +785,14 @@ system.cpu.dcache.demand_misses::cpu.data 209 # n
|
|||
system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 209 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9408000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9408000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5676000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5676000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15084000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15084000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9669000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9669000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5702500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5702500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15371500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15371500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15371500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15371500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -783,14 +809,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082090
|
|||
system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73250 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73250 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73547.846890 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73547.846890 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
||||
|
|
@ -813,14 +839,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143
|
|||
system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5340000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5340000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10861500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10861500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -829,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27705000 # Number of ticks simulated
|
||||
final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 27725000 # Number of ticks simulated
|
||||
final_tick 27725000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 23200 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 23199 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42390050 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236824 # Number of bytes of host memory used
|
||||
host_seconds 0.65 # Real time elapsed on the host
|
||||
host_inst_rate 72342 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72337 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 132265036 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269700 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 19008 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 27904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 27840 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 19008 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 19008 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::total 435 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 685590622 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 318557259 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1004147881 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 685590622 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 685590622 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 685590622 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 318557259 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1004147881 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 436 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 27671500 # Total gap between requests
|
||||
system.physmem.totGap 27691500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2393750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 487.111111 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 330.231493 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 390.430808 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 3 8.33% 8.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 9 25.00% 33.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8 22.22% 55.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2 5.56% 61.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 5.56% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 2.78% 69.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 11 30.56% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2136500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10682750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 6256250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 6366250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 4900.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14601.49 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 24501.72 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1006.46 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1006.46 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.87 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 7.86 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.86 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 372 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 362 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 63466.74 # Average gap between requests
|
||||
system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1004872767 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 63512.61 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 4.51 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1004147881 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
|
|
@ -213,9 +234,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27840 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4047500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 14.6 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 5146 # Number of BP lookups
|
||||
|
|
@ -228,7 +249,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT
|
|||
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 55411 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 55451 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -250,12 +271,12 @@ system.cpu.execution_unit.executions 11045 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 21862 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.timesIdled 439 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 37883 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 31.704896 # Percentage of cycles cpu is active
|
||||
system.cpu.activity 31.682026 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 2225 # Number of Load instructions committed
|
||||
system.cpu.comStores 1448 # Number of Store instructions committed
|
||||
system.cpu.comBranches 3358 # Number of Branches instructions committed
|
||||
|
|
@ -267,39 +288,39 @@ system.cpu.committedInsts 15162 # Nu
|
|||
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 3.657235 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 3.657235 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.273431 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.273431 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 42025 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 24.212368 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 46098 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 16.867144 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 46648 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 15.875277 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 52573 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 5.190168 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 46142 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 16.787795 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 168.846335 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.846335 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082444 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082444 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.145996 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 7069 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 7069 # Number of data accesses
|
||||
|
|
@ -315,12 +336,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n
|
|||
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 381 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25942000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25942000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25942000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25942000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
|
||||
|
|
@ -333,12 +354,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555
|
|||
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68089.238845 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68089.238845 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68089.238845 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68089.238845 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68089.238845 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68089.238845 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -359,26 +380,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
|
|||
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20512000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20512000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20512000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20512000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20512000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20512000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68146.179402 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68146.179402 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68146.179402 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68146.179402 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68146.179402 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68146.179402 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1008764653 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
|
|
@ -393,21 +414,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 499500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 221500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 199.869816 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.179067 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.690749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005132 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000967 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006100 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
|
||||
|
|
@ -431,17 +452,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20188500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 23889500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6006500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6006500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20188500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9707500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29896000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20188500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9707500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29896000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -464,17 +485,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67520.066890 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69830.188679 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67867.897727 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70664.705882 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70664.705882 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67520.066890 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70344.202899 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68411.899314 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67520.066890 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70344.202899 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68411.899314 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -494,17 +515,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16473000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19515500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4962500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4962500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16473000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8005000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24478000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16473000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8005000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24478000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -516,27 +537,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55093.645485 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57405.660377 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55441.761364 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58382.352941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58382.352941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55093.645485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58007.246377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56013.729977 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55093.645485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58007.246377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56013.729977 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 98.543212 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.543212 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024058 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024058 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
|
|
@ -561,14 +582,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n
|
|||
system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 480 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4273500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4273500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25910250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25910250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30183750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30183750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30183750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -587,19 +608,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897
|
|||
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73681.034483 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73681.034483 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61398.696682 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61398.696682 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62882.812500 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62882.812500 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62882.812500 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62882.812500 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1097 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.969697 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.242424 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -619,14 +640,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6094500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6094500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9850000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9850000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9850000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9850000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -635,14 +656,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70858.490566 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70858.490566 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71700 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71700 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71376.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71376.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71376.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71376.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 26616500 # Number of ticks simulated
|
||||
final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 26743500 # Number of ticks simulated
|
||||
final_tick 26743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19079 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19079 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35176168 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237844 # Number of bytes of host memory used
|
||||
host_seconds 0.76 # Real time elapsed on the host
|
||||
host_inst_rate 53060 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 53057 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98286640 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272776 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu
|
|||
system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 801690130 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 351786415 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1153476546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 801690130 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 801690130 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 801690130 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 351786415 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1153476546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 482 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 26455500 # Total gap between requests
|
||||
system.physmem.totGap 26582500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -154,55 +154,77 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2423000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 448 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 298.774659 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 377.002918 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 5 12.20% 12.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 12 29.27% 41.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 7 17.07% 58.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2 4.88% 63.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 4.88% 68.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1 2.44% 70.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 4.88% 75.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 24.39% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2269000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11609000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 6778750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 6930000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 4707.47 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14377.59 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 24085.06 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1153.48 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1153.48 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 9.05 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 9.01 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 9.01 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 413 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 403 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 54886.93 # Average gap between requests
|
||||
system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1158980332 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 55150.41 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 5.72 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1153476546 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
|
|
@ -213,105 +235,105 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30848 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4495000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 16.8 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 6713 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 6710 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 4453 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 5017 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2432 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 48.475184 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 53234 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 53488 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.icacheStallCycles 12425 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 31097 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6710 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.Cycles 9129 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3043 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 9229 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched
|
||||
system.cpu.fetch.CacheLines 5378 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 33579 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.926085 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.119056 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24450 72.81% 72.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4510 13.43% 86.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 474 1.41% 87.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 392 1.17% 88.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 680 2.03% 90.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 706 2.10% 92.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 235 0.70% 93.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 253 0.75% 94.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1879 5.60% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 8343 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 7952 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename
|
||||
system.cpu.fetch.rateDist::total 33579 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.125449 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.581383 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 12934 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 10235 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 8342 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1871 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 28992 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1871 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 13577 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 435 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 9274 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 7946 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 476 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 26641 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups
|
||||
system.cpu.rename.LSQFullEvents 148 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 23939 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 49429 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 40899 # Number of integer rename lookups
|
||||
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 10120 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 2745 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 3528 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 2282 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 22511 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 21117 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 7892 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5484 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 33579 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.628875 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.255627 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 24339 72.48% 72.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3553 10.58% 83.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2322 6.92% 89.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1704 5.07% 95.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 887 2.64% 97.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 469 1.40% 99.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 240 0.71% 99.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 33579 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
|
||||
|
|
@ -347,7 +369,7 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 15648 74.10% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued
|
||||
|
|
@ -377,39 +399,39 @@ system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 2107 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 21122 # Type of FU issued
|
||||
system.cpu.iq.rate 0.396776 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 21117 # Type of FU issued
|
||||
system.cpu.iq.rate 0.394799 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes
|
||||
system.cpu.iq.fu_busy_rate 0.006961 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 76057 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 31084 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 21264 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1303 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 834 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewSquashCycles 1871 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 286 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 3528 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2282 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
|
|
@ -419,41 +441,41 @@ system.cpu.iew.predictedNotTakenIncorrect 946 # N
|
|||
system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 1043 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 1134 # number of nop insts executed
|
||||
system.cpu.iew.exec_nop 1133 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 5224 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 4239 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 2022 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.377090 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.375299 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 19522 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 9120 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 11235 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 9122 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 11233 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.364979 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.812072 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 31708 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.478176 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.176132 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 24394 76.93% 76.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 4067 12.83% 89.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1357 4.28% 94.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 765 2.41% 96.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 68 0.21% 99.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 31708 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 15162 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -466,22 +488,22 @@ system.cpu.commit.int_insts 12174 # Nu
|
|||
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 54530 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 50298 # The number of ROB writes
|
||||
system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 54969 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 50281 # The number of ROB writes
|
||||
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19909 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 3.705181 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.705181 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.269892 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.269892 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 32043 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17841 # number of integer regfile writes
|
||||
system.cpu.misc_regfile_reads 6919 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1158262755 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
|
|
@ -496,61 +518,61 @@ system.cpu.toL2Bus.data_through_bus 30976 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 562250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 233750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 187.339200 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4870 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.451039 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 187.339200 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.091474 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.091474 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 11095 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4872 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 507 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency
|
||||
system.cpu.icache.tags.tag_accesses 11093 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 11093 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4870 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4870 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4870 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4870 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4870 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4870 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 508 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5378 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5378 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5378 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5378 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5378 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5378 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094459 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.094459 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.094459 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.094459 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.094459 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.094459 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62312.007874 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62312.007874 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62312.007874 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62312.007874 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -559,48 +581,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 171 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 171 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 171 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 171 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 171 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22543250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22543250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22543250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22543250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22543250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22543250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062663 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.062663 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.062663 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66893.916914 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66893.916914 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 221.171170 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.732473 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.438696 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005699 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id
|
||||
|
|
@ -624,17 +646,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 482 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22186250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4642250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26828500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6101000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6101000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22186250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10743250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22186250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10743250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -657,17 +679,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66227.611940 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72535.156250 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67239.348371 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73506.024096 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73506.024096 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68318.464730 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68318.464730 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -687,17 +709,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17979250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3856250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21835500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5083000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5083000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17979250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8939250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26918500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17979250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8939250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26918500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -709,27 +731,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53669.402985 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60253.906250 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54725.563910 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61240.963855 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61240.963855 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 99.038544 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 99.038544 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024179 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024179 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
||||
|
|
@ -754,14 +776,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n
|
|||
system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 535 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7972250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7972250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25777976 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25777976 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33750226 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33750226 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33750226 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33750226 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -780,19 +802,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102
|
|||
system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63271.825397 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63271.825397 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63026.836186 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 63026.836186 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63084.534579 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63084.534579 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.461538 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -812,14 +834,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4706750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4706750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6185000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6185000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10891750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10891750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10891750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10891750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -828,14 +850,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73542.968750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73542.968750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74518.072289 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74518.072289 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 33856013702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 195468 # Number of bytes of host memory used
|
||||
host_seconds 2.95 # Real time elapsed on the host
|
||||
host_tick_rate 24940417343 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228644 # Number of bytes of host memory used
|
||||
host_seconds 4.01 # Real time elapsed on the host
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
|
||||
|
|
@ -78,18 +78,18 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3150208 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 42074 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 2967921 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 224361 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 16917 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 15990 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 12952 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 13879 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 16917 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 15990 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 4489 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 5416 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
|
|
@ -142,118 +142,51 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 38918 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 5478.771982 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 4240.637477 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 2732.249719 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 284 0.73% 0.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 264 0.68% 1.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 268 0.69% 2.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 268 0.69% 2.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 266 0.68% 3.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 271 0.70% 4.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 268 0.69% 4.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 264 0.68% 5.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 268 0.69% 6.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832-833 270 0.69% 6.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-897 267 0.69% 7.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960-961 268 0.69% 8.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 268 0.69% 8.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 264 0.68% 9.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 270 0.69% 10.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 3 0.01% 10.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 268 0.69% 11.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 264 0.68% 11.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472-1473 268 0.69% 12.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600-1601 268 0.69% 13.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664-1665 267 0.69% 13.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1728-1729 271 0.70% 14.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856-1857 268 0.69% 15.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920-1921 264 0.68% 15.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984-1985 268 0.69% 16.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112-2113 271 0.70% 17.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2176-2177 266 0.68% 17.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240-2241 268 0.69% 18.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368-2369 268 0.69% 19.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2432-2433 264 0.68% 19.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2496-2497 271 0.70% 20.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2560-2561 2 0.01% 20.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2624-2625 268 0.69% 21.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2688-2689 264 0.68% 22.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2752-2753 268 0.69% 22.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2880-2881 268 0.69% 23.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2944-2945 267 0.69% 24.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3008-3009 270 0.69% 24.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3136-3137 268 0.69% 25.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3200-3201 264 0.68% 26.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3264-3265 268 0.69% 26.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3392-3393 349 0.90% 27.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3456-3457 264 0.68% 28.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3520-3521 268 0.69% 29.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3648-3649 268 0.69% 29.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3712-3713 264 0.68% 30.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3776-3777 268 0.69% 31.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3904-3905 268 0.69% 31.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3968-3969 264 0.68% 32.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4032-4033 268 0.69% 33.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4160-4161 268 0.69% 33.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4224-4225 264 0.68% 34.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4288-4289 268 0.69% 35.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4416-4417 268 0.69% 35.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4480-4481 264 0.68% 36.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4544-4545 268 0.69% 37.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4672-4673 268 0.69% 38.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4736-4737 264 0.68% 38.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4800-4801 268 0.69% 39.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4928-4929 268 0.69% 40.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4992-4993 264 0.68% 40.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5056-5057 268 0.69% 41.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5184-5185 267 0.69% 42.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5248-5249 264 0.68% 42.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5312-5313 268 0.69% 43.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5440-5441 267 0.69% 44.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5504-5505 264 0.68% 44.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5568-5569 268 0.69% 45.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5696-5697 267 0.69% 46.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5760-5761 264 0.68% 46.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5824-5825 268 0.69% 47.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5952-5953 267 0.69% 48.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6016-6017 264 0.68% 48.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6080-6081 268 0.69% 49.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6208-6209 267 0.69% 50.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6272-6273 264 0.68% 51.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6336-6337 268 0.69% 51.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6464-6465 267 0.69% 52.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6528-6529 264 0.68% 53.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6592-6593 268 0.69% 53.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6720-6721 267 0.69% 54.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6784-6785 264 0.68% 55.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6848-6849 268 0.69% 55.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6976-6977 267 0.69% 56.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7040-7041 264 0.68% 57.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7104-7105 268 0.69% 57.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7232-7233 268 0.69% 58.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7296-7297 264 0.68% 59.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7360-7361 268 0.69% 59.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7488-7489 268 0.69% 60.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7552-7553 264 0.68% 61.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7616-7617 268 0.69% 61.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7744-7745 268 0.69% 62.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7808-7809 264 0.68% 63.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7872-7873 268 0.69% 64.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8000-8001 268 0.69% 64.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8064-8065 264 0.68% 65.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8128-8129 268 0.69% 66.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 13193 33.90% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38918 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27766345550 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 88702111800 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 195487 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 1024 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 1024.000000 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 195487 100.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 195487 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27932046800 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 91374259300 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 44269266250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 8329.99 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13280.91 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 46775712500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 8379.70 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14032.85 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26610.90 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27412.55 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -262,15 +195,15 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 16.67 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.89 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.33 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 3294382 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 3112095 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 98.83 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 93.36 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 30000.29 # Average gap between requests
|
||||
system.physmem.pageHitRate 98.83 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.11 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 2133311360 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
|
||||
|
|
@ -281,7 +214,7 @@ system.membus.tot_pkt_size::total 213331136 # Cu
|
|||
system.membus.data_through_bus 213331136 # Total data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 17154822550 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.occupancy 17200626050 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
|
||||
system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
|
||||
|
|
@ -335,8 +268,8 @@ system.monitor.writeBurstLengthHist::19 0 # Hi
|
|||
system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::gmean 2133311357.398473 # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::stdev 105886.111402 # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::gmean 2133311357.360062 # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::stdev 106664.726883 # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
|
||||
system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
|
||||
|
|
@ -388,19 +321,19 @@ system.monitor.writeBandwidthHist::total 100 # Hi
|
|||
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
|
||||
system.monitor.totalWrittenBytes 0 # Number of bytes written
|
||||
system.monitor.readLatencyHist::samples 3333299 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 46636.264419 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 41775.198419 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 39874.537130 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 47438.751234 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 42490.722724 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 40033.411924 # Read request-response latency
|
||||
system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 3183561 95.51% 95.51% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 17049 0.51% 96.02% # Read request-response latency
|
||||
system.monitor.readLatencyHist::98304-131071 17311 0.52% 96.54% # Read request-response latency
|
||||
system.monitor.readLatencyHist::131072-163839 16920 0.51% 97.05% # Read request-response latency
|
||||
system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.56% # Read request-response latency
|
||||
system.monitor.readLatencyHist::196608-229375 17311 0.52% 98.08% # Read request-response latency
|
||||
system.monitor.readLatencyHist::229376-262143 16917 0.51% 98.58% # Read request-response latency
|
||||
system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.10% # Read request-response latency
|
||||
system.monitor.readLatencyHist::294912-327679 12954 0.39% 99.48% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 3182634 95.48% 95.48% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 17049 0.51% 95.99% # Read request-response latency
|
||||
system.monitor.readLatencyHist::98304-131071 18238 0.55% 96.54% # Read request-response latency
|
||||
system.monitor.readLatencyHist::131072-163839 15993 0.48% 97.02% # Read request-response latency
|
||||
system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.53% # Read request-response latency
|
||||
system.monitor.readLatencyHist::196608-229375 18238 0.55% 98.08% # Read request-response latency
|
||||
system.monitor.readLatencyHist::229376-262143 15990 0.48% 98.56% # Read request-response latency
|
||||
system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.07% # Read request-response latency
|
||||
system.monitor.readLatencyHist::294912-327679 13881 0.42% 99.48% # Read request-response latency
|
||||
system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
|
||||
|
|
@ -522,12 +455,12 @@ system.monitor.ittReqReq::min_value 30000 # Re
|
|||
system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time
|
||||
system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time
|
||||
system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::mean 1.270000 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::gmean 1.105133 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::stdev 1.135782 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::mean 1.290000 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::gmean 1.120561 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::stdev 1.139688 # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::1 94 94.00% 94.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::2 0 0.00% 94.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::1 92 92.00% 92.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::2 2 2.00% 94.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions
|
||||
system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions
|
||||
|
|
|
|||
Loading…
Reference in a new issue