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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
Andreas Hansson 8b4b1dcb86 stats: Update stats for DRAM changes 
This patch updates the stats to reflect the changes to the DRAM
controller.
2014-03-23 11:12:19 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.961814 # Number of seconds simulated
sim_ticks 1961813569500 # Number of ticks simulated
final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1769979 # Simulator instruction rate (inst/s)
host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 57024152249 # Simulator tick rate (ticks/s)
host_mem_usage 311592 # Number of bytes of host memory used
host_seconds 34.40 # Real time elapsed on the host
sim_insts 60892925 # Number of instructions simulated
sim_ops 60892925 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory
system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory
system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory
system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory
system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 449018 # Number of read requests accepted
system.physmem.writeReqs 120863 # Number of write requests accepted
system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28166 # Per bank write bursts
system.physmem.perBankRdBursts::1 28350 # Per bank write bursts
system.physmem.perBankRdBursts::2 28054 # Per bank write bursts
system.physmem.perBankRdBursts::3 27500 # Per bank write bursts
system.physmem.perBankRdBursts::4 27615 # Per bank write bursts
system.physmem.perBankRdBursts::5 27605 # Per bank write bursts
system.physmem.perBankRdBursts::6 28127 # Per bank write bursts
system.physmem.perBankRdBursts::7 27851 # Per bank write bursts
system.physmem.perBankRdBursts::8 28176 # Per bank write bursts
system.physmem.perBankRdBursts::9 27723 # Per bank write bursts
system.physmem.perBankRdBursts::10 27750 # Per bank write bursts
system.physmem.perBankRdBursts::11 28018 # Per bank write bursts
system.physmem.perBankRdBursts::12 28330 # Per bank write bursts
system.physmem.perBankRdBursts::13 28694 # Per bank write bursts
system.physmem.perBankRdBursts::14 28891 # Per bank write bursts
system.physmem.perBankRdBursts::15 28050 # Per bank write bursts
system.physmem.perBankWrBursts::0 7929 # Per bank write bursts
system.physmem.perBankWrBursts::1 7797 # Per bank write bursts
system.physmem.perBankWrBursts::2 7545 # Per bank write bursts
system.physmem.perBankWrBursts::3 7029 # Per bank write bursts
system.physmem.perBankWrBursts::4 7135 # Per bank write bursts
system.physmem.perBankWrBursts::5 7129 # Per bank write bursts
system.physmem.perBankWrBursts::6 7643 # Per bank write bursts
system.physmem.perBankWrBursts::7 7252 # Per bank write bursts
system.physmem.perBankWrBursts::8 7395 # Per bank write bursts
system.physmem.perBankWrBursts::9 7084 # Per bank write bursts
system.physmem.perBankWrBursts::10 7104 # Per bank write bursts
system.physmem.perBankWrBursts::11 7401 # Per bank write bursts
system.physmem.perBankWrBursts::12 7833 # Per bank write bursts
system.physmem.perBankWrBursts::13 8315 # Per bank write bursts
system.physmem.perBankWrBursts::14 8551 # Per bank write bursts
system.physmem.perBankWrBursts::15 7701 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
system.physmem.totGap 1961806557500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 449018 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 120863 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1864 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads
system.physmem.totQLat 7845433250 # Total ticks spent queuing
system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers
system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks
system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing
system.physmem.readRowHits 403422 # Number of row buffer hits during reads
system.physmem.writeRowHits 97436 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes
system.physmem.avgGap 3442484.58 # Average gap between requests
system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 18651494 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 292756 # Transaction distribution
system.membus.trans_dist::ReadResp 292756 # Transaction distribution
system.membus.trans_dist::WriteReq 14067 # Transaction distribution
system.membus.trans_dist::WriteResp 14067 # Transaction distribution
system.membus.trans_dist::Writeback 120863 # Transaction distribution
system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution
system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution
system.membus.trans_dist::ReadExReq 164854 # Transaction distribution
system.membus.trans_dist::ReadExResp 164030 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36554338 # Total data (bytes)
system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 342098 # number of replacements
system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use
system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor
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system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy
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system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id
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system.l2c.ReadReq_hits::total 1774887 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 792911 # number of Writeback hits
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system.l2c.overall_mshr_miss_latency::total 22032067517 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373162000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1390781500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2149958500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674822000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2824780500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3523120500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692441500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4215562000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288990 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002269 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.138517 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941327 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766549 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.868012 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956897 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974277 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965610 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474683 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106621 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.415830 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.327813 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.034791 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.173326 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.327813 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.034791 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.173326 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52653.001351 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60892.405063 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53053.913569 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.674797 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.161868 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41694 # number of replacements
system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
system.iocache.tags.data_accesses 375534 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
system.iocache.overall_misses::total 41726 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles
system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 7562587 # DTB read hits
system.cpu0.dtb.read_misses 7765 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 524069 # DTB read accesses
system.cpu0.dtb.write_hits 5147352 # DTB write hits
system.cpu0.dtb.write_misses 910 # DTB write misses
system.cpu0.dtb.write_acv 133 # DTB write access violations
system.cpu0.dtb.write_accesses 202595 # DTB write accesses
system.cpu0.dtb.data_hits 12709939 # DTB hits
system.cpu0.dtb.data_misses 8675 # DTB misses
system.cpu0.dtb.data_acv 343 # DTB access violations
system.cpu0.dtb.data_accesses 726664 # DTB accesses
system.cpu0.itb.fetch_hits 3660806 # ITB hits
system.cpu0.itb.fetch_misses 3984 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
system.cpu0.itb.fetch_accesses 3664790 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 3923627139 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 48127942 # Number of instructions committed
system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses
system.cpu0.num_func_calls 1209779 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls
system.cpu0.num_int_insts 44644072 # number of integer instructions
system.cpu0.num_fp_insts 213646 # number of float instructions
system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read
system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written
system.cpu0.num_mem_refs 12751056 # number of memory refs
system.cpu0.num_load_insts 7590434 # Number of load instructions
system.cpu0.num_store_insts 5160622 # Number of store instructions
system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles
system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles
system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles
system.cpu0.Branches 7246727 # Number of branches fetched
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 234 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed
system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed
system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed
system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 150615 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1371
system.cpu0.kern.mode_good::user 1372
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3108 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.throughput 103965077 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 201613666 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1398487 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
system.iobus.trans_dist::WriteReq 55619 # Transaction distribution
system.iobus.trans_dist::WriteResp 55619 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2743570 # Total data (bytes)
system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 703274 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 48840865 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 47433057 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 47433057 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 47433057 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 47433057 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 47433057 # number of overall hits
system.cpu0.icache.overall_hits::total 47433057 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 703904 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 703904 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 703904 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 703904 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 703904 # number of overall misses
system.cpu0.icache.overall_misses::total 703904 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10025783755 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 10025783755 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 10025783755 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 10025783755 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 10025783755 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 10025783755 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136961 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 48136961 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 48136961 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 48136961 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 48136961 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 48136961 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014623 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014623 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014623 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014623 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014623 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014623 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14243.112349 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14243.112349 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703904 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 703904 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 703904 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 703904 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 703904 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 703904 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8612997245 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8612997245 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8612997245 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 8612997245 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8612997245 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 8612997245 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014623 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014623 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014623 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1191290 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.228160 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11513399 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1191802 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.660496 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 108508250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.228160 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986774 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.986774 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 52084916 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 52084916 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6477391 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6477391 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4731575 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4731575 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141550 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 141550 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149263 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 149263 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11208966 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11208966 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11208966 # number of overall hits
system.cpu0.dcache.overall_hits::total 11208966 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 942691 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 942691 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 258024 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 258024 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13717 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13717 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1200715 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1200715 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1200715 # number of overall misses
system.cpu0.dcache.overall_misses::total 1200715 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27259981257 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 27259981257 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10282729939 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10282729939 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150891500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 150891500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41989388 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 41989388 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 37542711196 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 37542711196 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 37542711196 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 37542711196 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420082 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7420082 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989599 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4989599 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155267 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 155267 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154715 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 154715 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12409681 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12409681 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12409681 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12409681 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127046 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.127046 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051712 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.051712 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088345 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088345 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks
system.cpu0.dcache.writebacks::total 686471 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942691 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 942691 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258024 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 258024 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13717 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13717 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200715 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1200715 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200715 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1200715 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25249299743 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25249299743 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9714288061 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9714288061 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 123443500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 123443500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31083612 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31083612 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34963587804 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 34963587804 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34963587804 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 34963587804 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2280051500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2280051500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3745653500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3745653500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127046 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127046 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051712 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051712 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088345 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088345 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035239 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035239 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.096756 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.096756 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8999.307429 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8999.307429 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5701.322817 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5701.322817 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 2348422 # DTB read hits
system.cpu1.dtb.read_misses 2620 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 205337 # DTB read accesses
system.cpu1.dtb.write_hits 1677006 # DTB write hits
system.cpu1.dtb.write_misses 235 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 89739 # DTB write accesses
system.cpu1.dtb.data_hits 4025428 # DTB hits
system.cpu1.dtb.data_misses 2855 # DTB misses
system.cpu1.dtb.data_acv 24 # DTB access violations
system.cpu1.dtb.data_accesses 295076 # DTB accesses
system.cpu1.itb.fetch_hits 1801062 # ITB hits
system.cpu1.itb.fetch_misses 1064 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_accesses 1802126 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 3921881188 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 12764983 # Number of instructions committed
system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses
system.cpu1.num_func_calls 404056 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls
system.cpu1.num_int_insts 11763372 # number of integer instructions
system.cpu1.num_fp_insts 170364 # number of float instructions
system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read
system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written
system.cpu1.num_mem_refs 4047975 # number of memory refs
system.cpu1.num_load_insts 2361944 # Number of load instructions
system.cpu1.num_store_insts 1686031 # Number of store instructions
system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles
system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles
system.cpu1.Branches 1821589 # Number of branches fetched
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 92 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed
system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed
system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed
system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed
system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 70661 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches
system.cpu1.kern.mode_switch::user 368 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 798
system.cpu1.kern.mode_good::user 368
system.cpu1.kern.mode_good::idle 430
system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1956 # number of times the context was actually changed
system.cpu1.icache.tags.replacements 311472 # number of replacements
system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits
system.cpu1.icache.overall_hits::total 12455839 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses
system.cpu1.icache.overall_misses::total 312023 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 155135 # number of replacements
system.cpu1.dcache.tags.tagsinuse 486.308895 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 3855441 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 155464 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 24.799574 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 1048852146500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308895 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949822 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.949822 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 16322717 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 16322717 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 2189668 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2189668 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1567568 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1567568 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46969 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 46969 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49480 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 49480 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3757236 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3757236 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3757236 # number of overall hits
system.cpu1.dcache.overall_hits::total 3757236 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 113735 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 113735 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 55930 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 55930 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8863 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 8863 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5883 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 5883 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 169665 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 169665 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 169665 # number of overall misses
system.cpu1.dcache.overall_misses::total 169665 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1371834000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 1371834000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1009197248 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 1009197248 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80472000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 80472000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43306909 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 43306909 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 2381031248 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 2381031248 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 2381031248 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 2381031248 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303403 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2303403 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623498 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1623498 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55832 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 55832 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55363 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 55363 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3926901 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3926901 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3926901 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3926901 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049377 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.049377 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034450 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.034450 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158744 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158744 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106262 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106262 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043206 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.043206 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043206 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.043206 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9079.544172 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9079.544172 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.364780 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.364780 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks
system.cpu1.dcache.writebacks::total 106440 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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