1059 lines
121 KiB
Plaintext
1059 lines
121 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.530994 # Number of seconds simulated
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sim_ticks 530994193500 # Number of ticks simulated
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final_tick 530994193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 125227 # Simulator instruction rate (inst/s)
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host_op_rate 139700 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 43051016 # Simulator tick rate (ticks/s)
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host_mem_usage 313040 # Number of bytes of host memory used
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host_seconds 12334.07 # Real time elapsed on the host
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sim_insts 1544563023 # Number of instructions simulated
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sim_ops 1723073835 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 47488 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 143709888 # Number of bytes read from this memory
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system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 47488 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 47488 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 70419456 # Number of bytes written to this memory
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system.physmem.bytes_written::total 70419456 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 742 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2245467 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1100304 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1100304 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 89432 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 270643050 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 270732482 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 89432 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 89432 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 132618128 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 132618128 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 132618128 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 89432 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 270643050 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 403350610 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 2246209 # Number of read requests accepted
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system.physmem.writeReqs 1100304 # Number of write requests accepted
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system.physmem.readBursts 2246209 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1100304 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 143663936 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 93440 # Total number of bytes read from write queue
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system.physmem.bytesWritten 70418368 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 143757376 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 70419456 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1460 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 139551 # Per bank write bursts
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system.physmem.perBankRdBursts::1 136202 # Per bank write bursts
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system.physmem.perBankRdBursts::2 133682 # Per bank write bursts
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system.physmem.perBankRdBursts::3 136207 # Per bank write bursts
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system.physmem.perBankRdBursts::4 134706 # Per bank write bursts
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system.physmem.perBankRdBursts::5 135350 # Per bank write bursts
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system.physmem.perBankRdBursts::6 136147 # Per bank write bursts
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system.physmem.perBankRdBursts::7 135992 # Per bank write bursts
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system.physmem.perBankRdBursts::8 143786 # Per bank write bursts
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system.physmem.perBankRdBursts::9 146457 # Per bank write bursts
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system.physmem.perBankRdBursts::10 144536 # Per bank write bursts
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system.physmem.perBankRdBursts::11 146082 # Per bank write bursts
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system.physmem.perBankRdBursts::12 145807 # Per bank write bursts
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system.physmem.perBankRdBursts::13 145943 # Per bank write bursts
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system.physmem.perBankRdBursts::14 141988 # Per bank write bursts
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system.physmem.perBankRdBursts::15 142313 # Per bank write bursts
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system.physmem.perBankWrBursts::0 69095 # Per bank write bursts
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system.physmem.perBankWrBursts::1 67437 # Per bank write bursts
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system.physmem.perBankWrBursts::2 65633 # Per bank write bursts
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system.physmem.perBankWrBursts::3 66265 # Per bank write bursts
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system.physmem.perBankWrBursts::4 66084 # Per bank write bursts
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system.physmem.perBankWrBursts::5 66429 # Per bank write bursts
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system.physmem.perBankWrBursts::6 67953 # Per bank write bursts
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system.physmem.perBankWrBursts::7 68751 # Per bank write bursts
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system.physmem.perBankWrBursts::8 70388 # Per bank write bursts
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system.physmem.perBankWrBursts::9 70973 # Per bank write bursts
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system.physmem.perBankWrBursts::10 70609 # Per bank write bursts
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system.physmem.perBankWrBursts::11 70934 # Per bank write bursts
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system.physmem.perBankWrBursts::12 70330 # Per bank write bursts
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system.physmem.perBankWrBursts::13 70711 # Per bank write bursts
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system.physmem.perBankWrBursts::14 69591 # Per bank write bursts
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system.physmem.perBankWrBursts::15 69104 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 530994124500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 2246209 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1100304 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1619262 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 446010 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 134777 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 44683 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 17958 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 19185 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 29573 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 48522 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 58770 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 63067 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 64531 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 65202 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 65713 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 66239 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 70263 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 71854 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 72330 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 80202 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 72456 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 68391 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 66809 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 65859 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 22753 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 6508 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1933 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 609 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 277 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 70 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 70 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1604351 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 105.964762 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 82.430314 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 134.227606 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1240784 77.34% 77.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 261404 16.29% 93.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 44793 2.79% 96.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 17157 1.07% 97.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 10128 0.63% 98.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 4810 0.30% 98.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 3056 0.19% 98.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 2546 0.16% 98.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 19673 1.23% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1604351 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 64945 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 34.562861 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 155.173168 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 64902 99.93% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 64945 # Reads before turning the bus around for writes
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|
system.physmem.wrPerTurnAround::samples 64945 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.941828 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.872806 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.740981 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 45649 70.29% 70.29% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 15339 23.62% 93.91% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-21 3628 5.59% 99.49% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::22-23 219 0.34% 99.83% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::24-25 37 0.06% 99.89% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::26-27 12 0.02% 99.91% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::28-29 13 0.02% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30-31 7 0.01% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-37 2 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::38-39 4 0.01% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-41 17 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::42-43 3 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-45 2 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-53 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::54-55 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-57 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::66-67 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-69 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-77 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-81 2 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::82-83 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::90-91 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 64945 # Writes before turning the bus around for reads
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|
system.physmem.totQLat 28406230500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 98095071750 # Total ticks spent from burst creation until serviced by the DRAM
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|
system.physmem.totBusLat 11223745000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 58465096250 # Total ticks spent accessing banks
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system.physmem.avgQLat 12654.52 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 26045.27 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 43699.80 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 270.56 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 132.62 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 270.73 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 132.62 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.15 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.38 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 908698 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 419053 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 40.48 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 38.09 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 158670.87 # Average gap between requests
|
|
system.physmem.pageHitRate 39.69 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 6.04 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.membus.throughput 403350610 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 1419771 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1419771 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1100304 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 826438 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 826438 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5592722 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 5592722 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214176832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 214176832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 214176832 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 12918660500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 21056537500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 4.0 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 303422540 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 249650550 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15218950 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 174790549 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 161666933 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 92.491805 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 17552768 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 208 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
|
system.cpu.numCycles 1061988388 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 298972523 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 2188716520 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 303422540 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 179219701 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 435616214 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 87982008 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 163592873 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.CacheLines 289402821 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 5967581 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 968083151 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.501232 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.206704 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 532467013 55.00% 55.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 25400980 2.62% 57.63% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 39071584 4.04% 61.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 48282365 4.99% 66.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 43747142 4.52% 71.17% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 46387901 4.79% 75.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 38401401 3.97% 79.93% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 18925667 1.95% 81.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 175399098 18.12% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 968083151 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.285712 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.060961 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 331186258 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 141449476 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 405224090 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 20322579 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 69900748 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 46031045 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 725 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 2368410495 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2465 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 69900748 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 354622933 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 70003752 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 18690 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 400463677 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 73073351 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 2305921736 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 149865 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 5017686 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 60142463 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 2281817078 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 10647699630 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 9761875654 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 372 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 575497148 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 824 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 821 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 160915749 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 624658588 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 220783882 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 86055084 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 71680407 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2202175358 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 849 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2018579412 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 4016690 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 474511400 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1127247409 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 968083151 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.085130 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.905910 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 285219249 29.46% 29.46% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 153603913 15.87% 45.33% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 160908478 16.62% 61.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 120369215 12.43% 74.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 123515877 12.76% 87.14% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 73725483 7.62% 94.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 38349194 3.96% 98.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 9869125 1.02% 99.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2522617 0.26% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 968083151 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 891948 3.74% 3.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 5659 0.02% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 18285123 76.74% 80.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4644794 19.49% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1236892590 61.28% 61.28% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 924644 0.05% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 35 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 587766580 29.12% 90.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 192995535 9.56% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2018579412 # Type of FU issued
|
|
system.cpu.iq.rate 1.900755 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 23827524 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.011804 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5033085915 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2676877502 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1957286875 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 274 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2042406797 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 64607409 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 138731819 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 269264 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 192926 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 45936837 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4636852 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 69900748 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 32985264 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1607893 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2202176322 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 7875030 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 624658588 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 220783882 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 787 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 480489 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 97297 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 192926 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 8154150 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 9614096 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 17768246 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1987907812 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 573917969 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 30671600 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 115 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 764035004 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 238344765 # Number of branches executed
|
|
system.cpu.iew.exec_stores 190117035 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.871873 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1965721385 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1957286989 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1295353169 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2059124619 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.843040 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.629080 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 479201419 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 15218256 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 898182403 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.918401 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.718632 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 409520932 45.59% 45.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 193341126 21.53% 67.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 72856392 8.11% 75.23% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 35266381 3.93% 79.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 18923261 2.11% 81.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 30757515 3.42% 84.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19970325 2.22% 86.91% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 11453537 1.28% 88.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106092934 11.81% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 898182403 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 660773814 # Number of memory references committed
|
|
system.cpu.commit.loads 485926769 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462426 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 106092934 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 2994364142 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4474601624 # The number of ROB writes
|
|
system.cpu.timesIdled 1160522 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 93905237 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.687566 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.687566 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.454407 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.454407 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 9955508978 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1937309574 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 108 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 108 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 737568033 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1613255878 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7708873 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7708872 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 3782409 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1893555 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1893555 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22985720 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22987269 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856579904 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 856629440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 856629440 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10474986844 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1289999 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14746367742 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 17 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 631.201883 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 289401615 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 772 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 374872.558290 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 631.201883 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.308204 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.308204 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 755 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 729 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.368652 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 578806417 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 578806417 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 289401622 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 289401622 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 289401622 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 289401622 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 289401622 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 289401622 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1199 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1199 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1199 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1199 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1199 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1199 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 84823499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 84823499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 84823499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 84823499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 84823499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 84823499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 289402821 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 289402821 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 289402821 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 289402821 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 289402821 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 289402821 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70745.203503 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 70745.203503 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70745.203503 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 70745.203503 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70745.203503 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 70745.203503 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 424 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 424 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 424 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 424 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56494501 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 56494501 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56494501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 56494501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56494501 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 56494501 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72896.130323 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72896.130323 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72896.130323 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 72896.130323 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72896.130323 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 72896.130323 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 2213521 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31530.649727 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 9247246 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 2243295 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.122171 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 21629133000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14295.824986 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.209231 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 17214.615510 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.436274 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000617 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.525348 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.962239 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23754 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3955 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 111215565 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 111215565 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 31 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6289061 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6289092 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3782409 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3782409 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1067117 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1067117 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 31 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7356178 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7356209 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 31 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7356178 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7356209 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 743 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1419037 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1419780 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 826438 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 826438 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 743 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2245475 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 2246218 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 743 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2245475 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 2246218 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55398500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 122091721000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 122147119500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 73834470750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 73834470750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 55398500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 195926191750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 195981590250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 55398500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 195926191750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 195981590250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7708098 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7708872 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3782409 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3782409 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893555 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1893555 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9601653 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9602427 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9601653 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9602427 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.959948 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184097 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.184175 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436448 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436448 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.959948 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233863 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.233922 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.959948 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233863 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.233922 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74560.565276 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86038.433811 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 86032.427207 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89340.604800 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89340.604800 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74560.565276 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87253.784500 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 87249.585859 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74560.565276 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87253.784500 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 87249.585859 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1100304 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1100304 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 742 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419029 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1419771 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826438 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 826438 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 742 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2245467 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 2246209 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 742 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2245467 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 2246209 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45997000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 104316352250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 104362349250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63474835750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63474835750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45997000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 167791188000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 167837185000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45997000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 167791188000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 167837185000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184096 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184174 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436448 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436448 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233863 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.233921 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233863 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.233921 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61990.566038 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73512.487941 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73506.466360 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76805.320847 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76805.320847 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61990.566038 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74724.406103 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74720.199679 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61990.566038 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74724.406103 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74720.199679 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 9597556 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4088.017894 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 656035033 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9601652 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 68.325225 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 3543401250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.017894 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.998051 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.998051 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 619 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2366 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1110 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1355956994 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1355956994 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 489079777 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 489079777 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 166955126 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 166955126 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 656034903 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 656034903 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 656034903 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 656034903 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 11511719 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 11511719 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5630921 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5630921 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 17142640 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 17142640 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 17142640 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 17142640 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 356637028987 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 356637028987 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 299385068793 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 299385068793 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 231500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 656022097780 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 656022097780 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 656022097780 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 656022097780 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 500591496 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 500591496 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 673177543 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 673177543 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 673177543 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 673177543 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022996 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022996 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032627 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032627 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025465 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.025465 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025465 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.025465 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30980.345245 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 30980.345245 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53168.046363 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 53168.046363 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77166.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77166.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38268.440437 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 38268.440437 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38268.440437 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 38268.440437 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 23433940 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 3966170 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1210564 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.357870 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 60.894338 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3782409 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3782409 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3803620 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 3803620 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3737364 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3737364 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7540984 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7540984 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7540984 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7540984 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708099 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7708099 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893557 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1893557 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9601656 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9601656 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9601656 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9601656 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194575797258 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 194575797258 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86895396246 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86895396246 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 281471193504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 281471193504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 281471193504 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 281471193504 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015398 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015398 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25243.032978 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25243.032978 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45890.034599 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45890.034599 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29314.859177 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29314.859177 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29314.859177 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29314.859177 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|