x86, regressions: updates stats
This is due to op class, function call, walker patches.
This commit is contained in:
Nilay Vaish
parent
22b60c57e6
commit
af2e83c7f1
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@ -4,13 +4,13 @@ sim_seconds 5.205149 # Nu
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sim_ticks 5205148879000 # Number of ticks simulated
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final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 134092 # Simulator instruction rate (inst/s)
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host_op_rate 257066 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6543163557 # Simulator tick rate (ticks/s)
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host_inst_rate 131600 # Simulator instruction rate (inst/s)
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host_op_rate 252290 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6421585329 # Simulator tick rate (ticks/s)
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host_mem_usage 872300 # Number of bytes of host memory used
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host_seconds 795.51 # Real time elapsed on the host
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host_seconds 810.57 # Real time elapsed on the host
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sim_insts 106671342 # Number of instructions simulated
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sim_ops 204498755 # Number of ops (including micro ops) simulated
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sim_ops 204498751 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory
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@ -264,10 +264,10 @@ system.cpu0.numCycles 10410297758 # nu
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 60288276 # Number of instructions committed
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system.cpu0.committedOps 115773081 # Number of ops (including micro ops) committed
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system.cpu0.committedOps 115773079 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu0.num_func_calls 0 # number of times a function call or return occured
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system.cpu0.num_func_calls 1065656 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 108731496 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
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@ -288,10 +288,10 @@ system.cpu1.numCycles 10407399002 # nu
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu1.committedInsts 46383066 # Number of instructions committed
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system.cpu1.committedOps 88725674 # Number of ops (including micro ops) committed
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system.cpu1.committedOps 88725672 # Number of ops (including micro ops) committed
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system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu1.num_func_calls 0 # number of times a function call or return occured
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system.cpu1.num_func_calls 1670749 # number of times a function call or return occured
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system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls
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system.cpu1.num_int_insts 85218419 # number of integer instructions
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system.cpu1.num_fp_insts 0 # number of float instructions
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu
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sim_ticks 963992672000 # Number of ticks simulated
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final_tick 963992672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 595979 # Simulator instruction rate (inst/s)
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host_op_rate 1098124 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 652844357 # Simulator tick rate (ticks/s)
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host_mem_usage 283988 # Number of bytes of host memory used
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host_seconds 1476.60 # Real time elapsed on the host
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host_inst_rate 988845 # Simulator instruction rate (inst/s)
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host_op_rate 1822001 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1083195788 # Simulator tick rate (ticks/s)
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host_mem_usage 286888 # Number of bytes of host memory used
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host_seconds 889.95 # Real time elapsed on the host
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sim_insts 880025278 # Number of instructions simulated
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sim_ops 1621493928 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
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@ -41,7 +41,7 @@ system.cpu.committedInsts 880025278 # Nu
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system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 2123381 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1621354440 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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@ -4,11 +4,11 @@ sim_seconds 1.800193 # Nu
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sim_ticks 1800193398000 # Number of ticks simulated
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final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 392596 # Simulator instruction rate (inst/s)
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host_op_rate 723379 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 803099848 # Simulator tick rate (ticks/s)
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host_mem_usage 292568 # Number of bytes of host memory used
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host_seconds 2241.56 # Real time elapsed on the host
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host_inst_rate 510604 # Simulator instruction rate (inst/s)
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host_op_rate 940816 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1044499940 # Simulator tick rate (ticks/s)
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host_mem_usage 295340 # Number of bytes of host memory used
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host_seconds 1723.50 # Real time elapsed on the host
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sim_insts 880025278 # Number of instructions simulated
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sim_ops 1621493928 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
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@ -42,7 +42,7 @@ system.cpu.committedInsts 880025278 # Nu
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system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 2123381 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1621354440 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
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sim_ticks 168950040000 # Number of ticks simulated
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final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 540700 # Simulator instruction rate (inst/s)
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host_op_rate 952086 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 578214744 # Simulator tick rate (ticks/s)
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host_mem_usage 420252 # Number of bytes of host memory used
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host_seconds 292.19 # Real time elapsed on the host
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host_inst_rate 992711 # Simulator instruction rate (inst/s)
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host_op_rate 1748005 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1061587108 # Simulator tick rate (ticks/s)
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host_mem_usage 424044 # Number of bytes of host memory used
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host_seconds 159.15 # Real time elapsed on the host
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sim_insts 157988548 # Number of instructions simulated
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sim_ops 278192465 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
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@ -41,7 +41,7 @@ system.cpu.committedInsts 157988548 # Nu
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system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 8475189 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
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system.cpu.num_int_insts 278186175 # number of integer instructions
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system.cpu.num_fp_insts 40 # number of float instructions
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@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
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sim_ticks 365989065000 # Number of ticks simulated
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final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 284823 # Simulator instruction rate (inst/s)
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host_op_rate 501527 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 659807143 # Simulator tick rate (ticks/s)
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host_mem_usage 428704 # Number of bytes of host memory used
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host_seconds 554.69 # Real time elapsed on the host
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host_inst_rate 466388 # Simulator instruction rate (inst/s)
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host_op_rate 821234 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1080412484 # Simulator tick rate (ticks/s)
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host_mem_usage 431468 # Number of bytes of host memory used
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host_seconds 338.75 # Real time elapsed on the host
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sim_insts 157988548 # Number of instructions simulated
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sim_ops 278192465 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
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@ -42,7 +42,7 @@ system.cpu.committedInsts 157988548 # Nu
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system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 8475189 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
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system.cpu.num_int_insts 278186175 # number of integer instructions
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system.cpu.num_fp_insts 40 # number of float instructions
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File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu
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sim_ticks 885229328000 # Number of ticks simulated
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final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 607816 # Simulator instruction rate (inst/s)
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host_op_rate 1123920 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 650709398 # Simulator tick rate (ticks/s)
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host_mem_usage 293412 # Number of bytes of host memory used
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host_seconds 1360.41 # Real time elapsed on the host
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host_inst_rate 1006678 # Simulator instruction rate (inst/s)
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host_op_rate 1861461 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1077718973 # Simulator tick rate (ticks/s)
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host_mem_usage 296180 # Number of bytes of host memory used
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host_seconds 821.39 # Real time elapsed on the host
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sim_insts 826877110 # Number of instructions simulated
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sim_ops 1528988702 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
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@ -41,7 +41,7 @@ system.cpu.committedInsts 826877110 # Nu
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system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 35346287 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1528317562 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
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sim_ticks 1647872849000 # Number of ticks simulated
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final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 379189 # Simulator instruction rate (inst/s)
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host_op_rate 701163 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 755680972 # Simulator tick rate (ticks/s)
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host_mem_usage 300836 # Number of bytes of host memory used
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host_seconds 2180.65 # Real time elapsed on the host
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host_inst_rate 533286 # Simulator instruction rate (inst/s)
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host_op_rate 986105 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1062778196 # Simulator tick rate (ticks/s)
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host_mem_usage 304632 # Number of bytes of host memory used
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host_seconds 1550.53 # Real time elapsed on the host
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sim_insts 826877110 # Number of instructions simulated
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sim_ops 1528988702 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
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@ -42,7 +42,7 @@ system.cpu.committedInsts 826877110 # Nu
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system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 35346287 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1528317562 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
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sim_ticks 2846007227500 # Number of ticks simulated
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final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 922936 # Simulator instruction rate (inst/s)
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host_op_rate 1438019 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 873209138 # Simulator tick rate (ticks/s)
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host_mem_usage 283960 # Number of bytes of host memory used
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host_seconds 3259.25 # Real time elapsed on the host
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host_inst_rate 1114602 # Simulator instruction rate (inst/s)
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host_op_rate 1736651 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1054547884 # Simulator tick rate (ticks/s)
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host_mem_usage 286860 # Number of bytes of host memory used
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host_seconds 2698.79 # Real time elapsed on the host
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sim_insts 3008081022 # Number of instructions simulated
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sim_ops 4686862596 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
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@ -41,7 +41,7 @@ system.cpu.committedInsts 3008081022 # Nu
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system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 33534539 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4686862527 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
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sim_ticks 5882580526000 # Number of ticks simulated
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final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 579739 # Simulator instruction rate (inst/s)
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host_op_rate 903286 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1133733281 # Simulator tick rate (ticks/s)
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host_mem_usage 291512 # Number of bytes of host memory used
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host_seconds 5188.68 # Real time elapsed on the host
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host_inst_rate 548624 # Simulator instruction rate (inst/s)
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host_op_rate 854806 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1072884756 # Simulator tick rate (ticks/s)
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host_mem_usage 295308 # Number of bytes of host memory used
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host_seconds 5482.96 # Real time elapsed on the host
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sim_insts 3008081022 # Number of instructions simulated
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sim_ops 4686862596 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
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@ -42,7 +42,7 @@ system.cpu.committedInsts 3008081022 # Nu
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system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_func_calls 33534539 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4686862527 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
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sim_ticks 131393068000 # Number of ticks simulated
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final_tick 131393068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 538543 # Simulator instruction rate (inst/s)
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host_op_rate 902645 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 535777601 # Simulator tick rate (ticks/s)
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host_mem_usage 308992 # Number of bytes of host memory used
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host_seconds 245.24 # Real time elapsed on the host
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host_inst_rate 929815 # Simulator instruction rate (inst/s)
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host_op_rate 1558452 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 925040607 # Simulator tick rate (ticks/s)
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host_mem_usage 311764 # Number of bytes of host memory used
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host_seconds 142.04 # Real time elapsed on the host
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sim_insts 132071193 # Number of instructions simulated
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sim_ops 221362963 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
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@ -41,7 +41,7 @@ system.cpu.committedInsts 132071193 # Nu
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system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 220339554 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
|
|||
sim_ticks 250953957000 # Number of ticks simulated
|
||||
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 308460 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 517006 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 586117013 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316420 # Number of bytes of host memory used
|
||||
host_seconds 428.16 # Real time elapsed on the host
|
||||
host_inst_rate 507243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 850184 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 963833485 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 320216 # Number of bytes of host memory used
|
||||
host_seconds 260.37 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221362963 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
|
||||
|
|
@ -35,7 +35,7 @@ system.cpu.committedInsts 132071193 # Nu
|
|||
system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 220339554 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112100 # Number of seconds simulated
|
||||
sim_ticks 5112099861500 # Number of ticks simulated
|
||||
final_tick 5112099861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 5112099860500 # Number of ticks simulated
|
||||
final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1058684 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2167614 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27073251373 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 628224 # Number of bytes of host memory used
|
||||
host_seconds 188.82 # Real time elapsed on the host
|
||||
host_inst_rate 1019592 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2087576 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26073588986 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 631672 # Number of bytes of host memory used
|
||||
host_seconds 196.06 # Real time elapsed on the host
|
||||
sim_insts 199905607 # Number of instructions simulated
|
||||
sim_ops 409299164 # Number of ops (including micro ops) simulated
|
||||
sim_ops 409299132 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
|
|
@ -194,7 +194,7 @@ system.iocache.tagsinuse 0.042441 # Cy
|
|||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 4994822604059 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
|
|
@ -245,57 +245,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10224199746 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224199744 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199905607 # Number of instructions committed
|
||||
system.cpu.committedOps 409299164 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374462077 # Number of integer alu accesses
|
||||
system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374462047 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39972120 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374462077 # number of integer instructions
|
||||
system.cpu.num_func_calls 2307315 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374462047 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 915890450 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480542967 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 915890300 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480542889 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 35654170 # number of memory refs
|
||||
system.cpu.num_load_insts 27234345 # Number of load instructions
|
||||
system.cpu.num_store_insts 8419825 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770518373.401503 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453681372.598497 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955627 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790584 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243492011 # Total number of references to valid blocks.
|
||||
system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 307.790725 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148824779500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243492011 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243492011 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243492011 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243492011 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243492011 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243492011 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243492014 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791103 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244283114 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244283114 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244283114 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244283114 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244283114 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244283114 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
|
||||
|
|
@ -316,7 +316,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cy
|
|||
system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102064746500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy
|
||||
|
|
@ -364,7 +364,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cy
|
|||
system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5100425402500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy
|
||||
|
|
@ -408,22 +408,22 @@ system.cpu.dcache.tagsinuse 511.999425 # Cy
|
|||
system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7550500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12073184 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12073184 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8093253 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8093253 # number of WriteReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12073185 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12073185 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8093252 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8093252 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20166437 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308370 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308370 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316386 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316386 # number of WriteReq misses
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308369 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308369 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316387 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316387 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses
|
||||
|
|
@ -456,16 +456,16 @@ system.cpu.dcache.writebacks::writebacks 1535700 # nu
|
|||
system.cpu.dcache.writebacks::total 1535700 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 105930 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64819.953894 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456507 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.325460 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.325454 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 51906.788142 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 51906.788145 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2490.593014 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10422.435538 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10422.435543 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
|
|
@ -475,14 +475,14 @@ system.cpu.l2cache.occ_percent::total 0.989074 # Av
|
|||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275492 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062560 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275491 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062559 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179720 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179720 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179721 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179721 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits
|
||||
|
|
@ -515,14 +515,14 @@ system.cpu.l2cache.overall_misses::total 179971 # nu
|
|||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307738 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108138 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307737 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108137 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314113 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314113 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314114 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314114 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses
|
||||
|
|
@ -540,8 +540,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658
|
|||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427849 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427849 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427848 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427848 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ sim_seconds 5.187336 # Nu
|
|||
sim_ticks 5187335906000 # Number of ticks simulated
|
||||
final_tick 5187335906000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 632480 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1219228 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25568906299 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 629256 # Number of bytes of host memory used
|
||||
host_seconds 202.88 # Real time elapsed on the host
|
||||
host_inst_rate 633010 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1220249 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25590316667 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 632708 # Number of bytes of host memory used
|
||||
host_seconds 202.71 # Real time elapsed on the host
|
||||
sim_insts 128315489 # Number of instructions simulated
|
||||
sim_ops 247353050 # Number of ops (including micro ops) simulated
|
||||
sim_ops 247353048 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2850304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory
|
||||
|
|
@ -293,10 +293,10 @@ system.cpu.numCycles 10374671812 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 128315489 # Number of instructions committed
|
||||
system.cpu.committedOps 247353050 # Number of ops (including micro ops) committed
|
||||
system.cpu.committedOps 247353048 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 232087369 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 2299349 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 23166071 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 232087369 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu
|
|||
sim_ticks 5615000 # Number of ticks simulated
|
||||
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 54091 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 97967 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56419373 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276792 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 70800 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 128226 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 73842503 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280580 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
|
||||
|
|
@ -41,7 +41,7 @@ system.cpu.committedInsts 5381 # Nu
|
|||
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 209 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9655 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu
|
|||
sim_ticks 121759 # Number of ticks simulated
|
||||
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 7080 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12826 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 160202 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 32232 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58383 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 729156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 170120 # Number of bytes of host memory used
|
||||
host_seconds 0.76 # Real time elapsed on the host
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
|
||||
|
|
@ -22,7 +22,7 @@ system.cpu.committedInsts 5381 # Nu
|
|||
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 209 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9655 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 28358000 # Number of ticks simulated
|
||||
final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 48918 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 88604 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 257715326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 285372 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 90736 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 477859669 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289160 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
|
||||
|
|
@ -35,7 +35,7 @@ system.cpu.committedInsts 5381 # Nu
|
|||
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 209 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9655 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
|
|
|
|||
Loading…
Reference in a new issue