779 lines
89 KiB
Text
779 lines
89 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.064955 # Number of seconds simulated
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sim_ticks 64955437500 # Number of ticks simulated
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final_tick 64955437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 70718 # Simulator instruction rate (inst/s)
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host_op_rate 124523 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 29075113 # Simulator tick rate (ticks/s)
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host_mem_usage 434544 # Number of bytes of host memory used
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host_seconds 2234.06 # Real time elapsed on the host
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sim_insts 157988547 # Number of instructions simulated
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sim_ops 278192464 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1946560 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory
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system.physmem.bytes_written::total 10432 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 30415 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 163 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 986276 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 28981346 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 29967622 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 986276 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 986276 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 160602 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 160602 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 160602 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 986276 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 28981346 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 30128224 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 30415 # Total number of read requests seen
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system.physmem.writeReqs 163 # Total number of write requests seen
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system.physmem.cpureqs 30578 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1946560 # Total number of bytes read from memory
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system.physmem.bytesWritten 10432 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1946560 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 40 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1903 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 1919 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1928 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1935 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1899 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 1949 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 1933 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1946 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 1848 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 1827 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 63 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 11 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 7 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 64955401000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 30415 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 163 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 29875 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 392 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 11278750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 610070000 # Sum of mem lat for all requests
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system.physmem.totBusLat 151875000 # Total cycles spent in databus access
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system.physmem.totBankLat 446916250 # Total cycles spent in bank access
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system.physmem.avgQLat 371.32 # Average queueing delay per request
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system.physmem.avgBankLat 14713.29 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 20084.61 # Average memory access latency
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system.physmem.avgRdBW 29.97 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 29.97 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.24 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 9.38 # Average write queue length over time
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system.physmem.readRowHits 29086 # Number of row buffer hits during reads
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system.physmem.writeRowHits 90 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 95.76 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 55.21 # Row buffer hit rate for writes
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system.physmem.avgGap 2124252.76 # Average gap between requests
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system.cpu.branchPred.lookups 33861369 # Number of BP lookups
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system.cpu.branchPred.condPredicted 33861369 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 775033 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 19294803 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 19205281 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 99.536031 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 5016068 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 5449 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 444 # Number of system calls
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system.cpu.numCycles 129910880 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 26135643 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 182272269 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 33861369 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 24221349 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 55463274 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 5355481 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 43685508 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 275 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 25577909 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 166501 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 129829944 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.475075 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.321063 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 76844002 59.19% 59.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1961117 1.51% 60.70% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2942078 2.27% 62.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 3835155 2.95% 65.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 7767567 5.98% 71.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4757667 3.66% 75.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 2666355 2.05% 77.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1316617 1.01% 78.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 27739386 21.37% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 129829944 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.260651 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.403056 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 36820018 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 35912600 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 43886713 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 8665410 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 4545203 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 318850210 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 4545203 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 42299380 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 8565943 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 6540 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 46769687 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 27643191 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 315014600 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 37506 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 25780031 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 461 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 317193496 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 836529852 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 836528510 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1342 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 37980749 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 473 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 470 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 62475342 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 101554999 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 34779465 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 39658435 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 5856370 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 311474506 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 1648 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 300268759 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 90582 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 32704656 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 46105854 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 1203 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 129829944 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.312785 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.693578 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 23157142 17.84% 17.84% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 23146978 17.83% 35.67% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 25463277 19.61% 55.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 25807307 19.88% 75.16% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 18888431 14.55% 89.70% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 8277018 6.38% 96.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 3970528 3.06% 99.14% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 942780 0.73% 99.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 176483 0.14% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 129829944 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 31372 1.52% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 1915002 93.02% 94.54% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 112311 5.46% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 169830588 56.56% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 11175 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 97304104 32.41% 88.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 33091251 11.02% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 300268759 # Type of FU issued
|
|
system.cpu.iq.rate 2.311344 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2058685 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 732516269 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 344212556 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 298017233 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 646 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 145 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 302295951 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 54147980 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 10775614 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 30228 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 33222 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 3339713 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3234 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 8606 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 4545203 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1761176 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 160180 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 311476154 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 195955 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 101554999 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 34779465 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3219 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 73682 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 33222 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 393210 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 428039 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 821249 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 298868187 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 96891593 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1400572 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 129818447 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 30819793 # Number of branches executed
|
|
system.cpu.iew.exec_stores 32926854 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.300563 # Inst execution rate
|
|
system.cpu.iew.wb_sent 298386144 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 298017378 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 218312526 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 296857185 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.294014 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.735413 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 33296720 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 775062 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 125284741 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.220482 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.978635 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 57056182 45.54% 45.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 19092863 15.24% 60.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 11627505 9.28% 70.06% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 9458661 7.55% 77.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1851635 1.48% 79.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 2083324 1.66% 80.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1287468 1.03% 81.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 696184 0.56% 82.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 22130919 17.66% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 125284741 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
|
|
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 122219137 # Number of memory references committed
|
|
system.cpu.commit.loads 90779385 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 29309705 # Number of branches committed
|
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 278186174 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 4237596 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 22130919 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 414643006 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 627527392 # The number of ROB writes
|
|
system.cpu.timesIdled 13814 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 80936 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
|
|
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.822280 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.822280 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.216130 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.216130 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 590791400 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 298595306 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 134 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 70 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 191828831 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 61 # number of replacements
|
|
system.cpu.icache.tagsinuse 820.655975 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 25576619 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1018 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 25124.380157 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 820.655975 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.400711 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.400711 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 25576619 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 25576619 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 25576619 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 25576619 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 25576619 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 25576619 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1290 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1290 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1290 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1290 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1290 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1290 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64574500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 64574500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 64574500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 64574500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 64574500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 64574500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 25577909 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 25577909 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 25577909 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 25577909 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 25577909 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 25577909 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50057.751938 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 50057.751938 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50057.751938 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 50057.751938 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50057.751938 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 50057.751938 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1018 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1018 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1018 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1018 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1018 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1018 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52495000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 52495000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52495000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 52495000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52495000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 52495000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51566.797642 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51566.797642 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51566.797642 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 51566.797642 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51566.797642 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 51566.797642 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 476 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 20892.456285 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 4029594 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 30400 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 132.552434 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 19980.495233 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 670.175654 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 241.785398 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.609756 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.020452 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.007379 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.637587 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1993856 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1993873 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2066867 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2066867 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 53312 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 53312 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2047168 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2047185 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2047168 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2047185 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1001 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 414 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1415 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1001 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 29414 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 30415 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1001 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 29414 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 30415 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 51299000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21301500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1218397500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1218397500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 51299000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1239699000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1290998000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 51299000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1239699000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1290998000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1018 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994270 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1995288 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2066867 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2066867 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82312 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 82312 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1018 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2076582 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2077600 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1018 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2076582 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2077600 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983301 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000208 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.000709 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352318 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.352318 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983301 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014165 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014639 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983301 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014165 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014639 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51247.752248 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51452.898551 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51307.773852 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42013.706897 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42013.706897 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51247.752248 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42146.562861 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 42446.095676 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51247.752248 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42146.562861 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 42446.095676 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 163 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 163 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1001 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 414 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1415 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1001 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 29414 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 30415 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1001 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 29414 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 30415 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38886556 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16149852 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55036408 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 860635717 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 860635717 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38886556 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 876785569 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 915672125 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38886556 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 876785569 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 915672125 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000208 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352318 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352318 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014639 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014639 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38847.708292 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39009.304348 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38894.987986 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29677.093690 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29677.093690 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38847.708292 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38847.708292 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 2072485 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4072.522671 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 71414123 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 2076581 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 34.390242 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 20537505000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4072.522671 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.994268 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.994268 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 40072419 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 40072419 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 71414123 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 71414123 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 71414123 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 71414123 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2626925 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2626925 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 98048 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 98048 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2724973 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2724973 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2724973 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2724973 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31341587500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 31341587500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2106729496 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2106729496 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 33448316996 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 33448316996 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 33448316996 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 33448316996 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 42699344 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 42699344 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 74139096 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 74139096 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 74139096 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 74139096 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061521 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.061521 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.036755 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.036755 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.036755 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.036755 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.903052 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.903052 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21486.715649 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 21486.715649 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 12274.733363 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 12274.733363 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 32679 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.440981 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2066867 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2066867 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632543 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 632543 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15848 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 15848 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 648391 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 648391 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 648391 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 648391 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994382 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1994382 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82200 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 82200 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2076582 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2076582 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2076582 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2076582 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987816500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987816500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833120496 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833120496 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820936996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 23820936996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820936996 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 23820936996 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046708 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046708 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.028009 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.028009 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.877130 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.877130 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22300.735961 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22300.735961 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|