757 lines
86 KiB
Plaintext
757 lines
86 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000016 # Number of seconds simulated
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sim_ticks 16021500 # Number of ticks simulated
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final_tick 16021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 25477 # Simulator instruction rate (inst/s)
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host_op_rate 46153 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 75857343 # Simulator tick rate (ticks/s)
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host_mem_usage 290184 # Number of bytes of host memory used
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host_seconds 0.21 # Real time elapsed on the host
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sim_insts 5380 # Number of instructions simulated
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sim_ops 9747 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1110507755 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 571232406 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1681740162 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1110507755 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1110507755 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1110507755 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 571232406 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1681740162 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 422 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 422 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 26944 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 26944 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 45 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 35 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 26 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 33 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 7 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 12 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 3 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 16004000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 422 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 233 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2229750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 13029750 # Sum of mem lat for all requests
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system.physmem.totBusLat 2110000 # Total cycles spent in databus access
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system.physmem.totBankLat 8690000 # Total cycles spent in bank access
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system.physmem.avgQLat 5283.77 # Average queueing delay per request
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system.physmem.avgBankLat 20592.42 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 30876.18 # Average memory access latency
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system.physmem.avgRdBW 1681.74 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1681.74 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 13.14 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.81 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 302 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 71.56 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 37924.17 # Average gap between requests
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system.cpu.branchPred.lookups 3090 # Number of BP lookups
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system.cpu.branchPred.condPredicted 3090 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 2310 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 714 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 30.909091 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 211 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 32044 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 9523 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 14230 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 3090 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 925 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 3948 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2389 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 3636 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 340 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 19279 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.312568 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.813131 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 15433 80.05% 80.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 214 1.11% 81.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 145 0.75% 81.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 217 1.13% 83.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 192 1.00% 84.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 169 0.88% 84.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 290 1.50% 86.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 155 0.80% 87.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2464 12.78% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 19279 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.096430 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.444077 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 10008 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 3780 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 3579 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1785 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 24215 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1785 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 10348 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2654 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 3350 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 726 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 620 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 25234 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 54863 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 54847 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 14171 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 1819 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2277 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1616 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 20098 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 17004 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 251 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 9536 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 13688 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 19279 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.881996 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.736426 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 13831 71.74% 71.74% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1491 7.73% 79.48% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 1108 5.75% 85.22% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 718 3.72% 88.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 686 3.56% 92.50% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 589 3.06% 95.56% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 582 3.02% 98.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 230 1.19% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 44 0.23% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 19279 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 127 76.51% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.51% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 24 14.46% 90.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 15 9.04% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 13619 80.09% 80.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 1977 11.63% 91.80% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1394 8.20% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 17004 # Type of FU issued
|
|
system.cpu.iq.rate 0.530645 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 166 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.009762 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 53696 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 29666 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 17163 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 167 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1224 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1785 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1955 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 20123 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2277 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1616 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 674 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 16111 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 893 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3149 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1620 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1296 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.502777 # Inst execution rate
|
|
system.cpu.iew.wb_sent 15852 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 15645 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 10112 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 15481 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.488235 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.653188 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 10375 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 582 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 17494 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.557162 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.425293 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 13941 79.69% 79.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1339 7.65% 87.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 594 3.40% 90.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 714 4.08% 94.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 361 2.06% 96.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 136 0.78% 97.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 122 0.70% 98.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 74 0.42% 98.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 213 1.22% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 17494 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5380 # Number of instructions committed
|
|
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 1988 # Number of memory references committed
|
|
system.cpu.commit.loads 1053 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1208 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 9654 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 106 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 37403 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 42056 # The number of ROB writes
|
|
system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 12765 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
|
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
|
system.cpu.cpi 5.956134 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 5.956134 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.167894 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.167894 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 28607 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 17139 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 7155 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 134.419040 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1594 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 5.713262 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 134.419040 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.065634 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.065634 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1594 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1594 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1594 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1594 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1594 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1594 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 371 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19224000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 19224000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 19224000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 19224000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 19224000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 19224000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.188804 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.188804 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.188804 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.188804 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.188804 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.188804 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51816.711590 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 51816.711590 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 51816.711590 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 51816.711590 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15030000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 15030000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15030000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 15030000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15030000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 15030000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142494 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.142494 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.142494 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53678.571429 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53678.571429 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 167.756635 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 344 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.005814 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 134.530220 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 33.226414 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004106 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001014 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005120 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 345 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 422 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 422 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14740500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3980000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18720500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4206500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4206500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 14740500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8186500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 22927000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 14740500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8186500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 22927000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 67 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 424 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 424 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996429 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.985075 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.994236 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996429 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.993056 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995283 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996429 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995283 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52833.333333 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60303.030303 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54262.318841 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54629.870130 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54629.870130 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 54329.383886 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 54329.383886 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 345 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 422 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 422 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11293716 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3166039 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14459755 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3259559 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3259559 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11293716 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6425598 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17719314 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11293716 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6425598 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17719314 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996429 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994236 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996429 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995283 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996429 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995283 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40479.268817 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47970.287879 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41912.333333 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42331.935065 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42331.935065 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40479.268817 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44934.251748 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41988.895735 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40479.268817 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44934.251748 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41988.895735 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 84.412169 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2338 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 16.236111 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 84.412169 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020608 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020608 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2338 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2338 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2338 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2338 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 213 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 213 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 213 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 213 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8307000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 8307000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4438000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4438000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 12745000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 12745000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 12745000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 12745000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084158 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.084158 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.083497 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.083497 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.083497 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.083497 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61080.882353 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 61080.882353 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57636.363636 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 57636.363636 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 59835.680751 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 59835.680751 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 69 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4057000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4057000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8341000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 8341000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8341000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 8341000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60552.238806 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60552.238806 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55636.363636 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55636.363636 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
|
|
---------- End Simulation Statistics ----------
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