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stats: Update stats to reflect bus retry changes

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This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
This commit is contained in:
Andreas Hansson 2013-03-26 14:46:49 -04:00
parent 93a8423dea
commit 08f7a8bc00
23 changed files with 13764 additions and 13765 deletions
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2802
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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70
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 1.841686 # Nu
sim_ticks 1841685557500 # Number of ticks simulated
final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 244491 # Simulator instruction rate (inst/s)
host_op_rate 244491 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6478446279 # Simulator tick rate (ticks/s)
host_mem_usage 315916 # Number of bytes of host memory used
host_seconds 284.28 # Real time elapsed on the host
host_inst_rate 257826 # Simulator instruction rate (inst/s)
host_op_rate 257826 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6831790357 # Simulator tick rate (ticks/s)
host_mem_usage 316032 # Number of bytes of host memory used
host_seconds 269.58 # Real time elapsed on the host
sim_insts 69503534 # Number of instructions simulated
sim_ops 69503534 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory
@ -60,7 +60,7 @@ system.physmem.bw_total::cpu2.data 1468811 # To
system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 109963 # Total number of read requests seen
system.physmem.writeReqs 45515 # Total number of write requests seen
system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 155519 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 7037632 # Total number of bytes read from memory
system.physmem.bytesWritten 2912960 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize()
@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::13 2879 # Tr
system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
system.physmem.totGap 1840673470000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@ -180,14 +180,14 @@ system.physmem.wrQLenPdf::28 8 # Wh
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
system.physmem.totQLat 2376401250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 4386835000 # Sum of mem lat for all requests
system.physmem.totQLat 2376402250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 4386836000 # Sum of mem lat for all requests
system.physmem.totBusLat 549785000 # Total cycles spent in databus access
system.physmem.totBankLat 1460648750 # Total cycles spent in bank access
system.physmem.avgQLat 21612.10 # Average queueing delay per request
system.physmem.avgQLat 21612.11 # Average queueing delay per request
system.physmem.avgBankLat 13283.82 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 39895.91 # Average memory access latency
system.physmem.avgMemAccLat 39895.92 # Average memory access latency
system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s
@ -512,12 +512,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 4305588904 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 4305588904 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4314766902 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4314766902 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4314766902 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4314766902 # number of overall miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 4305944082 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 4305944082 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4315122080 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4315122080 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4315122080 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4315122080 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@ -536,12 +536,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103619.293993 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 103619.293993 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 103409.632163 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 103409.632163 # average overall miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103627.841789 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 103627.841789 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 103418.144518 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 103418.144518 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 103418.144518 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 103418.144518 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked
@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16837
system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433126461 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 3433126461 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 3438715710 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3438715710 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 3438715710 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3438715710 # number of overall MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433481639 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 3433481639 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 3439070888 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3439070888 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 3439070888 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3439070888 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses
@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523
system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204742.751729 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204742.751729 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204763.933624 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204763.933624 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).

1644
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
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2606
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
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1878
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
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@ -4,26 +4,26 @@ sim_seconds 5.204983 # Nu
sim_ticks 5204982530500 # Number of ticks simulated
final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 107235 # Simulator instruction rate (inst/s)
host_op_rate 205734 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5169140013 # Simulator tick rate (ticks/s)
host_mem_usage 810688 # Number of bytes of host memory used
host_seconds 1006.93 # Real time elapsed on the host
sim_insts 107979054 # Number of instructions simulated
sim_ops 207160582 # Number of ops (including micro ops) simulated
host_inst_rate 97445 # Simulator instruction rate (inst/s)
host_op_rate 186950 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4697195864 # Simulator tick rate (ticks/s)
host_mem_usage 811856 # Number of bytes of host memory used
host_seconds 1108.10 # Real time elapsed on the host
sim_insts 107979048 # Number of instructions simulated
sim_ops 207160548 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 864449224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 69078733 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 864449144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 69078721 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 160961632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 27339818 # Number of bytes read from this memory
system.physmem.bytes_read::total 1122197487 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 864449224 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 160961632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1025410856 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu1.inst 160961656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 27339822 # Number of bytes read from this memory
system.physmem.bytes_read::total 1122197423 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 864449144 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 160961656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1025410800 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory
@ -32,13 +32,13 @@ system.physmem.bytes_written::total 72643771 # Nu
system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 108056153 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 12053065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 108056143 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 12053062 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 20120204 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 4057615 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144329463 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 20120207 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 4057616 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144329454 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory
@ -47,16 +47,16 @@ system.physmem.num_writes::total 10106709 # Nu
system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 166081100 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 13271655 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 166081085 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 13271653 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 30924529 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 5252624 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 215600625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 166081100 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 30924529 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 197005629 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 30924533 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 5252625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 215600613 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 166081085 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 30924533 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 197005618 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s)
@ -65,16 +65,16 @@ system.physmem.bw_write::total 13956583 # Wr
system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 166081100 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 22559437 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 166081085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 22559435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 30924529 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 30924533 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 9346761 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 229557208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 229557196 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 810 # Total number of read requests seen
system.physmem.writeReqs 46736 # Total number of write requests seen
system.physmem.cpureqs 48918 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 47278 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 51840 # Total number of bytes read from memory
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize()
@ -114,7 +114,7 @@ system.physmem.perBankWrReqs::13 2864 # Tr
system.physmem.perBankWrReqs::14 3048 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 3040 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 1670 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry
system.physmem.totGap 63182142000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@ -278,23 +278,23 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0
system.cpu0.numCycles 10407785676 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 92551747 # Number of instructions committed
system.cpu0.committedOps 178518572 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 168457773 # Number of integer alu accesses
system.cpu0.committedInsts 92551738 # Number of instructions committed
system.cpu0.committedOps 178518541 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 168457745 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 16414014 # number of instructions that are conditional controls
system.cpu0.num_int_insts 168457773 # number of integer instructions
system.cpu0.num_conditional_control_insts 16414009 # number of instructions that are conditional controls
system.cpu0.num_int_insts 168457745 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 415888554 # number of times the integer registers were read
system.cpu0.num_int_register_writes 210334552 # number of times the integer registers were written
system.cpu0.num_int_register_reads 415888462 # number of times the integer registers were read
system.cpu0.num_int_register_writes 210334505 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 20039559 # number of memory refs
system.cpu0.num_load_insts 12899832 # Number of load instructions
system.cpu0.num_mem_refs 20039556 # number of memory refs
system.cpu0.num_load_insts 12899829 # Number of load instructions
system.cpu0.num_store_insts 7139727 # Number of store instructions
system.cpu0.num_idle_cycles 9669887298.959074 # Number of idle cycles
system.cpu0.num_busy_cycles 737898377.040926 # Number of busy cycles
system.cpu0.num_idle_cycles 9669887390.939814 # Number of idle cycles
system.cpu0.num_busy_cycles 737898285.060187 # Number of busy cycles
system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
@ -302,23 +302,23 @@ system.cpu0.kern.inst.quiesce 0 # nu
system.cpu1.numCycles 10409965061 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 15427307 # Number of instructions committed
system.cpu1.committedOps 28642010 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 28123688 # Number of integer alu accesses
system.cpu1.committedInsts 15427310 # Number of instructions committed
system.cpu1.committedOps 28642007 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 28123684 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1978312 # number of instructions that are conditional controls
system.cpu1.num_int_insts 28123688 # number of integer instructions
system.cpu1.num_conditional_control_insts 1978311 # number of instructions that are conditional controls
system.cpu1.num_int_insts 28123684 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 73029248 # number of times the integer registers were read
system.cpu1.num_int_register_writes 31865943 # number of times the integer registers were written
system.cpu1.num_int_register_reads 73029212 # number of times the integer registers were read
system.cpu1.num_int_register_writes 31865924 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 7025199 # number of memory refs
system.cpu1.num_load_insts 4066765 # Number of load instructions
system.cpu1.num_mem_refs 7025200 # number of memory refs
system.cpu1.num_load_insts 4066766 # Number of load instructions
system.cpu1.num_store_insts 2958434 # Number of store instructions
system.cpu1.num_idle_cycles 10280018133.934025 # Number of idle cycles
system.cpu1.num_busy_cycles 129946927.065975 # Number of busy cycles
system.cpu1.num_idle_cycles 10280018132.934025 # Number of idle cycles
system.cpu1.num_busy_cycles 129946928.065975 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed

1304
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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132
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 0.434779 # Nu
sim_ticks 434778577000 # Number of ticks simulated
final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 65958 # Simulator instruction rate (inst/s)
host_op_rate 121963 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34681028 # Simulator tick rate (ticks/s)
host_mem_usage 469672 # Number of bytes of host memory used
host_seconds 12536.50 # Real time elapsed on the host
host_inst_rate 92341 # Simulator instruction rate (inst/s)
host_op_rate 170748 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48553388 # Simulator tick rate (ticks/s)
host_mem_usage 422424 # Number of bytes of host memory used
host_seconds 8954.65 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory
@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 56304964 # To
system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 385749 # Total number of read requests seen
system.physmem.writeReqs 293653 # Total number of write requests seen
system.physmem.cpureqs 898439 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 895346 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 24687808 # Total number of bytes read from memory
system.physmem.bytesWritten 18793792 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize()
@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 17888 # Tr
system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 3123 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry
system.physmem.totGap 434778560000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 37 # Wh
system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see
system.physmem.totQLat 3433767500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12026720000 # Sum of mem lat for all requests
system.physmem.totQLat 3433770500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12026723000 # Sum of mem lat for all requests
system.physmem.totBusLat 1927915000 # Total cycles spent in databus access
system.physmem.totBankLat 6665037500 # Total cycles spent in bank access
system.physmem.avgQLat 8905.39 # Average queueing delay per request
system.physmem.avgQLat 8905.40 # Average queueing delay per request
system.physmem.avgBankLat 17285.61 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 31191.00 # Average memory access latency
system.physmem.avgMemAccLat 31191.01 # Average memory access latency
system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s
@ -196,17 +196,17 @@ system.cpu.fetch.Branches 214994146 # Nu
system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 231974123 # Number of cycles fetch has spent blocked
system.cpu.fetch.BlockedCycles 231974121 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 854248204 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 854248202 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 487377953 57.05% 57.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 487377951 57.05% 57.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total)
@ -218,11 +218,11 @@ system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 854248204 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 854248202 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 188537109 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 188537107 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing
@ -230,7 +230,7 @@ system.cpu.decode.DecodedInsts 2166915251 # Nu
system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 54166582 # Number of cycles rename is blocking
system.cpu.rename.BlockCycles 54166580 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking
@ -259,11 +259,11 @@ system.cpu.iq.iqSquashedInstsIssued 841556 # Nu
system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 854248204 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 854248202 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 233580311 27.34% 27.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 233580309 27.34% 27.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle
@ -275,7 +275,7 @@ system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 854248204 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 854248202 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available
@ -348,7 +348,7 @@ system.cpu.iq.FU_type_0::total 1808317213 # Ty
system.cpu.iq.rate 2.079584 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4486980237 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 4486980235 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads
@ -368,7 +368,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 12353 #
system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16317048 # Number of cycles IEW is blocking
system.cpu.iew.iewBlockCycles 16317046 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch
@ -401,11 +401,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 784230563 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 784230561 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 290802586 37.08% 37.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 290802584 37.08% 37.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle
@ -417,7 +417,7 @@ system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 784230563 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 784230561 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -430,10 +430,10 @@ system.cpu.commit.int_insts 1528317561 # Nu
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2748434579 # The number of ROB reads
system.cpu.rob.rob_reads 2748434577 # The number of ROB reads
system.cpu.rob.rob_writes 4138359582 # The number of ROB writes
system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 15308951 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 15308953 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
@ -532,14 +532,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4129.492827
system.cpu.icache.overall_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 353068 # number of replacements
system.cpu.l2cache.tagsinuse 29624.531163 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 29624.531166 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3697718 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 385429 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 9.593772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 201975419000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21048.484716 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 21048.484720 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 232.592119 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 8343.454327 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 8343.454326 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.642349 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.007098 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.254622 # Average percentage of cache occupancy
@ -573,18 +573,18 @@ system.cpu.l2cache.overall_misses::cpu.inst 3245 #
system.cpu.l2cache.overall_misses::cpu.data 382536 # number of overall misses
system.cpu.l2cache.overall_misses::total 385781 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201201000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144981454 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 10346182454 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144983954 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 10346184954 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7392500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 7392500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10367117000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10367117000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 201201000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20512098454 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20713299454 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20512100954 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20713301954 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 201201000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20512098454 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20713299454 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20512100954 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20713301954 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 7061 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762430 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1769491 # number of ReadReq accesses(hits+misses)
@ -614,18 +614,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459567
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150976 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151834 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62003.389831 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.709453 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.413123 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.723676 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.427088 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53691.860029 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53691.866510 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53691.860029 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53691.866510 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -650,18 +650,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 3245
system.cpu.l2cache.overall_mshr_misses::cpu.data 382536 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160858519 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969651402 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130509921 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969654402 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130512921 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2164647428 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2164647428 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7779866278 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7779866278 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160858519 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749517680 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15910376199 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749520680 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15910379199 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160858519 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749517680 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15910376199 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749520680 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15910379199 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099733 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101169 # mshr miss rate for ReadReq accesses
@ -676,18 +676,18 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.459567
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151834 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49571.192296 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.847245 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.529737 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.864313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.546496 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.947133 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.947133 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37626.793243 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37626.793243 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2529656 # number of replacements
system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use
@ -716,12 +716,12 @@ system.cpu.dcache.overall_misses::cpu.data 3900651 #
system.cpu.dcache.overall_misses::total 3900651 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898482499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23898482499 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75300273999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75300273999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75300273999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75300273999 # number of overall miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898481499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23898481499 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75300272999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75300272999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75300272999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75300272999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
@ -740,12 +740,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.009545
system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.920793 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.920793 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19304.540191 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19304.540191 # average overall miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.919798 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.919798 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19304.539934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19304.539934 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked

70
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.042726 # Nu
sim_ticks 42726055500 # Number of ticks simulated
final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 89848 # Simulator instruction rate (inst/s)
host_op_rate 89848 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43455006 # Simulator tick rate (ticks/s)
host_mem_usage 257260 # Number of bytes of host memory used
host_seconds 983.23 # Real time elapsed on the host
host_inst_rate 80618 # Simulator instruction rate (inst/s)
host_op_rate 80618 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38990762 # Simulator tick rate (ticks/s)
host_mem_usage 257380 # Number of bytes of host memory used
host_seconds 1095.80 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 237287713 # To
system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165519 # Total number of read requests seen
system.physmem.writeReqs 113997 # Total number of write requests seen
system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 279517 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 10593216 # Total number of bytes read from memory
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 7250 # Tr
system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
system.physmem.totGap 42726035000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 1 # Wh
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests
system.physmem.totQLat 7053831750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 9647394250 # Sum of mem lat for all requests
system.physmem.totBusLat 827595000 # Total cycles spent in databus access
system.physmem.totBankLat 1765967500 # Total cycles spent in bank access
system.physmem.avgQLat 42616.50 # Average queueing delay per request
system.physmem.avgQLat 42616.45 # Average queueing delay per request
system.physmem.avgBankLat 10669.27 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 58285.77 # Average memory access latency
system.physmem.avgMemAccLat 58285.72 # Average memory access latency
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
@ -403,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 165519 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996609634 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11996609634 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13509764634 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13965064634 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13509764634 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13965064634 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses)
@ -438,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.569383 #
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91653.434033 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91653.434033 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84371.369051 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84371.369051 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -470,14 +470,14 @@ system.cpu.l2cache.overall_mshr_misses::total 165519
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407373592 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407373592 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578155437 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11945053093 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578155437 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11945053093 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses
@ -492,14 +492,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79511.758578 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79511.758578 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200249 # number of replacements
system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use

58
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.023888 # Nu
sim_ticks 23888231000 # Number of ticks simulated
final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 143918 # Simulator instruction rate (inst/s)
host_op_rate 143918 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43194720 # Simulator tick rate (ticks/s)
host_mem_usage 260336 # Number of bytes of host memory used
host_seconds 553.04 # Real time elapsed on the host
host_inst_rate 183235 # Simulator instruction rate (inst/s)
host_op_rate 183235 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54995028 # Simulator tick rate (ticks/s)
host_mem_usage 260452 # Number of bytes of host memory used
host_seconds 434.37 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory
@ -604,14 +604,14 @@ system.cpu.l2cache.overall_misses::total 166330 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 493837000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614539500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2108376500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203454500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12203454500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203503384 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12203503384 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 493837000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13817994000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 14311831000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13818042884 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 14311879884 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 493837000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13817994000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 14311831000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13818042884 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 14311879884 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 93652 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 62106 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 155758 # number of ReadReq accesses(hits+misses)
@ -639,14 +639,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.555949 #
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64368.743483 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57947.724499 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 59334.060337 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.435059 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.435059 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.808801 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.808801 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86044.796489 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87093.262766 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86045.090387 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86044.796489 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87093.262766 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86045.090387 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total 166330
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398141894 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1271865950 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1670007844 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613542919 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613542919 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613591803 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613591803 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398141894 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885408869 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 12283550763 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885457753 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 12283599647 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398141894 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885408869 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12283550763 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885457753 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12283599647 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448620 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228136 # mshr miss rate for ReadReq accesses
@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.555949
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51895.450209 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45648.767138 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46997.462824 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81145.776010 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81145.776010 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81146.149752 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81146.149752 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.439039 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.776450 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.439039 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.776450 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 201434 # number of replacements
system.cpu.dcache.tagsinuse 4076.506217 # Cycle average of tags in use

890
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
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14
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu
sim_ticks 993559170500 # Number of ticks simulated
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139940 # Simulator instruction rate (inst/s)
host_op_rate 139940 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 76403951 # Simulator tick rate (ticks/s)
host_mem_usage 449176 # Number of bytes of host memory used
host_seconds 13004.03 # Real time elapsed on the host
host_inst_rate 90803 # Simulator instruction rate (inst/s)
host_op_rate 90803 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49576515 # Simulator tick rate (ticks/s)
host_mem_usage 449304 # Number of bytes of host memory used
host_seconds 20040.92 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 126177745 # To
system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1959688 # Total number of read requests seen
system.physmem.writeReqs 1018058 # Total number of write requests seen
system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 125420032 # Total number of bytes read from memory
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize()
@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 64147 # Tr
system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
system.physmem.totGap 993559118500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes

1234
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
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1184
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
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800
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
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454
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.913475 # Nu
sim_ticks 1913474690000 # Number of ticks simulated
final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1324010 # Simulator instruction rate (inst/s)
host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45134311907 # Simulator tick rate (ticks/s)
host_mem_usage 328328 # Number of bytes of host memory used
host_seconds 42.40 # Real time elapsed on the host
host_inst_rate 960952 # Simulator instruction rate (inst/s)
host_op_rate 960952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32757999490 # Simulator tick rate (ticks/s)
host_mem_usage 329472 # Number of bytes of host memory used
host_seconds 58.41 # Real time elapsed on the host
sim_insts 56131527 # Number of instructions simulated
sim_ops 56131527 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@ -40,7 +40,7 @@ system.physmem.bw_total::tsunami.ide 1386010 # To
system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 443158 # Total number of read requests seen
system.physmem.writeReqs 115703 # Total number of write requests seen
system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28362112 # Total number of bytes read from memory
system.physmem.bytesWritten 7404992 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize()
@ -80,7 +80,7 @@ system.physmem.perBankWrReqs::13 7186 # Tr
system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
system.physmem.totGap 1913462790000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@ -96,26 +96,26 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 115703 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 402453 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4723 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3684 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1422 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1367 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
@ -132,11 +132,11 @@ system.physmem.wrQLenPdf::0 3531 # Wh
system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see
@ -155,19 +155,19 @@ system.physmem.wrQLenPdf::23 1500 # Wh
system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests
system.physmem.wrQLenPdf::27 378 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests
system.physmem.totBusLat 2215485000 # Total cycles spent in databus access
system.physmem.totBankLat 6297005000 # Total cycles spent in bank access
system.physmem.avgQLat 10649.88 # Average queueing delay per request
system.physmem.avgBankLat 14211.35 # Average bank access latency per request
system.physmem.totBankLat 6297018750 # Total cycles spent in bank access
system.physmem.avgQLat 10630.27 # Average queueing delay per request
system.physmem.avgBankLat 14211.38 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29861.22 # Average memory access latency
system.physmem.avgMemAccLat 29841.64 # Average memory access latency
system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s
@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10653271428 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10653271428 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10674199426 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10674199426 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10674199426 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10674199426 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.083269 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256384.083269 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255822.634536 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255822.634536 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.516778 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491261949 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8491261949 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8503193198 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8503193198 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8503193198 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8503193198 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.665311 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.665311 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@ -335,8 +335,8 @@ system.cpu.num_fp_register_writes 166418 # nu
system.cpu.num_mem_refs 15461819 # number of memory refs
system.cpu.num_load_insts 9093811 # Number of load instructions
system.cpu.num_store_insts 6368008 # Number of store instructions
system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles
system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles
system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles
system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles
system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.938869 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
@ -352,10 +352,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu
system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
@ -420,9 +420,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323898 # fr
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
@ -476,12 +476,12 @@ system.cpu.icache.demand_misses::cpu.inst 928628 # n
system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses
system.cpu.icache.overall_misses::total 928628 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770432000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12770432000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12770432000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12770432000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12770432000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12770432000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses
@ -494,12 +494,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540
system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.935113 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13751.935113 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13751.935113 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13751.935113 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -514,53 +514,53 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 928628
system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913022000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10913022000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913022000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10913022000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913022000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10913022000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913176000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10913176000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913176000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10913176000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913176000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10913176000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.769277 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.769277 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.935113 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.935113 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 336244 # number of replacements
system.cpu.l2cache.tagsinuse 65321.744295 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2445552 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 65321.744334 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2445560 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.092465 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 6.092485 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 55750.890928 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 4786.700552 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 4784.152815 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 55750.890947 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 4786.700562 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 4784.152824 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 813981 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1729299 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 834498 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 834498 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits::cpu.data 813988 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1729306 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1001495 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1916813 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1001502 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1916820 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 915318 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1001495 # number of overall hits
system.cpu.l2cache.overall_hits::total 1916813 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1001502 # number of overall hits
system.cpu.l2cache.overall_hits::total 1916820 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 271963 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses
@ -574,60 +574,60 @@ system.cpu.l2cache.demand_misses::total 402109 # nu
system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 388819 # number of overall misses
system.cpu.l2cache.overall_misses::total 402109 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831194000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699138000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12530332000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831348000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699456000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12530804000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596958000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5596958000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 831194000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17296096000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 18127290000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 831194000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17296096000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 18127290000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596921000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5596921000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 831348000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17296377000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 18127725000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 831348000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17296377000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 18127725000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1085944 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2014552 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 834498 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 834498 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1085951 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2014559 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 1390321 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2318929 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2318922 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1390321 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2318929 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250439 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250438 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279663 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279661 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279663 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279661 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62542.814146 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43017.388395 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 43927.082274 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62554.401806 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43018.557671 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 43928.736946 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47896.197029 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47896.197029 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 45080.537864 # average overall miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47895.880400 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 45081.619660 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 45081.619660 # average overall miss latency
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -651,19 +651,19 @@ system.cpu.l2cache.demand_mshr_misses::total 402109
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system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360475460 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520350040 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666421030 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520631540 # number of overall MSHR miss cycles
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@ -671,31 +671,31 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250438 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50144.547028 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30741.223843 # average ReadReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35600.705826 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -703,47 +703,47 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1389801 # number of replacements
system.cpu.dcache.replacements 1389808 # number of replacements
system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use
system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 14037921 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1390320 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.096899 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
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system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses
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system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles
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system.cpu.dcache.overall_misses::total 1373094 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 22868320000 # number of ReadReq miss cycles
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@ -756,8 +756,8 @@ system.cpu.dcache.demand_accesses::cpu.data 15028766 #
system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120403 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.120403 # miss rate for ReadReq accesses
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system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses
@ -766,16 +766,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091364
system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 21398.119410 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.300726 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22761.711143 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22761.711143 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -784,36 +784,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks
system.cpu.dcache.writebacks::total 834498 # number of writebacks
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses
@ -822,16 +822,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364
system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

716
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu
sim_ticks 5195162021000 # Number of ticks simulated
final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 926995 # Simulator instruction rate (inst/s)
host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37543942770 # Simulator tick rate (ticks/s)
host_mem_usage 611560 # Number of bytes of host memory used
host_seconds 138.38 # Real time elapsed on the host
sim_insts 128273323 # Number of instructions simulated
sim_ops 247275942 # Number of ops (including micro ops) simulated
host_inst_rate 697576 # Simulator instruction rate (inst/s)
host_op_rate 1344736 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28252317760 # Simulator tick rate (ticks/s)
host_mem_usage 611664 # Number of bytes of host memory used
host_seconds 183.88 # Real time elapsed on the host
sim_insts 128273373 # Number of instructions simulated
sim_ops 247275988 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
@ -48,16 +48,16 @@ system.physmem.bw_total::cpu.data 1734722 # To
system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198400 # Total number of read requests seen
system.physmem.writeReqs 126924 # Total number of write requests seen
system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 12697600 # Total number of bytes read from memory
system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
@ -88,7 +88,7 @@ system.physmem.perBankWrReqs::13 7628 # Tr
system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
system.physmem.totGap 5195161957500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@ -104,27 +104,27 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 126924 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
@ -136,15 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
@ -159,23 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh
system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests
system.physmem.totBusLat 991710000 # Total cycles spent in databus access
system.physmem.totBankLat 2804120000 # Total cycles spent in bank access
system.physmem.avgQLat 20536.88 # Average queueing delay per request
system.physmem.avgBankLat 14137.80 # Average bank access latency per request
system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests
system.physmem.totBusLat 991715000 # Total cycles spent in databus access
system.physmem.totBankLat 2804628750 # Total cycles spent in bank access
system.physmem.avgQLat 20766.54 # Average queueing delay per request
system.physmem.avgBankLat 14140.30 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 39674.68 # Average memory access latency
system.physmem.avgMemAccLat 39906.83 # Average memory access latency
system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
@ -184,8 +184,8 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.66 # Average write queue length over time
system.physmem.readRowHits 175586 # Number of row buffer hits during reads
system.physmem.writeRowHits 94818 # Number of row buffer hits during writes
system.physmem.readRowHits 175593 # Number of row buffer hits during reads
system.physmem.writeRowHits 94810 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
system.physmem.avgGap 15969193.66 # Average gap between requests
@ -206,14 +206,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47564
system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
system.iocache.overall_misses::total 47564 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732357682 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10732357682 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10870344079 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10870344079 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10870344079 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10870344079 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
@ -230,19 +230,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.559974 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229716.559974 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 228541.419540 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 228541.419540 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@ -256,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564
system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301559588 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8301559588 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8395637015 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8395637015 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
@ -272,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.491182 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.491182 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@ -296,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
system.cpu.numCycles 10390324042 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 128273323 # Number of instructions committed
system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses
system.cpu.committedInsts 128273373 # Number of instructions committed
system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls
system.cpu.num_int_insts 232011652 # number of integer instructions
system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls
system.cpu.num_int_insts 232011695 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read
system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written
system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read
system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 22232130 # number of memory refs
system.cpu.num_load_insts 13871776 # Number of load instructions
system.cpu.num_store_insts 8360354 # Number of store instructions
system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles
system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles
system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942191 # Percentage of idle cycles
system.cpu.num_mem_refs 22232145 # number of memory refs
system.cpu.num_load_insts 13871789 # Number of load instructions
system.cpu.num_store_insts 8360356 # Number of store instructions
system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles
system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles
system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942190 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.replacements 791510 # number of replacements
system.cpu.icache.replacements 791527 # number of replacements
system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use
system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks.
system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits
system.cpu.icache.overall_hits::total 144497671 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses
system.cpu.icache.overall_misses::total 792029 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits
system.cpu.icache.overall_hits::total 144497724 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses
system.cpu.icache.overall_misses::total 792046 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 10958971500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145289770 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145289770 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145289770 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145289770 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145289770 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145289770 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13831.869161 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13836.281605 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -370,40 +370,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792029 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 792029 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 792029 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 792029 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 792029 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 792029 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9371183500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9371183500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9371183500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9371183500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9371183500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9371183500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792046 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 792046 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 792046 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 792046 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 792046 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 792046 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9374879500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9374879500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9374879500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9374879500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9374879500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11836.281605 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11836.281605 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 3425 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use
system.cpu.itb_walker_cache.tagsinuse 3.077880 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192368 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.192368 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.warmup_cycle 5164120857000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077880 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192367 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.192367 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
@ -479,13 +479,13 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 7540 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use
system.cpu.dtb_walker_cache.replacements 7539 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.062514 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7554 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.744506 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7553 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.744737 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062514 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits
@ -559,63 +559,63 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1618785 # number of replacements
system.cpu.dcache.replacements 1618797 # number of replacements
system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use
system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 20025896 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1619309 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.366939 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 11988262 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11988262 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8035470 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8035470 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20023732 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20023732 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20023732 # number of overall hits
system.cpu.dcache.overall_hits::total 20023732 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1306602 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1306602 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 314890 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 314890 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1621492 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1621492 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1621492 # number of overall misses
system.cpu.dcache.overall_misses::total 1621492 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18343104000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18343104000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556691000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8556691000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 26899795000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 26899795000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 26899795000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 26899795000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13294864 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13294864 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8350360 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8350360 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21645224 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21645224 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 21645224 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_hits::total 11988260 # number of ReadReq hits
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system.cpu.dcache.overall_hits::total 20023734 # number of overall hits
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system.cpu.dcache.overall_misses::total 1621505 # number of overall misses
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system.cpu.dcache.overall_miss_latency::total 26903108500 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::total 8350362 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.overall_accesses::total 21645239 # number of overall (read+write) accesses
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -624,46 +624,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467833000 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12040.465186 # average ReadReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -672,17 +672,17 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 86864 # number of replacements
system.cpu.l2cache.tagsinuse 64770.428925 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3484716 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 64770.428854 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3484759 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.981554 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 22.981837 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50336.266909 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 50336.272506 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 11075.878059 # Average occupied blocks per requestor
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@ -690,25 +690,25 @@ system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Av
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@ -730,44 +730,44 @@ system.cpu.l2cache.overall_misses::cpu.data 141743 #
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system.cpu.l2cache.ReadReq_accesses::total 2107001 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1539412 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1539412 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 312725 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 312725 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 792016 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1618572 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2419695 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 792033 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1618583 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2419723 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 792016 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1618572 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2419695 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 792033 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1618583 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2419723 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses
@ -775,37 +775,37 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737
system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362485 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.362485 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087573 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063901 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087572 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063900 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000158 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001812 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016252 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087573 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063901 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087572 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063900 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61194.958048 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58056.068346 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 59036.824758 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11858.137830 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11858.137830 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49254.247605 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49254.247605 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61467.565258 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58134.296283 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 59175.677968 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11861.436950 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11861.436950 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49261.917994 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49261.917994 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51864.879285 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51907.557835 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51864.879285 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51907.557835 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -837,29 +837,29 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141743
system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 627778857 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1295316957 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923433320 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190411275 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190411275 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 631288357 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1297548953 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1929174816 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14616845 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14616845 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4191303025 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4191303025 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 627778857 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5485728232 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6113844595 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 631288357 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5488851978 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6120477841 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 631288357 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5488851978 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6120477841 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305022500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305022500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896198000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896198000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses
@ -867,37 +867,37 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063900 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063900 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

2847
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
View file

File diff suppressed because it is too large Load diff

24
tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt
View file

@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 31243111314 # Simulator tick rate (ticks/s)
host_mem_usage 230668 # Number of bytes of host memory used
host_seconds 3.20 # Real time elapsed on the host
host_tick_rate 15527580566 # Simulator tick rate (ticks/s)
host_mem_usage 226756 # Number of bytes of host memory used
host_seconds 6.44 # Real time elapsed on the host
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory
@ -151,9 +151,9 @@ system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% #
system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::total 1 # Read request-response latency
system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency
system.monitor.writeLatencyHist::mean 30000 # Write request-response latency
system.monitor.writeLatencyHist::gmean 29999.999984 # Write request-response latency
system.monitor.writeLatencyHist::stdev 0 # Write request-response latency
system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency
system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency
system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency
system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency
@ -204,8 +204,8 @@ system.monitor.ittReadRead::min_value 0 # Re
system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time
system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time
system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::mean 29999.695203 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::stdev 539.134360 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::mean 29999.695301 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::stdev 539.310304 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time
@ -229,11 +229,11 @@ system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # W
system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::max_value 994000 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::max_value 994328 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time
system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time
system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time
system.monitor.ittReqReq::stdev 539.308135 # Request-to-request inter transaction time
system.monitor.ittReqReq::stdev 539.488612 # Request-to-request inter transaction time
system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time
@ -256,8 +256,8 @@ system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Re
system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::min_value 5000 # Request-to-request inter transaction time
system.monitor.ittReqReq::max_value 994000 # Request-to-request inter transaction time
system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time
system.monitor.ittReqReq::max_value 994328 # Request-to-request inter transaction time
system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time
system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions