08f7a8bc00
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
1074 lines
125 KiB
Plaintext
1074 lines
125 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.533141 # Number of seconds simulated
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sim_ticks 2533140518500 # Number of ticks simulated
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final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 41838 # Simulator instruction rate (inst/s)
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host_op_rate 53833 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1757330352 # Simulator tick rate (ticks/s)
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host_mem_usage 435908 # Number of bytes of host memory used
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host_seconds 1441.47 # Real time elapsed on the host
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sim_insts 60307702 # Number of instructions simulated
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sim_ops 77599241 # Number of ops (including micro ops) simulated
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system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory
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system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15096807 # Total number of read requests seen
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system.physmem.writeReqs 813124 # Total number of write requests seen
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system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 966195648 # Total number of bytes read from memory
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system.physmem.bytesWritten 52039936 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2533139407500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 36 # Categorize read packet sizes
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system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 154563 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 754018 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 59106 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see
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system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests
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system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
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system.physmem.totBankLat 16909241250 # Total cycles spent in bank access
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system.physmem.avgQLat 26044.77 # Average queueing delay per request
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system.physmem.avgBankLat 1120.08 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 32164.85 # Average memory access latency
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system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.14 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.19 # Average read queue length over time
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system.physmem.avgWrQLen 11.32 # Average write queue length over time
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system.physmem.readRowHits 15020284 # Number of row buffer hits during reads
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system.physmem.writeRowHits 793162 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes
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system.physmem.avgGap 159217.50 # Average gap between requests
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.branchPred.lookups 14656582 # Number of BP lookups
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system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 51396633 # DTB read hits
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system.cpu.dtb.read_misses 64067 # DTB read misses
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system.cpu.dtb.write_hits 11699653 # DTB write hits
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system.cpu.dtb.write_misses 15746 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 51460700 # DTB read accesses
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system.cpu.dtb.write_accesses 11715399 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 63096286 # DTB hits
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system.cpu.dtb.misses 79813 # DTB misses
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system.cpu.dtb.accesses 63176099 # DTB accesses
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system.cpu.itb.inst_hits 12325480 # ITB inst hits
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system.cpu.itb.inst_misses 11172 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 2484 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 12336652 # ITB inst accesses
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system.cpu.itb.hits 12325480 # DTB hits
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system.cpu.itb.misses 11172 # DTB misses
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system.cpu.itb.accesses 12336652 # DTB accesses
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system.cpu.numCycles 471810648 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued
|
|
system.cpu.iq.rate 0.263438 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 221429 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 11545908 # Number of branches executed
|
|
system.cpu.iew.exec_stores 12211356 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.257527 # Inst execution rate
|
|
system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 47220023 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 60458083 # Number of instructions committed
|
|
system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27386631 # Number of memory references committed
|
|
system.cpu.commit.loads 15654552 # Number of loads committed
|
|
system.cpu.commit.membars 403601 # Number of memory barriers committed
|
|
system.cpu.commit.branches 9961338 # Number of branches committed
|
|
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 68854854 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 991262 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 242306963 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 201917005 # The number of ROB writes
|
|
system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 60307702 # Number of Instructions Simulated
|
|
system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 550141263 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 88418139 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 8398 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2928 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 831893 # number of misc regfile writes
|
|
system.cpu.icache.replacements 979850 # number of replacements
|
|
system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 11261998 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1059902 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79506 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 79506 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 79506 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 79506 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 79506 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 79506 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980396 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 980396 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 980396 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 980396 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 980396 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 980396 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379943495 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11379943495 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379943495 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11379943495 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379943495 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11379943495 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079565 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.079565 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.079565 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11607.496864 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11607.496864 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 64334 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 51346.876619 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1884630 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 129728 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 14.527550 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 2498196259500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 36934.415864 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.547842 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003890 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 8157.503084 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6228.405939 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.563574 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.124474 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.095038 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.783491 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52007 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10206 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 966908 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 387081 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1416202 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 607769 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 607769 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 112939 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 112939 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 52007 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 10206 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 966908 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 500020 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1529141 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 52007 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 10206 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 966908 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 500020 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1529141 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12331 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 23084 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12331 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143895 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 156270 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12331 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143895 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 156270 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2874000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 694978000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 630766499 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1328805499 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 455500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732631500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6732631500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2874000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 694978000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7363397999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8061436999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2874000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 694978000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7363397999 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8061436999 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52048 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10209 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 979239 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 397790 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1439286 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 607769 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 607769 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246125 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 246125 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52048 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10209 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 979239 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 643915 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1685411 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52048 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10209 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 979239 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 643915 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1685411 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000788 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000294 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012592 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026921 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.016039 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986815 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986815 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541132 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541132 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000788 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000294 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012592 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223469 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.092719 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000788 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000294 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012592 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223469 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.092719 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70097.560976 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56360.230314 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58900.597535 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57563.918688 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 156.046591 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 156.046591 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50550.594657 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50550.594657 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51586.593710 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51586.593710 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 59106 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 59106 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12319 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10648 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 23011 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2919 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2919 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12319 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143834 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 156197 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12319 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143834 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 156197 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2360290 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541016289 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 495761741 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1039287822 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29192919 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29192919 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072671631 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072671631 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2360290 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541016289 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5568433372 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6111959453 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2360290 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541016289 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5568433372 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6111959453 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002461767 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007542597 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26898020017 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26898020017 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541132 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541132 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092676 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092676 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43917.224531 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45164.826474 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38087.123504 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38087.123504 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 643403 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 21507300 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 643915 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 33.400837 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13753934 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13753934 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 7259500 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 7259500 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 243166 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 243166 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247603 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247603 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 21013434 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 21013434 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 21013434 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 21013434 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 737092 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 737092 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2962848 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2962848 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13493 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 13493 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3699940 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3699940 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3699940 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3699940 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9782888500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9782888500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104355801234 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 104355801234 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 179982000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 179982000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 114138689734 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 114138689734 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 114138689734 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 114138689734 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 14491026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 14491026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10222348 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10222348 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256659 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 256659 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 607769 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|