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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
Andreas Hansson 08f7a8bc00 stats: Update stats to reflect bus retry changes 
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
2013-03-26 14:46:49 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.541275 # Number of seconds simulated
sim_ticks 2541275479000 # Number of ticks simulated
final_tick 2541275479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 58368 # Simulator instruction rate (inst/s)
host_op_rate 75104 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2459458086 # Simulator tick rate (ticks/s)
host_mem_usage 437960 # Number of bytes of host memory used
host_seconds 1033.27 # Real time elapsed on the host
sim_insts 60310144 # Number of instructions simulated
sim_ops 77602537 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 503040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4153104 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 296576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4940508 # Number of bytes read from this memory
system.physmem.bytes_read::total 131006444 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 503040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 296576 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 799616 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3785600 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1346056 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1670056 # Number of bytes written to this memory
system.physmem.bytes_written::total 6801712 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 7860 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 64926 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4634 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 77202 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293480 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59150 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 336514 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 417514 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47657379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 730 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 197948 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1634260 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 116704 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1944106 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51551453 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 197948 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 116704 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314651 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1489646 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 529677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 657172 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2676495 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1489646 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47657379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 730 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 197948 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2163937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 116704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2601278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54227949 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293480 # Total number of read requests seen
system.physmem.writeReqs 813178 # Total number of write requests seen
system.physmem.cpureqs 218453 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 978782720 # Total number of bytes read from memory
system.physmem.bytesWritten 52043392 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131006444 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6801712 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4682 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 955733 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955667 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 956482 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 955442 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 956164 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956098 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955607 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955922 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956025 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 955322 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50413 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50428 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50859 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51371 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50904 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50728 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51236 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 32469 # Number of times wr buffer was full causing retry
system.physmem.totGap 2541274319500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 43 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 154621 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754028 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 59150 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1054746 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 991862 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 961693 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3604884 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2718217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2723048 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2699101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 60161 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 110020 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 160431 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 109941 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 10084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 9995 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 10658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 9166 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2881 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2936 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2935 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2930 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 32754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 32637 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 32503 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 32484 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32475 # What write queue length does an incoming req see
system.physmem.totQLat 346695398500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 439867444750 # Sum of mem lat for all requests
system.physmem.totBusLat 76467350000 # Total cycles spent in databus access
system.physmem.totBankLat 16704696250 # Total cycles spent in bank access
system.physmem.avgQLat 22669.51 # Average queueing delay per request
system.physmem.avgBankLat 1092.28 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 28761.78 # Average memory access latency
system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
system.physmem.avgWrQLen 1.12 # Average write queue length over time
system.physmem.readRowHits 15218335 # Number of row buffer hits during reads
system.physmem.writeRowHits 794661 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes
system.physmem.avgGap 157777.88 # Average gap between requests
system.l2c.replacements 64389 # number of replacements
system.l2c.tagsinuse 51396.917216 # Cycle average of tags in use
system.l2c.total_refs 1903765 # Total number of references to valid blocks.
system.l2c.sampled_refs 129779 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.669284 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2505294633000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36944.332930 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 18.025643 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 5127.291089 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3277.380324 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 9.553076 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 3076.231813 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2944.101992 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563726 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000275 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.078236 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.050009 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000146 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.046940 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.044923 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784255 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 32015 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 7355 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 491964 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 214249 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 30395 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6870 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 478610 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 173362 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1434820 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608422 # number of Writeback hits
system.l2c.Writeback_hits::total 608422 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57870 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 55015 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112885 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 32015 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 7355 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 491964 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 272119 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 30395 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6870 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 478610 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 228377 # number of demand (read+write) hits
system.l2c.demand_hits::total 1547705 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 32015 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 7355 # number of overall hits
system.l2c.overall_hits::cpu0.inst 491964 # number of overall hits
system.l2c.overall_hits::cpu0.data 272119 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 30395 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6870 # number of overall hits
system.l2c.overall_hits::cpu1.inst 478610 # number of overall hits
system.l2c.overall_hits::cpu1.data 228377 # number of overall hits
system.l2c.overall_hits::total 1547705 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7751 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6089 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 4640 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4614 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23136 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1537 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1371 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 59818 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 73396 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133214 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7751 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 65907 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 4640 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 78010 # number of demand (read+write) misses
system.l2c.demand_misses::total 156350 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
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system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027462 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025807 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015817 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988424 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990607 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.989452 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508276 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571571 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.541302 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091708 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091708 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44222.681044 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46327.958415 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 44435.697238 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10055.671772 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.775447 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39592.848256 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37458.838234 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38417.087453 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 7621777 # Number of BP lookups
system.cpu0.branchPred.condPredicted 6075515 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 381764 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4964344 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4051622 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 81.614449 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 732539 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 39625 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 26065013 # DTB read hits
system.cpu0.dtb.read_misses 39990 # DTB read misses
system.cpu0.dtb.write_hits 5895229 # DTB write hits
system.cpu0.dtb.write_misses 9395 # DTB write misses
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5652 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1415 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 26105003 # DTB read accesses
system.cpu0.dtb.write_accesses 5904624 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 31960242 # DTB hits
system.cpu0.dtb.misses 49385 # DTB misses
system.cpu0.dtb.accesses 32009627 # DTB accesses
system.cpu0.itb.inst_hits 6121620 # ITB inst hits
system.cpu0.itb.inst_misses 7590 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2650 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1597 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 6129210 # ITB inst accesses
system.cpu0.itb.hits 6121620 # DTB hits
system.cpu0.itb.misses 7590 # DTB misses
system.cpu0.itb.accesses 6129210 # DTB accesses
system.cpu0.numCycles 238950356 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 15511561 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 47861098 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 7621777 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4784161 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 10616760 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2562446 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 93609 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 49488171 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 1734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 1985 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 51736 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 101083 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6119617 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 397619 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3186 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 77638963 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.762623 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.119947 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 67029800 86.34% 86.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 691008 0.89% 87.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 886701 1.14% 88.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1229558 1.58% 89.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1143059 1.47% 91.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 577576 0.74% 92.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1327799 1.71% 93.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 398469 0.51% 94.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4354993 5.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 77638963 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.031897 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.200297 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 16561693 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 49223207 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9616319 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 551624 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1684026 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1027423 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 90511 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 56351612 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 302709 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1684026 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 17495833 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 18963913 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 27008828 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9162852 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3321475 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 53533397 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 13490 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 620965 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2156088 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 544 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 55691405 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 243710313 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 243662711 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 47602 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 40470990 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 15220415 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 429980 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 381705 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6754845 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 10370790 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6781090 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1064335 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1313359 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 49665444 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1039347 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 63215993 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 96269 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10485149 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 26517521 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 261916 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 77638963 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.814230 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 54786055 70.57% 70.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 7213649 9.29% 79.86% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3700645 4.77% 84.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3137751 4.04% 88.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6288496 8.10% 96.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1404757 1.81% 98.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 809185 1.04% 99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 232478 0.30% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 65947 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 77638963 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 29964 0.67% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 4 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4227609 94.71% 95.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 206392 4.62% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 195815 0.31% 0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 29964622 47.40% 47.71% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 46968 0.07% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 26783752 42.37% 90.16% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 6223613 9.84% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 63215993 # Type of FU issued
system.cpu0.iq.rate 0.264557 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4463969 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.070615 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 208668164 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 61198847 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 44188793 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12222 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6485 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5502 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 67477689 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6458 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 323157 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2276582 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3606 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 15957 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 887836 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 17155494 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 367481 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1684026 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14200734 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 233893 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 50821833 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 107458 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 10370790 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6781090 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 738100 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 56554 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 3388 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 15957 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 188011 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 147687 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 335698 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 62040059 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 26425172 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1175934 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 117042 # number of nop insts executed
system.cpu0.iew.exec_refs 32592128 # number of memory reference insts executed
system.cpu0.iew.exec_branches 6029174 # Number of branches executed
system.cpu0.iew.exec_stores 6166956 # Number of stores executed
system.cpu0.iew.exec_rate 0.259636 # Inst execution rate
system.cpu0.iew.wb_sent 61509785 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 44194295 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 24341972 # num instructions producing a value
system.cpu0.iew.wb_consumers 44715542 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.184952 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.544374 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 10343604 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 777431 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 292475 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 75954937 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.526454 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.509299 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 61716542 81.25% 81.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6915967 9.11% 90.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2042261 2.69% 93.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1137231 1.50% 94.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1037452 1.37% 95.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 547322 0.72% 96.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 703732 0.93% 97.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 369670 0.49% 98.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1484760 1.95% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 75954937 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 31329293 # Number of instructions committed
system.cpu0.commit.committedOps 39986762 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 13987462 # Number of memory references committed
system.cpu0.commit.loads 8094208 # Number of loads committed
system.cpu0.commit.membars 212609 # Number of memory barriers committed
system.cpu0.commit.branches 5213704 # Number of branches committed
system.cpu0.commit.fp_insts 5481 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 35328328 # Number of committed integer instructions.
system.cpu0.commit.function_calls 514863 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1484760 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 123824951 # The number of ROB reads
system.cpu0.rob.rob_writes 102387078 # The number of ROB writes
system.cpu0.timesIdled 884056 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 161311393 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2289794473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 31249850 # Number of Instructions Simulated
system.cpu0.committedOps 39907319 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 31249850 # Number of Instructions Simulated
system.cpu0.cpi 7.646448 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 7.646448 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.130780 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.130780 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 280856495 # number of integer regfile reads
system.cpu0.int_regfile_writes 45466199 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22714 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19802 # number of floating regfile writes
system.cpu0.misc_regfile_reads 15537514 # number of misc regfile reads
system.cpu0.misc_regfile_writes 430329 # number of misc regfile writes
system.cpu0.icache.replacements 983581 # number of replacements
system.cpu0.icache.tagsinuse 511.609112 # Cycle average of tags in use
system.cpu0.icache.total_refs 11036717 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 984093 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 11.215116 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 356.975852 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 154.633260 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.697218 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.302018 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999237 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5578101 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5458616 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 11036717 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5578101 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5458616 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 11036717 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5578101 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5458616 # number of overall hits
system.cpu0.icache.overall_hits::total 11036717 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 541391 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 523221 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1064612 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 541391 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 523221 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1064612 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 541391 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 523221 # number of overall misses
system.cpu0.icache.overall_misses::total 1064612 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7337521992 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6947086995 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14284608987 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7337521992 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 6947086995 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14284608987 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7337521992 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 6947086995 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14284608987 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6119492 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981837 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 12101329 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6119492 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 5981837 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 12101329 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6119492 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 5981837 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 12101329 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088470 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087468 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.087975 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088470 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087468 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.087975 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088470 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087468 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.087975 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13553.091928 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13277.538545 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13417.666706 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13417.666706 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13417.666706 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4893 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.100865 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41083 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39415 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 80498 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 41083 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39415 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 80498 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 41083 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39415 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 80498 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 500308 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 483806 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 984114 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 500308 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 483806 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 984114 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 500308 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 483806 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 984114 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5984214993 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5663833496 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648048489 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5984214993 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5663833496 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11648048489 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5984214993 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5663833496 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11648048489 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081323 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.081323 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.081323 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11836.076399 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 643901 # number of replacements
system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use
system.cpu0.dcache.total_refs 21533518 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 644413 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 33.415710 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 318.189291 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 193.803424 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.621463 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.378522 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7127084 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6650362 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13777446 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3774490 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3487348 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 7261838 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125952 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117576 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243528 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127946 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119673 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247619 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10901574 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10137710 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21039284 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10901574 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10137710 # number of overall hits
system.cpu0.dcache.overall_hits::total 21039284 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 437179 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 313532 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 750711 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1386171 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1574804 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2960975 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6802 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6759 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1823350 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1888336 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3711686 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1823350 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1888336 # number of overall misses
system.cpu0.dcache.overall_misses::total 3711686 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6487702500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4845715000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11333417500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52314948357 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62070901782 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114385850139 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91825500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94465000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 186290500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 155000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 58802650857 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 66916616782 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125719267639 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 58802650857 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 66916616782 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125719267639 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7564263 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6963894 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14528157 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5160661 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5062152 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10222813 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132754 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124335 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 257089 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127952 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119678 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247630 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12724924 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12026046 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24750970 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12724924 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12026046 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24750970 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057795 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045023 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051673 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268603 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.311094 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289644 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051238 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054361 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052748 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000047 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143290 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.157021 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149961 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143290 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.157021 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149961 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14839.922549 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15455.248587 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15096.911461 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37740.616675 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39415.001347 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38631.143505 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13499.779477 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13976.179908 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13737.224393 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14090.909091 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33871.202370 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33871.202370 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 36391 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 16051 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3543 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 264 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.271239 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 60.799242 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 608422 # number of writebacks
system.cpu0.dcache.writebacks::total 608422 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 222914 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 141593 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 364507 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1266986 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1445051 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2712037 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 671 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 680 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489900 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1586644 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3076544 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489900 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1586644 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3076544 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 214265 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171939 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 386204 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119185 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129753 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6131 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6079 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12210 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 333450 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 301692 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 333450 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 301692 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2906449500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2315533500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5221983000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3953585991 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4507381433 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460967424 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71518000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74200000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145718000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6860035491 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6822914933 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13682950424 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6860035491 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6822914933 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13682950424 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91872733500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90487640000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182360373500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14914514407 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18644008670 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33558523077 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106787247907 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109131648670 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215918896577 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028326 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024690 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023095 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025632 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046183 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048892 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047493 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025661 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025661 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13564.742258 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13467.180221 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.307392 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33171.842019 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34738.167387 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33988.251790 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.981243 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.954927 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11934.316134 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 7016100 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5626613 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 342958 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4632911 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3801004 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 82.043536 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 670740 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 35021 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 25297638 # DTB read hits
system.cpu1.dtb.read_misses 36209 # DTB read misses
system.cpu1.dtb.write_hits 5817747 # DTB write hits
system.cpu1.dtb.write_misses 9250 # DTB write misses
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 5517 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1319 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 648 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25333847 # DTB read accesses
system.cpu1.dtb.write_accesses 5826997 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 31115385 # DTB hits
system.cpu1.dtb.misses 45459 # DTB misses
system.cpu1.dtb.accesses 31160844 # DTB accesses
system.cpu1.itb.inst_hits 5983825 # ITB inst hits
system.cpu1.itb.inst_misses 6876 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 1422 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 5990701 # ITB inst accesses
system.cpu1.itb.hits 5983825 # DTB hits
system.cpu1.itb.misses 6876 # DTB misses
system.cpu1.itb.accesses 5990701 # DTB accesses
system.cpu1.numCycles 234271094 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 15106075 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 46495215 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7016100 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4471744 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10263244 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2607774 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 83065 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 47539930 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 2033 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 42850 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 94637 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 151 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 5981839 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 442153 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2974 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 74917861 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.771750 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.136158 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 64662198 86.31% 86.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 618220 0.83% 87.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 830780 1.11% 88.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1202992 1.61% 89.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1054171 1.41% 91.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 533923 0.71% 91.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1365534 1.82% 93.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 350745 0.47% 94.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4299298 5.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 74917861 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.029949 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.198468 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 16114785 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 47334136 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9307437 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 457642 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1701687 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 943149 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 85752 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 54765911 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 286536 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1701687 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17049791 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 18574833 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 25739106 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8750674 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3099680 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 51604165 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 7083 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 481938 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2120083 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 47 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 53629483 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 236928405 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 236886159 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 42246 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 37922365 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 15707117 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 402858 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 356707 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6241200 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 9820106 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6689053 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 876297 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1123238 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 47543883 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 946480 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 60738625 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 81609 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10509389 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 27830287 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 241377 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 74917861 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.810736 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.521004 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 53210773 71.03% 71.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6641164 8.86% 79.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3529295 4.71% 84.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 2876551 3.84% 88.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6221124 8.30% 96.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1436861 1.92% 98.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 733077 0.98% 99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 210173 0.28% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 58843 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 74917861 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 24144 0.55% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4145479 94.86% 95.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 200357 4.58% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 167851 0.28% 0.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 28384328 46.73% 47.01% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 46613 0.08% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 903 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26029174 42.85% 89.94% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6109728 10.06% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 60738625 # Type of FU issued
system.cpu1.iq.rate 0.259266 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4369980 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.071947 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 200881299 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 59008077 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 41690782 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 10661 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 5857 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 4774 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 64935130 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 5624 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 302237 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2258994 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3096 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 14702 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 849711 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 16948413 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 457547 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1701687 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 13992381 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 229468 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 48596033 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 98735 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 9820106 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6689053 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 673721 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 49557 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 3683 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 14702 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 165794 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 132525 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 298319 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 59364884 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 25624684 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1373741 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 105670 # number of nop insts executed
system.cpu1.iew.exec_refs 31682928 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5509079 # Number of branches executed
system.cpu1.iew.exec_stores 6058244 # Number of stores executed
system.cpu1.iew.exec_rate 0.253403 # Inst execution rate
system.cpu1.iew.wb_sent 58786539 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 41695556 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 22722145 # num instructions producing a value
system.cpu1.iew.wb_consumers 41696703 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.177980 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.544939 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 10421777 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 705103 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 258416 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 73216174 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.515817 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.496135 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 59718106 81.56% 81.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 6653283 9.09% 90.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1904372 2.60% 93.25% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1008936 1.38% 94.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 956792 1.31% 95.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 521917 0.71% 96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 703785 0.96% 97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 374006 0.51% 98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1374977 1.88% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 73216174 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 29131232 # Number of instructions committed
system.cpu1.commit.committedOps 37766156 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 13400454 # Number of memory references committed
system.cpu1.commit.loads 7561112 # Number of loads committed
system.cpu1.commit.membars 191037 # Number of memory barriers committed
system.cpu1.commit.branches 4747981 # Number of branches committed
system.cpu1.commit.fp_insts 4731 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 33529515 # Number of committed integer instructions.
system.cpu1.commit.function_calls 476457 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1374977 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 119155388 # The number of ROB reads
system.cpu1.rob.rob_writes 98129561 # The number of ROB writes
system.cpu1.timesIdled 872896 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 159353233 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2285655752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 29060294 # Number of Instructions Simulated
system.cpu1.committedOps 37695218 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 29060294 # Number of Instructions Simulated
system.cpu1.cpi 8.061553 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 8.061553 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.124046 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.124046 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 268946784 # number of integer regfile reads
system.cpu1.int_regfile_writes 42787312 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22150 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19734 # number of floating regfile writes
system.cpu1.misc_regfile_reads 14724221 # number of misc regfile reads
system.cpu1.misc_regfile_writes 402169 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1192686110607 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1192686110607 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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