stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
This commit is contained in:
Andreas Hansson
parent
c4898b15bc
commit
fce3433b2e
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -1,80 +1,80 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.204982 # Number of seconds simulated
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sim_ticks 5204982293000 # Number of ticks simulated
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final_tick 5204982293000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 5.204983 # Number of seconds simulated
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sim_ticks 5204982530500 # Number of ticks simulated
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final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 233342 # Simulator instruction rate (inst/s)
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host_op_rate 447673 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 11247967547 # Simulator tick rate (ticks/s)
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host_mem_usage 849540 # Number of bytes of host memory used
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host_seconds 462.75 # Real time elapsed on the host
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sim_insts 107978732 # Number of instructions simulated
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sim_ops 207159910 # Number of ops (including micro ops) simulated
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host_inst_rate 181134 # Simulator instruction rate (inst/s)
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host_op_rate 347511 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 8731335326 # Simulator tick rate (ticks/s)
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host_mem_usage 804468 # Number of bytes of host memory used
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host_seconds 596.13 # Real time elapsed on the host
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sim_insts 107979054 # Number of instructions simulated
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sim_ops 207160582 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 864448872 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 69078677 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 864449224 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 69078733 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 160958728 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 27339153 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1122193510 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 864448872 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 160958728 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1025407600 # Number of instructions bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 160961632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 27339818 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1122197487 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 864449224 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 160961632 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1025410856 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 21309608 # Number of bytes written to this memory
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system.physmem.bytes_written::total 72643471 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 21309908 # Number of bytes written to this memory
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system.physmem.bytes_written::total 72643771 # Number of bytes written to this memory
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system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 108056109 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 12053051 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 108056153 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 12053065 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 20119841 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 4057514 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 144328941 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 20120204 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 4057615 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 144329463 # Number of read requests responded to by this memory
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system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 2934421 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 10106666 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 2934464 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 10106709 # Number of write requests responded to by this memory
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system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 166081040 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 13271645 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 166081100 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 13271655 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 30923972 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 5252497 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 215599871 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 166081040 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 30923972 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 197005012 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 30924529 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 5252624 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 215600625 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 166081100 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 30924529 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 197005629 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 4094079 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 13956526 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 4094136 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 13956583 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 166081040 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 22559427 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 166081100 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 22559437 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 30923972 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 9346576 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 229556397 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 30924529 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 9346761 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 229557208 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 810 # Total number of read requests seen
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system.physmem.writeReqs 46736 # Total number of write requests seen
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system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady
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system.physmem.cpureqs 48918 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 51840 # Total number of bytes read from memory
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system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize()
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@ -82,40 +82,40 @@ system.physmem.bytesConsumedWr 2991104 # by
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 298 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 298 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 96 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 144 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 2944 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 3168 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 3232 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 3264 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 3120 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 2992 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 2960 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 3096 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 2768 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 2640 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 2736 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 2640 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 2560 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 2768 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 2992 # Track writes on a per bank basis
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system.physmem.perBankRdReqs::14 96 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 48 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 2952 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 2848 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 3008 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 2928 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 2928 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 2944 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 3056 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 2944 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 2848 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 2912 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 2848 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 2704 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 3048 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 3040 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 63181906000 # Total gap between requests
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system.physmem.numWrRetry 1670 # Number of times wr buffer was full causing retry
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system.physmem.totGap 63182142000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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@ -131,7 +131,7 @@ system.physmem.writePktSize::2 0 # ca
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 46736 # categorize write packet sizes
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system.physmem.writePktSize::6 48406 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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@ -176,15 +176,15 @@ system.physmem.rdQLenPdf::29 2 # Wh
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system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1995 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1995 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1996 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1996 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1999 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
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@ -199,37 +199,37 @@ system.physmem.wrQLenPdf::19 2032 # Wh
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system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 61 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 37 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 36 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 34586744 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 44980744 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 3240000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7154000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42699.68 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 8832.10 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 55531.78 # Average memory access latency
|
||||
system.physmem.totQLat 40946729 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 4050000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7548750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 50551.52 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 9319.44 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 64870.96 # Average memory access latency
|
||||
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.15 # Average write queue length over time
|
||||
system.physmem.readRowHits 716 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 45919 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 88.40 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 98.25 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1328858.49 # Average gap between requests
|
||||
system.physmem.readRowHits 696 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 45224 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1328863.46 # Average gap between requests
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -290,50 +290,50 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.numCycles 10407785201 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 10407785676 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 92551705 # Number of instructions committed
|
||||
system.cpu0.committedOps 178518504 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 168457719 # Number of integer alu accesses
|
||||
system.cpu0.committedInsts 92551747 # Number of instructions committed
|
||||
system.cpu0.committedOps 178518572 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 168457773 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 16414006 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 168457719 # number of integer instructions
|
||||
system.cpu0.num_conditional_control_insts 16414014 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 168457773 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 0 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 415888508 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 210334532 # number of times the integer registers were written
|
||||
system.cpu0.num_int_register_reads 415888554 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 210334552 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 20039545 # number of memory refs
|
||||
system.cpu0.num_load_insts 12899818 # Number of load instructions
|
||||
system.cpu0.num_mem_refs 20039559 # number of memory refs
|
||||
system.cpu0.num_load_insts 12899832 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7139727 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 9669886063.125444 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 737899137.874556 # Number of busy cycles
|
||||
system.cpu0.num_idle_cycles 9669887298.959074 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 737898377.040926 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.numCycles 10409964586 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 10409965061 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 15427027 # Number of instructions committed
|
||||
system.cpu1.committedOps 28641406 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 28123113 # Number of integer alu accesses
|
||||
system.cpu1.committedInsts 15427307 # Number of instructions committed
|
||||
system.cpu1.committedOps 28642010 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 28123688 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 1978272 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 28123113 # number of integer instructions
|
||||
system.cpu1.num_conditional_control_insts 1978312 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 28123688 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 0 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 73027794 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 31865306 # number of times the integer registers were written
|
||||
system.cpu1.num_int_register_reads 73029248 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 31865943 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 7025055 # number of memory refs
|
||||
system.cpu1.num_load_insts 4066664 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2958391 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10280021112.934025 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 129943473.065975 # Number of busy cycles
|
||||
system.cpu1.num_mem_refs 7025199 # number of memory refs
|
||||
system.cpu1.num_load_insts 4066765 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2958434 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10280018133.934025 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 129946927.065975 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.269661 # Number of seconds simulated
|
||||
sim_ticks 269661304500 # Number of ticks simulated
|
||||
final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.269672 # Number of seconds simulated
|
||||
sim_ticks 269671683500 # Number of ticks simulated
|
||||
final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 98682 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 98682 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44214559 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273520 # Number of bytes of host memory used
|
||||
host_seconds 6098.93 # Real time elapsed on the host
|
||||
host_inst_rate 125294 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 125294 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56139844 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224468 # Number of bytes of host memory used
|
||||
host_seconds 4803.57 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu
|
|||
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 26294 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1014 # Total number of write requests seen
|
||||
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by
|
|||
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 269661252500 # Total gap between requests
|
||||
system.physmem.totGap 269671631500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
|
||||
|
|
@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh
|
|||
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
|
|
@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 364261179 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 105120000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 554778000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 13860.78 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 21110.27 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 38971.05 # Average memory access latency
|
||||
system.physmem.totQLat 384531397 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 131400000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 580703750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 14632.09 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 22096.79 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 41728.89 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.04 # Data bus utilization in percentage
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 12.19 # Average write queue length over time
|
||||
system.physmem.readRowHits 17406 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9874807.84 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 86405274 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted
|
||||
system.physmem.readRowHits 16315 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 296 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9875187.91 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 86405403 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114517568 # DTB read hits
|
||||
system.cpu.dtb.read_hits 114517881 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114520199 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453362 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 114520512 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453501 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39455664 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153970930 # DTB hits
|
||||
system.cpu.dtb.write_accesses 39455803 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153971382 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 153975863 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 24997854 # ITB hits
|
||||
system.cpu.dtb.data_accesses 153976315 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 24997849 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 24997876 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 24997871 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -234,18 +234,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 539322610 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 539343368 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 154928367 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -256,12 +256,12 @@ system.cpu.execution_unit.executions 412128439 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.582759 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.579328 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
|
|
@ -273,77 +273,77 @@ system.cpu.committedInsts 601856964 # Nu
|
|||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 30 # number of replacements
|
||||
system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24996820 # number of overall hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24996815 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1034 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -359,38 +359,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 855
|
|||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1042 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
|
||||
|
|
@ -415,17 +415,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -450,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -482,17 +482,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -504,51 +504,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786016 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179347 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles
|
||||
system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786159 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179204 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -557,40 +557,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 #
|
|||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
|
|
@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.139847 # Number of seconds simulated
|
||||
sim_ticks 139846906500 # Number of ticks simulated
|
||||
final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.139855 # Number of seconds simulated
|
||||
sim_ticks 139855372500 # Number of ticks simulated
|
||||
final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 94955 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 94955 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33309069 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278532 # Number of bytes of host memory used
|
||||
host_seconds 4198.46 # Real time elapsed on the host
|
||||
host_inst_rate 164436 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164436 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57685897 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230388 # Number of bytes of host memory used
|
||||
host_seconds 2424.43 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 468992 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 139846854500 # Total gap between requests
|
||||
system.physmem.totGap 139855320500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 39390791 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 29312000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 105924000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5375.38 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14454.69 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 23830.08 # Average memory access latency
|
||||
system.physmem.totQLat 47661305 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 113038750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6504.00 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15425.59 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26929.59 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 6444 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6132 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 19083904.82 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 53489670 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685393 # Number of conditional branches predicted
|
||||
system.physmem.avgGap 19085060.11 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 53489671 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754613 # DTB read hits
|
||||
system.cpu.dtb.read_hits 94754610 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754634 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521103 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 94754631 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521101 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73521138 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275716 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73521136 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275711 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275772 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611354 # ITB hits
|
||||
system.cpu.dtb.data_accesses 168275767 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611339 # ITB hits
|
||||
system.cpu.itb.fetch_misses 44520 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 48655874 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 48655859 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 279693814 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 279710746 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 205475782 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.213631 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.207865 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -266,124 +266,124 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606847 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4507 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4507 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4507 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4507 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4507 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 195448500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 195448500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 195448500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 195448500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 195448500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 195448500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611354 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611354 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611354 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611354 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606831 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4508 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 67.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 170297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 170297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170297500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 170297500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43632.462209 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43632.462209 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3907.773744 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.670185 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2909.388487 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.715072 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088787 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119256 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
||||
|
|
@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160908500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45014500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 205923000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151967500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 151967500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 160908500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 196982000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 357890500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 160908500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 196982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 357890500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48838.769105 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48838.769105 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118404553 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34670717 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153075270 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112966799 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112966799 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118404553 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147637516 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 266042069 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118404553 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147637516 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 266042069 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254423 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20795 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254397 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20821 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -556,32 +556,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000124
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
|
|
@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,90 +1,90 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.043266 # Number of seconds simulated
|
||||
sim_ticks 43266024500 # Number of ticks simulated
|
||||
final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.042726 # Number of seconds simulated
|
||||
sim_ticks 42726055500 # Number of ticks simulated
|
||||
final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 92573 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 92573 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45339086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308556 # Number of bytes of host memory used
|
||||
host_seconds 954.28 # Real time elapsed on the host
|
||||
host_inst_rate 156388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 156388 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75637274 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259292 # Number of bytes of host memory used
|
||||
host_seconds 564.88 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165517 # Total number of read requests seen
|
||||
system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165519 # Total number of read requests seen
|
||||
system.physmem.writeReqs 113997 # Total number of write requests seen
|
||||
system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 10593088 # Total number of bytes read from memory
|
||||
system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 10593216 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 6949 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 7300 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 7039 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 7210 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 6879 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 7379 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 7080 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 7117 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 7374 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 43266004500 # Total gap between requests
|
||||
system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 42726035000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165517 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165519 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
|
|
@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca
|
|||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 113997 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 114011 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
|
|
@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
|
||||
|
|
@ -161,45 +161,45 @@ system.physmem.wrQLenPdf::19 4956 # Wh
|
|||
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 662068000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1734068000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 56247.27 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10476.68 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 70723.94 # Average memory access latency
|
||||
system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 2.58 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.27 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.35 # Average write queue length over time
|
||||
system.physmem.readRowHits 151965 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 41713 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 154790.12 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 18742312 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12317439 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4774431 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 15498318 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 4661486 # Number of BTB hits
|
||||
system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 827595000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1765926250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42615.22 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10669.02 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 58284.24 # Average memory access latency
|
||||
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 3.27 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.23 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.42 # Average write queue length over time
|
||||
system.physmem.readRowHits 148856 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 71620 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 152857.21 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 18742591 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 30.077367 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1660962 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -209,18 +209,18 @@ system.cpu.dtb.read_hits 20277550 # DT
|
|||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20367698 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14728696 # DTB write hits
|
||||
system.cpu.dtb.write_hits 14728779 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14735948 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006246 # DTB hits
|
||||
system.cpu.dtb.write_accesses 14736031 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006329 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35103646 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12367278 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11044 # ITB misses
|
||||
system.cpu.dtb.data_accesses 35103729 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12368275 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11063 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 12378322 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 12379338 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 86532050 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 85452112 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35060577 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35060657 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 80.401850 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 81.422683 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
||||
system.cpu.comStores 14613377 # Number of Store instructions committed
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
|
|
@ -273,194 +273,194 @@ system.cpu.committedInsts 88340673 # Nu
|
|||
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 84282 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 84308 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12250113 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12250113 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12250113 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117156 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117156 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117156 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117156 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117156 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117156 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1822166500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1822166500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12251160 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117106 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 131593 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30981.522130 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 151339 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163652 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.924761 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 131595 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30966.013927 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27280.254395 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2018.521657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1682.746078 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.832527 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27281.106507 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2018.513793 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1666.393626 # Average occupied blocks per requestor
|
||||
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|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051353 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79223 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945008 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79247 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33054 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 112277 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 112301 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168350 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168350 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 79223 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 79247 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45933 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 125156 # number of demand (read+write) hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 7105 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 7107 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 165517 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7105 # number of overall misses
|
||||
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|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165517 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 397918500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1540033500 # number of ReadReq miss cycles
|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 14268456500 # number of ReadExReq miss cycles
|
||||
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|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15808490000 # number of demand (read+write) miss cycles
|
||||
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|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 397918500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15808490000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 16206408500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::total 165519 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454675000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513576000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1968251000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996247000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 11996247000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 454675000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13509823000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13964498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 454675000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13509823000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13964498000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 86328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 86354 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 290673 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 86328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 290699 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 86354 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 290673 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082302 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 290699 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082301 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.235707 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.235678 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082302 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.569427 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082302 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569427 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56005.418719 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55958.486247 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55968.116444 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109010.218426 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109010.218426 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 97913.860812 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 97913.860812 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -471,84 +471,84 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7105 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses
|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7105 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165517 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7105 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165517 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307703601 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1187367459 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1495071060 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12647339647 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12647339647 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307703601 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13834707106 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14142410707 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307703601 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13834707106 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14142410707 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235707 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569427 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43308.036735 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43144.052142 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43177.700572 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96624.975338 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96624.975338 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200249 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33754882 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574731 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574731 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33755002 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33755002 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33755002 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33755002 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038646 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038646 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1135013 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1135013 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135013 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135013 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3942448000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3942448000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 91414151500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 91414151500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95356599500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95356599500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95356599500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95356599500 # number of overall miss cycles
|
||||
system.cpu.dcache.avg_refs 165.185750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.188712 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33754882 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135133 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -559,38 +559,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015
|
|||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168350 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
|
|
@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345
|
|||
system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,90 +1,90 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.985090 # Number of seconds simulated
|
||||
sim_ticks 985089830500 # Number of ticks simulated
|
||||
final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.993559 # Number of seconds simulated
|
||||
sim_ticks 993559170500 # Number of ticks simulated
|
||||
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 87940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 87940 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 47603973 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 516412 # Number of bytes of host memory used
|
||||
host_seconds 20693.44 # Real time elapsed on the host
|
||||
host_inst_rate 148425 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 148425 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 81036604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 464668 # Number of bytes of host memory used
|
||||
host_seconds 12260.62 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959687 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1018055 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 125419968 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65155520 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959688 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1018058 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 125420032 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 985089778500 # Total gap between requests
|
||||
system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 993559118500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 1959687 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 1959688 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
|
|
@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca
|
|||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1018055 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1018171 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
|
|
@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
|
||||
|
|
@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44263 # Wh
|
|||
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 7836420000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 57752478000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 10025.42 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29479.01 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 43504.43 # Average memory access latency
|
||||
system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 1.21 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.09 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.28 # Average write queue length over time
|
||||
system.physmem.readRowHits 834572 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 194113 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 330817.71 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 326556831 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252596788 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 138232865 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 218937552 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135479530 # Number of BTB hits
|
||||
system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 58644685000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 18298.46 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29934.41 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 53232.87 # Average memory access latency
|
||||
system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 1.50 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.10 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.46 # Average write queue length over time
|
||||
system.physmem.readRowHits 770935 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 285714 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 333661.47 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 326540496 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 61.880444 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444784566 # DTB read hits
|
||||
system.cpu.dtb.read_hits 444796007 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449681644 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833172 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 449693085 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833351 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162534476 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605617738 # DTB hits
|
||||
system.cpu.dtb.write_accesses 162534655 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605629358 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 612216120 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 231916745 # ITB hits
|
||||
system.cpu.dtb.data_accesses 612227740 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232025962 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 231916767 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 232025984 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 1970179662 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1987118342 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617888959 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617884568 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.773501 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.100703 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 444595663 # Number of Load instructions committed
|
||||
system.cpu.comStores 160728502 # Number of Store instructions committed
|
||||
system.cpu.comBranches 214632552 # Number of Branches instructions committed
|
||||
|
|
@ -273,191 +273,191 @@ system.cpu.committedInsts 1819780127 # Nu
|
|||
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 231915637 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1108 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232024853 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1109 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47313000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47313000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47313000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47313000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47313000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47313000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51094000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51094000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55079.161816 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55079.161816 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59480.791618 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59480.791618 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926956 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30892.708902 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8958711 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1956749 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578365 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 67095700002 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.085957 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 35.170225 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15821.452721 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458865 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.482832 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.942771 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044304 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044304 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693296 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3693296 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108342 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1108342 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7152646 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7152646 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7152646 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7152646 # number of overall hits
|
||||
system.cpu.l2cache.replacements 1926957 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30901.189493 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 67146389752 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.220551 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.907128 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15830.061814 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.943029 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044311 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044311 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693293 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3693293 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108328 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1108328 # number of ReadExReq hits
|
||||
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|
||||
system.cpu.l2cache.demand_hits::total 7152639 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7152639 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7152639 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1177532 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1178391 # number of ReadReq misses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1177530 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1178389 # number of ReadReq misses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_misses::total 781299 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1958828 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1959687 # number of demand (read+write) misses
|
||||
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|
||||
system.cpu.l2cache.demand_misses::total 1959688 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958828 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959687 # number of overall misses
|
||||
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|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76219681500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 76266131500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54834553000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 54834553000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46450000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 131054234500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 131100684500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46450000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 131054234500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 131100684500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50231000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163632000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 83213863000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66179053000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 66179053000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 50231000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 149342685000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 149392916000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50231000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 149342685000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 149392916000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221836 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222695 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3693296 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3693296 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889638 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889638 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3693293 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3693293 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889627 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889627 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111474 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112333 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111468 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112327 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111474 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112333 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111468 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112327 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163051 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413463 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413463 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54074.505239 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64728.331374 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 64720.565160 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70184.095400 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70184.095400 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66898.787664 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66898.787664 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58476.135041 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.488947 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.632538 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84703.875213 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84703.875213 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76233.010561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76233.010561 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -466,86 +466,86 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1018055 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1018058 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177532 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1178391 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177530 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1178389 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781299 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 781299 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958828 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1959687 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958828 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959687 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35585421 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61199276421 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61234861842 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44953209175 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44953209175 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35585421 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106152485596 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 106188071017 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35585421 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106152485596 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 106188071017 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41426.566938 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51972.495373 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51964.807812 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57536.719982 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57536.719982 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107378 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.173275 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593539212 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111474 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.141953 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12614691000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.173275 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268752 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268752 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156270460 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156270460 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593539212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593539212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593539212 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593539212 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326911 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326911 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4458042 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4458042 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11784953 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11784953 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11784953 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11784953 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 160323624500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 160323624500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195351556000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195351556000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 355675180500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 355675180500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 355675180500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 355675180500 # number of overall miss cycles
|
||||
system.cpu.dcache.replacements 9107372 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593512880 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4484380 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4484380 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11811285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11811285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11811285 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11811285 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288165500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 167288165500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 202507086500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 202507086500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 369795252000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 369795252000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -556,54 +556,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165
|
|||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693296 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2568846 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2673479 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2673479 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2673479 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2673479 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222278 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222278 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111474 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111474 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111474 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111474 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144015924000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144015924000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67975303000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 67975303000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693293 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -612,14 +612,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.041615 # Number of seconds simulated
|
||||
sim_ticks 41615049000 # Number of ticks simulated
|
||||
final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.041622 # Number of seconds simulated
|
||||
sim_ticks 41622221000 # Number of ticks simulated
|
||||
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 92405 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 92405 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41842312 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276220 # Number of bytes of host memory used
|
||||
host_seconds 994.57 # Real time elapsed on the host
|
||||
host_inst_rate 156492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 156492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 70874179 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228076 # Number of bytes of host memory used
|
||||
host_seconds 587.27 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 41614997000 # Total gap between requests
|
||||
system.physmem.totGap 41622168000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 17845427 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 19752000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 69230000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3613.90 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14019.85 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 21633.74 # Average memory access latency
|
||||
system.physmem.totQLat 23375922 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 74071250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4733.88 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15000.25 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24734.14 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.06 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 4457 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4243 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 8427500.41 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 13412629 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
|
||||
system.physmem.avgGap 8428952.61 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 13412628 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 7424481 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 50.757716 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 19996253 # DTB read hits
|
||||
system.cpu.dtb.read_hits 19996247 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 19996263 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501863 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 19996257 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501860 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6501886 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498116 # DTB hits
|
||||
system.cpu.dtb.write_accesses 6501883 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498107 # DTB hits
|
||||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498149 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956935 # ITB hits
|
||||
system.cpu.dtb.data_accesses 26498140 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956943 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 9956984 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 9956992 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 83230099 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 83244443 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570549 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146021 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 38521870 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 57404029 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82970167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.841817 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10691 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7636719 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607724 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.826152 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -266,72 +266,72 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65203595 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026504 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.658636 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29370403 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859696 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.711801 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29384711 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.730683 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945572 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.702941 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.730683 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728872 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728872 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945572 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945572 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945572 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945572 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945572 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945572 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11363 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11363 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11363 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11363 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11363 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11363 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 253418000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 253418000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 253418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 253418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 253418000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 253418000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956935 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956935 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956935 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956935 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956935 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956935 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945578 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22302.032914 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22302.032914 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -340,50 +340,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1843 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1843 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1843 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1843 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1843 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1843 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204186500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 204186500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 204186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204186500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 204186500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21448.161765 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21448.161765 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2190.387059 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839462 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.429033 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.118565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055586 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066845 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
|
||||
|
|
@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127130500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21966500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 149097000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79600500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 79600500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 127130500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101567000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 228697500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 127130500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101567000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 228697500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45501.252684 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52053.317536 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46361.007463 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46225.609756 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46225.609756 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 46313.791009 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 46313.791009 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91774816 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16652177 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108426993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58348895 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58348895 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91774816 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75001072 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 166775888 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91774816 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75001072 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 166775888 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97843336 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32847.106657 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39460.135071 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33714.861007 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33884.375726 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33884.375726 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.892023 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488629 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488629 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488625 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8672 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8676 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -550,25 +550,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301
|
|||
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -576,12 +576,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu
|
|||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
|
|
@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -197,7 +197,7 @@ system.physmem.avgRdBW 0.00 # Av
|
|||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -440,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu
|
|||
system.cpu0.num_mem_refs 15124548 # number of memory refs
|
||||
system.cpu0.num_load_insts 9178366 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5946182 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles
|
||||
system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ system.physmem.avgRdBW 0.00 # Av
|
|||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu
|
|||
system.cpu.num_mem_refs 16115688 # number of memory refs
|
||||
system.cpu.num_load_insts 9747503 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies 0 # nu
|
|||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2042707 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -215,7 +215,7 @@ system.physmem.avgRdBW 0.00 # Av
|
|||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@ system.physmem.avgRdBW 0.00 # Av
|
|||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -211,7 +211,7 @@ system.physmem.avgRdBW 0.00 # Av
|
|||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu
|
|||
sim_ticks 5112040970500 # Number of ticks simulated
|
||||
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1071475 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27413112180 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 626876 # Number of bytes of host memory used
|
||||
host_seconds 186.48 # Real time elapsed on the host
|
||||
host_inst_rate 1816388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46471341970 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 582576 # Number of bytes of host memory used
|
||||
host_seconds 110.00 # Real time elapsed on the host
|
||||
sim_insts 199810242 # Number of instructions simulated
|
||||
sim_ops 409125923 # Number of ops (including micro ops) simulated
|
||||
sim_ops 409125913 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
|
|
@ -195,7 +195,7 @@ system.physmem.avgRdBW 0.00 # Av
|
|||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -264,22 +264,22 @@ system.cpu.numCycles 10224081964 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199810242 # Number of instructions committed
|
||||
system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses
|
||||
system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374289914 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374289904 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 35624590 # number of memory refs
|
||||
system.cpu.num_load_insts 27216588 # Number of load instructions
|
||||
system.cpu.num_store_insts 8408002 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy
|
|||
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
|
||||
|
|
@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy
|
|||
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
|
||||
|
|
@ -471,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu
|
|||
system.cpu.dcache.writebacks::total 1534848 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 106558 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
|
||||
|
|
@ -479,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
|||
system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,45 +1,45 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.200409 # Number of seconds simulated
|
||||
sim_ticks 200409284500 # Number of ticks simulated
|
||||
final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 200409293000 # Number of ticks simulated
|
||||
final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 13697441 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 13697433 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5245128514 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 514692 # Number of bytes of host memory used
|
||||
host_seconds 38.21 # Real time elapsed on the host
|
||||
sim_insts 523360203 # Number of instructions simulated
|
||||
sim_ops 523360203 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory
|
||||
host_inst_rate 19440889 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7408936081 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 472492 # Number of bytes of host memory used
|
||||
host_seconds 27.05 # Real time elapsed on the host
|
||||
sim_insts 525869186 # Number of instructions simulated
|
||||
sim_ops 525869186 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.readReqs 0 # Total number of read requests seen
|
||||
testsys.physmem.writeReqs 0 # Total number of write requests seen
|
||||
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -189,7 +189,7 @@ testsys.physmem.avgRdBW 0.00 # Av
|
|||
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -214,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT
|
|||
testsys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
testsys.cpu.dtb.read_hits 3909164 # DTB read hits
|
||||
testsys.cpu.dtb.read_hits 3916928 # DTB read hits
|
||||
testsys.cpu.dtb.read_misses 3287 # DTB read misses
|
||||
testsys.cpu.dtb.read_acv 80 # DTB read access violations
|
||||
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
|
||||
testsys.cpu.dtb.write_hits 2312434 # DTB write hits
|
||||
testsys.cpu.dtb.write_hits 2316846 # DTB write hits
|
||||
testsys.cpu.dtb.write_misses 528 # DTB write misses
|
||||
testsys.cpu.dtb.write_acv 81 # DTB write access violations
|
||||
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
|
||||
testsys.cpu.dtb.data_hits 6221598 # DTB hits
|
||||
testsys.cpu.dtb.data_hits 6233774 # DTB hits
|
||||
testsys.cpu.dtb.data_misses 3815 # DTB misses
|
||||
testsys.cpu.dtb.data_acv 161 # DTB access violations
|
||||
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
|
||||
testsys.cpu.itb.fetch_hits 4045775 # ITB hits
|
||||
testsys.cpu.itb.fetch_hits 4052272 # ITB hits
|
||||
testsys.cpu.itb.fetch_misses 1497 # ITB misses
|
||||
testsys.cpu.itb.fetch_acv 69 # ITB acv
|
||||
testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses
|
||||
testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses
|
||||
testsys.cpu.itb.read_hits 0 # DTB read hits
|
||||
testsys.cpu.itb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -242,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT
|
|||
testsys.cpu.itb.data_misses 0 # DTB misses
|
||||
testsys.cpu.itb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.numCycles 400807419 # number of cpu cycles simulated
|
||||
testsys.cpu.numCycles 400815936 # number of cpu cycles simulated
|
||||
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
testsys.cpu.committedInsts 20218035 # Number of instructions committed
|
||||
testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses
|
||||
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
|
||||
testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 18800192 # number of integer instructions
|
||||
testsys.cpu.num_fp_insts 17380 # number of float instructions
|
||||
testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written
|
||||
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
|
||||
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
|
||||
testsys.cpu.num_mem_refs 6250795 # number of memory refs
|
||||
testsys.cpu.num_load_insts 3936233 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 2314562 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles
|
||||
testsys.cpu.committedInsts 20258165 # Number of instructions committed
|
||||
testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses
|
||||
testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses
|
||||
testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 18837392 # number of integer instructions
|
||||
testsys.cpu.num_fp_insts 17313 # number of float instructions
|
||||
testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written
|
||||
testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read
|
||||
testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written
|
||||
testsys.cpu.num_mem_refs 6263009 # number of memory refs
|
||||
testsys.cpu.num_load_insts 3944038 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 2318971 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
|
||||
|
|
@ -309,30 +309,30 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu
|
|||
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
|
||||
testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::total 128057 # number of callpals executed
|
||||
testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches
|
||||
testsys.cpu.kern.callpal::total 128317 # number of callpals executed
|
||||
testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_good::kernel 707
|
||||
testsys.cpu.kern.mode_good::user 702
|
||||
testsys.cpu.kern.mode_good::idle 5
|
||||
testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_good::user 703
|
||||
testsys.cpu.kern.mode_good::idle 4
|
||||
testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
|
||||
testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.swap_context 437 # number of times the context was actually changed
|
||||
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
|
||||
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
|
||||
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
|
||||
|
|
@ -343,9 +343,9 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu
|
|||
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
|
||||
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
|
||||
testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA
|
||||
testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA
|
||||
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
|
||||
testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
|
||||
testsys.tsunami.ethernet.totPackets 13 # Total Packets
|
||||
|
|
@ -370,9 +370,9 @@ testsys.tsunami.ethernet.totalRxDesc 5 # to
|
|||
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR
|
||||
testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR
|
||||
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
|
|
@ -380,37 +380,37 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu
|
|||
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory
|
||||
drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory
|
||||
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
|
||||
drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory
|
||||
drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory
|
||||
drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.readReqs 0 # Total number of read requests seen
|
||||
drivesys.physmem.writeReqs 0 # Total number of write requests seen
|
||||
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -560,7 +560,7 @@ drivesys.physmem.avgRdBW 0.00 # Av
|
|||
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -585,22 +585,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT
|
|||
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
drivesys.cpu.dtb.read_hits 3721202 # DTB read hits
|
||||
drivesys.cpu.dtb.read_hits 3729326 # DTB read hits
|
||||
drivesys.cpu.dtb.read_misses 487 # DTB read misses
|
||||
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
|
||||
drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses
|
||||
drivesys.cpu.dtb.write_hits 2081819 # DTB write hits
|
||||
drivesys.cpu.dtb.write_hits 2086333 # DTB write hits
|
||||
drivesys.cpu.dtb.write_misses 82 # DTB write misses
|
||||
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
|
||||
drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses
|
||||
drivesys.cpu.dtb.data_hits 5803021 # DTB hits
|
||||
drivesys.cpu.dtb.data_hits 5815659 # DTB hits
|
||||
drivesys.cpu.dtb.data_misses 569 # DTB misses
|
||||
drivesys.cpu.dtb.data_acv 40 # DTB access violations
|
||||
drivesys.cpu.dtb.data_accesses 401230 # DTB accesses
|
||||
drivesys.cpu.itb.fetch_hits 4194101 # ITB hits
|
||||
drivesys.cpu.itb.fetch_hits 4201097 # ITB hits
|
||||
drivesys.cpu.itb.fetch_misses 194 # ITB misses
|
||||
drivesys.cpu.itb.fetch_acv 22 # ITB acv
|
||||
drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses
|
||||
drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses
|
||||
drivesys.cpu.itb.read_hits 0 # DTB read hits
|
||||
drivesys.cpu.itb.read_misses 0 # DTB read misses
|
||||
drivesys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -613,51 +613,51 @@ drivesys.cpu.itb.data_hits 0 # DT
|
|||
drivesys.cpu.itb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.itb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated
|
||||
drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated
|
||||
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
drivesys.cpu.committedInsts 19029878 # Number of instructions committed
|
||||
drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed
|
||||
drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses
|
||||
drivesys.cpu.committedInsts 19071544 # Number of instructions committed
|
||||
drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed
|
||||
drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses
|
||||
drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses
|
||||
drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured
|
||||
drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls
|
||||
drivesys.cpu.num_int_insts 17721251 # number of integer instructions
|
||||
drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured
|
||||
drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls
|
||||
drivesys.cpu.num_int_insts 17759891 # number of integer instructions
|
||||
drivesys.cpu.num_fp_insts 1412 # number of float instructions
|
||||
drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read
|
||||
drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written
|
||||
drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read
|
||||
drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written
|
||||
drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read
|
||||
drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written
|
||||
drivesys.cpu.num_mem_refs 5824433 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 3742101 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 2082332 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles
|
||||
drivesys.cpu.num_mem_refs 5837119 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 3750273 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 2086846 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles
|
||||
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed
|
||||
drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed
|
||||
drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
|
||||
|
|
@ -673,26 +673,26 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu
|
|||
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
|
||||
drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::total 122686 # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::total 122978 # number of callpals executed
|
||||
drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_good::kernel 143
|
||||
drivesys.cpu.kern.mode_good::user 139
|
||||
drivesys.cpu.kern.mode_good::idle 4
|
||||
drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
|
||||
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
|
||||
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
|
||||
|
|
@ -704,9 +704,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu
|
|||
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
|
||||
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
|
||||
drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
|
||||
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
|
||||
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
|
||||
|
|
@ -731,9 +731,9 @@ drivesys.tsunami.ethernet.totalRxDesc 8 # to
|
|||
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
|
|
@ -741,49 +741,49 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu
|
|||
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000407 # Number of seconds simulated
|
||||
sim_ticks 406952000 # Number of ticks simulated
|
||||
final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 407365500 # Number of ticks simulated
|
||||
final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 7058170696 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 7056390513 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5484794115 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 514692 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 523432506 # Number of instructions simulated
|
||||
sim_ops 523432506 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s)
|
||||
host_inst_rate 12024534237 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9308365303 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 472492 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 525940622 # Number of instructions simulated
|
||||
sim_ops 525940622 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.readReqs 0 # Total number of read requests seen
|
||||
testsys.physmem.writeReqs 0 # Total number of write requests seen
|
||||
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -933,7 +933,7 @@ testsys.physmem.avgRdBW 0.00 # Av
|
|||
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -958,22 +958,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT
|
|||
testsys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
testsys.cpu.dtb.read_hits 7069 # DTB read hits
|
||||
testsys.cpu.dtb.read_hits 6900 # DTB read hits
|
||||
testsys.cpu.dtb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
testsys.cpu.dtb.write_hits 3933 # DTB write hits
|
||||
testsys.cpu.dtb.write_hits 3839 # DTB write hits
|
||||
testsys.cpu.dtb.write_misses 0 # DTB write misses
|
||||
testsys.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
testsys.cpu.dtb.data_hits 11002 # DTB hits
|
||||
testsys.cpu.dtb.data_hits 10739 # DTB hits
|
||||
testsys.cpu.dtb.data_misses 0 # DTB misses
|
||||
testsys.cpu.dtb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.dtb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.itb.fetch_hits 5992 # ITB hits
|
||||
testsys.cpu.itb.fetch_hits 5847 # ITB hits
|
||||
testsys.cpu.itb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.itb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
|
||||
testsys.cpu.itb.fetch_accesses 5847 # ITB accesses
|
||||
testsys.cpu.itb.read_hits 0 # DTB read hits
|
||||
testsys.cpu.itb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -986,58 +986,58 @@ testsys.cpu.itb.data_hits 0 # DT
|
|||
testsys.cpu.itb.data_misses 0 # DTB misses
|
||||
testsys.cpu.itb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.numCycles 821760 # number of cpu cycles simulated
|
||||
testsys.cpu.numCycles 799188 # number of cpu cycles simulated
|
||||
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
testsys.cpu.committedInsts 36151 # Number of instructions committed
|
||||
testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses
|
||||
testsys.cpu.committedInsts 35284 # Number of instructions committed
|
||||
testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses
|
||||
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
testsys.cpu.num_func_calls 2388 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 33514 # number of integer instructions
|
||||
testsys.cpu.num_func_calls 2330 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 32710 # number of integer instructions
|
||||
testsys.cpu.num_fp_insts 0 # number of float instructions
|
||||
testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written
|
||||
testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written
|
||||
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
testsys.cpu.num_mem_refs 11043 # number of memory refs
|
||||
testsys.cpu.num_load_insts 7109 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 3934 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles
|
||||
testsys.cpu.num_mem_refs 10779 # number of memory refs
|
||||
testsys.cpu.num_load_insts 6939 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 3840 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::total 254 # number of callpals executed
|
||||
testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::total 248 # number of callpals executed
|
||||
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_good::kernel 0
|
||||
testsys.cpu.kern.mode_good::user 0
|
||||
testsys.cpu.kern.mode_good::idle 0
|
||||
|
|
@ -1049,9 +1049,9 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu
|
|||
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
|
||||
testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA
|
||||
testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA
|
||||
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
||||
|
|
@ -1068,9 +1068,9 @@ testsys.tsunami.ethernet.totalRxDesc 0 # to
|
|||
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR
|
||||
testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR
|
||||
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
|
|
@ -1078,34 +1078,34 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu
|
|||
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
|
||||
drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
|
||||
drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.readReqs 0 # Total number of read requests seen
|
||||
drivesys.physmem.writeReqs 0 # Total number of write requests seen
|
||||
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -1255,7 +1255,7 @@ drivesys.physmem.avgRdBW 0.00 # Av
|
|||
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
|
|
@ -1308,7 +1308,7 @@ drivesys.cpu.itb.data_hits 0 # DT
|
|||
drivesys.cpu.itb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.itb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated
|
||||
drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated
|
||||
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
drivesys.cpu.committedInsts 36152 # Number of instructions committed
|
||||
|
|
@ -1326,10 +1326,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu
|
|||
drivesys.cpu.num_mem_refs 11043 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 7109 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 3934 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles
|
||||
drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles
|
||||
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
|
||||
|
|
@ -1343,11 +1343,11 @@ drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # nu
|
|||
drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
|
|
@ -1371,9 +1371,9 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu
|
|||
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
|
||||
drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
||||
|
|
@ -1392,7 +1392,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av
|
|||
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
|
|
@ -1400,7 +1400,7 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu
|
|||
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18737000 # Number of ticks simulated
|
||||
final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 19476000 # Number of ticks simulated
|
||||
final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 42684 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42679 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 125129111 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269636 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 78389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 78368 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 238789679 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223680 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
|
|||
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -37,21 +37,21 @@ system.physmem.bytesConsumedWr 0 # by
|
|||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 18722500 # Total gap between requests
|
||||
system.physmem.totGap 19461500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 1862969 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1876000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7910000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3972.22 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16865.67 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24837.89 # Average memory access latency
|
||||
system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 2628216 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2345000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8401250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5603.87 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17913.11 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28516.99 # Average memory access latency
|
||||
system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.99 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.62 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 12.01 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.69 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 401 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 377 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 39920.04 # Average gap between requests
|
||||
system.physmem.avgGap 41495.74 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 1632 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
|
||||
|
|
@ -202,14 +202,14 @@ system.cpu.dtb.read_hits 1183 # DT
|
|||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1190 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_hits 866 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2048 # DTB hits
|
||||
system.cpu.dtb.write_accesses 869 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2049 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2058 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 2059 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 915 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 37475 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 38953 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2152 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 4448 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7374 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 19.677118 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 18.933073 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1183 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
||||
|
|
@ -266,72 +266,72 @@ system.cpu.committedInsts 6390 # Nu
|
|||
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 561 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 561 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 354 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles
|
||||
system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 560 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 355 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -340,48 +340,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -399,17 +399,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5344500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 20888500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8903000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24447000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15544000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8903000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24447000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -432,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -462,17 +462,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -484,27 +484,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
|
||||
|
|
@ -521,14 +521,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
|
|||
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -545,19 +545,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -577,14 +577,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -593,14 +593,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 13354000 # Number of ticks simulated
|
||||
final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
sim_ticks 13709000 # Number of ticks simulated
|
||||
final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22763 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 28403 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66199618 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 285296 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_inst_rate 51480 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64222 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 153638426 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239936 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu
|
|||
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 394 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 13296500 # Total gap between requests
|
||||
system.physmem.totGap 13651500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2460894 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1576000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 6524000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6245.92 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
|
||||
system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 2508144 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1970000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7273750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6365.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18461.29 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 29827.14 # Average memory access latency
|
||||
system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 11.80 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.79 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 14.37 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.86 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 319 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 294 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 33747.46 # Average gap between requests
|
||||
system.physmem.avgGap 34648.48 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 2501 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
|
||||
|
|
@ -282,50 +282,50 @@ system.cpu.itb.inst_accesses 0 # IT
|
|||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 26709 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 27419 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2444 # Number of cycles decode is running
|
||||
system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2445 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
|
||||
|
|
@ -347,28 +347,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu
|
|||
system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
|
||||
|
|
@ -404,50 +404,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
|
||||
system.cpu.iq.rate 0.336516 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 8986 # Type of FU issued
|
||||
system.cpu.iq.rate 0.327729 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads
|
||||
system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -475,42 +475,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu
|
|||
system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3303 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1443 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1444 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1167 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.320604 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8105 # cumulative count of insts written-back
|
||||
system.cpu.iew.exec_rate 0.312302 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8106 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3904 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -523,117 +523,117 @@ system.cpu.commit.int_insts 4976 # Nu
|
|||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 22955 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 23072 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23605 # The number of ROB writes
|
||||
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39368 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 8018 # number of integer regfile writes
|
||||
system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39366 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 8019 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 3 # number of replacements
|
||||
system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1597 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1596 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1597 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 359 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles
|
||||
system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1596 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 360 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
|
||||
|
|
@ -654,17 +654,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 399 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -687,17 +687,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -723,17 +723,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -745,109 +745,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2373 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2370 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 498 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 500 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
|
||||
|
|
@ -856,30 +856,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 13354000 # Number of ticks simulated
|
||||
final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
sim_ticks 13709000 # Number of ticks simulated
|
||||
final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 20035 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24999 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 58267208 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 285296 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
host_inst_rate 58002 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72354 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 173086159 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238920 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu
|
|||
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 394 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 13296500 # Total gap between requests
|
||||
system.physmem.totGap 13651500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2460894 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1576000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 6524000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6245.92 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
|
||||
system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 2508144 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1970000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7273750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6365.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18461.29 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 29827.14 # Average memory access latency
|
||||
system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 11.80 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.79 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 14.37 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.86 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 319 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 294 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 33747.46 # Average gap between requests
|
||||
system.physmem.avgGap 34648.48 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 2501 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
|
||||
|
|
@ -237,50 +237,50 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 26709 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 27419 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2444 # Number of cycles decode is running
|
||||
system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2445 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
|
||||
|
|
@ -302,28 +302,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu
|
|||
system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
|
||||
|
|
@ -359,50 +359,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
|
||||
system.cpu.iq.rate 0.336516 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 8986 # Type of FU issued
|
||||
system.cpu.iq.rate 0.327729 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads
|
||||
system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -430,42 +430,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu
|
|||
system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3303 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1443 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1444 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1167 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.320604 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8105 # cumulative count of insts written-back
|
||||
system.cpu.iew.exec_rate 0.312302 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8106 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3904 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -478,117 +478,117 @@ system.cpu.commit.int_insts 4976 # Nu
|
|||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 22955 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 23072 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23605 # The number of ROB writes
|
||||
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39368 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 8018 # number of integer regfile writes
|
||||
system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39366 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 8019 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 3 # number of replacements
|
||||
system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1597 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1596 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1597 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 359 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles
|
||||
system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1596 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 360 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
|
||||
|
|
@ -609,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 399 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -642,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -678,17 +678,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -700,109 +700,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2373 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2370 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 498 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 500 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
|
||||
|
|
@ -811,30 +811,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18578000 # Number of ticks simulated
|
||||
final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 19339000 # Number of ticks simulated
|
||||
final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49489 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 49481 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 158085302 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270352 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 100636 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100592 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 334460805 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224316 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu
|
|||
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 455 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 18503000 # Total gap between requests
|
||||
system.physmem.totGap 19292000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2354454 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12658454 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1820000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8484000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5174.62 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18646.15 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27820.78 # Average memory access latency
|
||||
system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 2650454 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2275000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 9033750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5825.17 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19854.40 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 30679.57 # Average memory access latency
|
||||
system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.80 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.68 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 11.76 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.72 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 357 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 334 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 40665.93 # Average gap between requests
|
||||
system.physmem.avgGap 42400.00 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 1154 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
|
||||
|
|
@ -213,7 +213,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 37157 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 38679 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -235,12 +235,12 @@ system.cpu.execution_unit.executions 3135 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 9462 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 5375 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 14.465646 # Percentage of cycles cpu is active
|
||||
system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 5376 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 13.899015 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1163 # Number of Load instructions committed
|
||||
system.cpu.comStores 925 # Number of Store instructions committed
|
||||
system.cpu.comBranches 915 # Number of Branches instructions committed
|
||||
|
|
@ -252,36 +252,36 @@ system.cpu.committedInsts 5814 # Nu
|
|||
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 33508 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 9.820491 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34341 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 7.578653 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34392 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 7.441397 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 34255 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 7.810103 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.tagsinuse 149.849185 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 149.849185 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.073169 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.073169 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
|
||||
|
|
@ -294,12 +294,12 @@ system.cpu.icache.demand_misses::cpu.inst 346 # n
|
|||
system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 346 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18063500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18063500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18063500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18063500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18063500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18063500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses
|
||||
|
|
@ -312,12 +312,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.447028
|
|||
system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52206.647399 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52206.647399 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52206.647399 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52206.647399 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -338,36 +338,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
|
|||
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16468000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16468000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16468000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16468000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16468000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16468000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51623.824451 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51623.824451 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 207.484772 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 151.598539 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 55.886233 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004626 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -385,17 +385,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16122500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5062000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 21184500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7626500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23749000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16122500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7626500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23749000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16983500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5162000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 22145500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2560500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2560500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16983500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7722500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24706000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16983500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7722500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24706000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -418,17 +418,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50859.621451 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58183.908046 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52436.881188 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52195.604396 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52195.604396 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53575.709779 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59333.333333 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54815.594059 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50205.882353 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50205.882353 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54298.901099 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54298.901099 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -448,17 +448,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12118017 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982594 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16100611 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12118017 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5912166 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18030183 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12118017 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5912166 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18030183 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -470,27 +470,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38227.182965 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45776.942529 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39852.997525 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 89.859083 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 89.859083 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021938 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021938 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits
|
||||
|
|
@ -507,14 +507,14 @@ system.cpu.dcache.demand_misses::cpu.data 444 # n
|
|||
system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 444 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5589500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14659500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14659500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20249000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20249000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20249000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20249000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -531,14 +531,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.212644
|
|||
system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60102.150538 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60102.150538 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41764.957265 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 41764.957265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45605.855856 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45605.855856 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -563,14 +563,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7774000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7774000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7774000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7774000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -579,14 +579,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59258.620690 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59258.620690 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000016 # Number of seconds simulated
|
||||
sim_ticks 16286500 # Number of ticks simulated
|
||||
final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16783500 # Number of ticks simulated
|
||||
final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 32843 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 32839 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 100387600 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278524 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 84096 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84062 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 264753473 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230292 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu
|
|||
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 423 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27072 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 16235000 # Total gap between requests
|
||||
system.physmem.totGap 16708000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2302422 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1692000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7308000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5443.08 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17276.60 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26719.67 # Average memory access latency
|
||||
system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 2673172 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2115000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8208750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6319.56 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19406.03 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 30725.58 # Average memory access latency
|
||||
system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 10.39 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.69 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 12.60 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.77 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 336 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 300 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 38380.61 # Average gap between requests
|
||||
system.physmem.avgGap 39498.82 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 1636 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
|
||||
|
|
@ -195,14 +195,14 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT
|
|||
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 32574 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 33568 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
|
||||
|
|
@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 3957 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6247 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 19.177872 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 18.604028 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 715 # Number of Load instructions committed
|
||||
system.cpu.comStores 673 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1115 # Number of Branches instructions committed
|
||||
|
|
@ -234,36 +234,36 @@ system.cpu.committedInsts 5327 # Nu
|
|||
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 895 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits
|
||||
|
|
@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 362 # n
|
|||
system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 362 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18347500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18347500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18347500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses
|
||||
|
|
@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.287987
|
|||
system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 50683.701657 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 50683.701657 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
|
|||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 142.886606 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 27.119790 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
|
@ -370,17 +370,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4069000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4069000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6941500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6941500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21817000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -403,17 +403,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50234.567901 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50234.567901 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51576.832151 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51576.832151 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -433,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11236437 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -455,27 +455,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
||||
|
|
@ -492,14 +492,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n
|
|||
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -516,19 +516,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499
|
|||
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -548,14 +548,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
|||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -564,14 +564,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000023 # Number of seconds simulated
|
||||
sim_ticks 22838500 # Number of ticks simulated
|
||||
final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 23146500 # Number of ticks simulated
|
||||
final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 21741 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 21740 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32746771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278448 # Number of bytes of host memory used
|
||||
host_seconds 0.70 # Real time elapsed on the host
|
||||
host_inst_rate 62448 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 62442 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 95315643 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230224 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu
|
|||
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 835081113 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 386715415 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1221796528 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 835081113 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 835081113 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 835081113 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 386715415 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1221796528 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 436 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27904 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 25 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 17 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 22805000 # Total gap between requests
|
||||
system.physmem.totGap 23113000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,41 +164,41 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2325934 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11335934 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1744000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7266000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5334.71 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16665.14 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 25999.85 # Average memory access latency
|
||||
system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 2156686 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2180000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7727500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4946.53 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17723.62 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27670.15 # Average memory access latency
|
||||
system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 7.64 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.50 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.42 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.52 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 359 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 339 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 52305.05 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 5147 # Number of BP lookups
|
||||
system.physmem.avgGap 53011.47 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 5146 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 4101 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2720 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2719 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 66.325287 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 45678 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 46294 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 2894 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
|
||||
|
|
@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 11045 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 21903 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 28109 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 17569 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 38.462717 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 37.948762 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 2225 # Number of Load instructions committed
|
||||
system.cpu.comStores 1448 # Number of Store instructions committed
|
||||
system.cpu.comBranches 3358 # Number of Branches instructions committed
|
||||
|
|
@ -234,36 +234,36 @@ system.cpu.committedInsts 15162 # Nu
|
|||
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 3.012663 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 3.012663 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32252 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 29.392705 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 36324 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 9354 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 20.478130 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 36874 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 8804 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 19.274049 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 36369 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 20.379614 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 172.574474 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 172.574474 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.084265 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.084265 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
|
||||
|
|
@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n
|
|||
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 381 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18868500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18868500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18868500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18868500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18868500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18868500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
|
||||
|
|
@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555
|
|||
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49523.622047 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49523.622047 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
|
|||
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15157500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15157500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15157500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15157500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50357.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50357.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 204.083022 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 171.933146 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 32.149876 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -367,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14874500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17720500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14874500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22146500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14874500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22146500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14678000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3230000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17908000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4625000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4625000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14678000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7855000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22533000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14678000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7855000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22533000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -400,17 +400,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49747.491639 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 50342.329545 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 50678.489703 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 50678.489703 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49090.301003 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60943.396226 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 50875 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54411.764706 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54411.764706 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51562.929062 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51562.929062 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -430,17 +430,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11105481 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13287049 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11105481 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16669113 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11105481 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16669113 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -452,27 +452,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37142.076923 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37747.298295 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 99.519804 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 99.519804 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 99.212064 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.024222 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.024222 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
|
||||
|
|
@ -491,14 +491,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n
|
|||
system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 480 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3301000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3301000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19263500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19263500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22564500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22564500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22564500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22564500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3686000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3686000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19969500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19969500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 23655500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 23655500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 23655500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 23655500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -517,19 +517,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897
|
|||
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47009.375000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47009.375000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63551.724138 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63551.724138 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47321.090047 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 47321.090047 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 49282.291667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 49282.291667 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 760 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.352941 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4514000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4514000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7414500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7414500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7414500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7414500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3284500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3284500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4713000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4713000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7997500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7997500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7997500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7997500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -565,14 +565,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61971.698113 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61971.698113 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55447.058824 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55447.058824 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000023 # Number of seconds simulated
|
||||
sim_ticks 23180500 # Number of ticks simulated
|
||||
final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000024 # Number of seconds simulated
|
||||
sim_ticks 23775500 # Number of ticks simulated
|
||||
final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 20805 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 20805 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33406458 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278444 # Number of bytes of host memory used
|
||||
host_seconds 0.69 # Real time elapsed on the host
|
||||
host_inst_rate 69212 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69204 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 113962469 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232268 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu
|
|||
system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 483 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30912 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 23120500 # Total gap between requests
|
||||
system.physmem.totGap 23715500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -164,121 +164,121 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 3040483 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1932000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8008000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6295.00 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16579.71 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26874.71 # Average memory access latency
|
||||
system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.totQLat 4632480 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2415000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8566250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 9591.06 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17735.51 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 32326.56 # Average memory access latency
|
||||
system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 8.33 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.56 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 10.16 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.66 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 394 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 369 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 47868.53 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 6759 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted
|
||||
system.physmem.avgGap 49100.41 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 6770 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2448 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2447 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 46362 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 47552 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched
|
||||
system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 8405 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 8008 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename
|
||||
system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 8402 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 8002 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups
|
||||
system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups
|
||||
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available
|
||||
|
|
@ -314,69 +314,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 21285 # Type of FU issued
|
||||
system.cpu.iq.rate 0.459104 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 21278 # Type of FU issued
|
||||
system.cpu.iq.rate 0.447468 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes
|
||||
system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
|
|
@ -384,43 +384,43 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 1139 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 5276 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 4247 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 2055 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.435853 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.exec_nop 1136 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 5272 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 4246 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 2053 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.424882 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 19647 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 9210 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 11373 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 9208 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 11364 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 15162 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -433,66 +433,66 @@ system.cpu.commit.int_insts 12174 # Nu
|
|||
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 54162 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 50836 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 54359 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 50813 # The number of ROB writes
|
||||
system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 32290 # number of integer regfile reads
|
||||
system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 32289 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17967 # number of integer regfile writes
|
||||
system.cpu.misc_regfile_reads 6967 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 6962 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4845 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4850 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4845 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 493 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4850 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 491 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -501,48 +501,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 155 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 155 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 155 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 153 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 153 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 153 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 153 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 153 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063284 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52118.343195 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52118.343195 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 225.767373 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006890 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -560,17 +560,17 @@ system.cpu.l2cache.demand_misses::total 483 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 483 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16755500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 20527500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4421500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4421500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16755500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8193500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24949000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16755500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8193500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17258000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4829500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 22087500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5160500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5160500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 17258000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9990000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 27248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 17258000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9990000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 27248000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -593,17 +593,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995876 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49867.559524 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58937.500000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51318.750000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53271.084337 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53271.084337 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12529012 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2980062 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15509074 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3397062 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3397062 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12529012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6377124 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18906136 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12529012 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6377124 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18906136 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -645,95 +645,95 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37288.726190 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38772.685000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40928.457831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40928.457831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.340136 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.326531 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 99.943036 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.024400 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 99.563734 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.024308 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.024308 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2978 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2978 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 4013 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 4011 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 4011 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 4011 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 4011 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 539 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6943000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6943000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19544474 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19544474 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 26487474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 26487474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 26487474 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 26487474 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 3110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 3110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 540 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21053474 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30052474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30052474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30052474 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30052474 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 3109 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 3109 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 4552 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 4552 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 4552 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 4552 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041801 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.041801 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 4551 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 4551 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 4551 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 4551 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.042136 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.118409 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.118409 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.118409 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.118409 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53407.692308 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 53407.692308 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47786 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 47786 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 49141.881262 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 49141.881262 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
|
||||
|
|
@ -742,30 +742,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3836500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3836500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 18434818132 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219256 # Number of bytes of host memory used
|
||||
host_seconds 5.42 # Real time elapsed on the host
|
||||
host_tick_rate 29045358432 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222412 # Number of bytes of host memory used
|
||||
host_seconds 3.44 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory
|
||||
system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory
|
||||
|
|
@ -25,21 +25,21 @@ system.physmem.bytesConsumedWr 0 # by
|
|||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 211200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 210200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 210200 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 208000 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -86,18 +86,18 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 3267797 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 52471 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 1882 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2141 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1602 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 1074 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 1074 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 804 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 538 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 274 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
|
|
@ -152,25 +152,25 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2980562702 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 63351670702 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 13333600000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 47037508000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 894.15 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14110.97 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 19005.12 # Average memory access latency
|
||||
system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 16667000000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 46722610000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 1834.67 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14016.50 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 20851.17 # Average memory access latency
|
||||
system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 13.33 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.63 # Average read queue length over time
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 16.67 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.70 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 3281300 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 3229200 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 98.44 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 96.87 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 29999.40 # Average gap between requests
|
||||
system.monitor.readBurstLengthHist::samples 3333400 # Histogram of burst lengths of transmitted packets
|
||||
|
|
@ -278,20 +278,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi
|
|||
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
|
||||
system.monitor.totalWrittenBytes 0 # Number of bytes written
|
||||
system.monitor.readLatencyHist::samples 3333399 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 19061.873685 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 18381.352509 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 11230.520439 # Read request-response latency
|
||||
system.monitor.readLatencyHist::0-32767 3267631 98.03% 98.03% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 52364 1.57% 99.60% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 2680 0.08% 99.68% # Read request-response latency
|
||||
system.monitor.readLatencyHist::98304-131071 2415 0.07% 99.75% # Read request-response latency
|
||||
system.monitor.readLatencyHist::131072-163839 2133 0.06% 99.81% # Read request-response latency
|
||||
system.monitor.readLatencyHist::163840-196607 1602 0.05% 99.86% # Read request-response latency
|
||||
system.monitor.readLatencyHist::196608-229375 1620 0.05% 99.91% # Read request-response latency
|
||||
system.monitor.readLatencyHist::229376-262143 1066 0.03% 99.94% # Read request-response latency
|
||||
system.monitor.readLatencyHist::262144-294911 802 0.02% 99.97% # Read request-response latency
|
||||
system.monitor.readLatencyHist::294912-327679 812 0.02% 99.99% # Read request-response latency
|
||||
system.monitor.readLatencyHist::327680-360447 274 0.01% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency
|
||||
system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency
|
||||
system.monitor.readLatencyHist::98304-131071 4826 0.14% 99.50% # Read request-response latency
|
||||
system.monitor.readLatencyHist::131072-163839 4267 0.13% 99.63% # Read request-response latency
|
||||
system.monitor.readLatencyHist::163840-196607 3205 0.10% 99.73% # Read request-response latency
|
||||
system.monitor.readLatencyHist::196608-229375 3236 0.10% 99.82% # Read request-response latency
|
||||
system.monitor.readLatencyHist::229376-262143 2130 0.06% 99.89% # Read request-response latency
|
||||
system.monitor.readLatencyHist::262144-294911 1602 0.05% 99.94% # Read request-response latency
|
||||
system.monitor.readLatencyHist::294912-327679 1620 0.05% 99.98% # Read request-response latency
|
||||
system.monitor.readLatencyHist::327680-360447 546 0.02% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency
|
||||
|
|
|
|||
Loading…
Reference in a new issue