fce3433b2e
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
1089 lines
126 KiB
Plaintext
1089 lines
126 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.533245 # Number of seconds simulated
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sim_ticks 2533245380500 # Number of ticks simulated
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final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 67317 # Simulator instruction rate (inst/s)
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host_op_rate 86618 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2827634962 # Simulator tick rate (ticks/s)
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host_mem_usage 409784 # Number of bytes of host memory used
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host_seconds 895.89 # Real time elapsed on the host
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sim_insts 60308251 # Number of instructions simulated
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sim_ops 77599937 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory
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system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15096850 # Total number of read requests seen
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system.physmem.writeReqs 813145 # Total number of write requests seen
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system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 966198400 # Total number of bytes read from memory
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system.physmem.bytesWritten 52041280 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2533244279000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 36 # Categorize read packet sizes
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system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 154606 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 2927056 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 59127 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests
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system.physmem.totBusLat 75482595000 # Total cycles spent in databus access
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system.physmem.totBankLat 16916941250 # Total cycles spent in bank access
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system.physmem.avgQLat 26034.38 # Average queueing delay per request
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system.physmem.avgBankLat 1120.59 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 32154.97 # Average memory access latency
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system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.14 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.19 # Average read queue length over time
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system.physmem.avgWrQLen 12.52 # Average write queue length over time
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system.physmem.readRowHits 15020214 # Number of row buffer hits during reads
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system.physmem.writeRowHits 793069 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
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system.physmem.avgGap 159223.45 # Average gap between requests
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system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.branchPred.lookups 14667589 # Number of BP lookups
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system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 51389080 # DTB read hits
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system.cpu.dtb.read_misses 73326 # DTB read misses
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system.cpu.dtb.write_hits 11702658 # DTB write hits
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system.cpu.dtb.write_misses 17128 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 51462406 # DTB read accesses
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system.cpu.dtb.write_accesses 11719786 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 63091738 # DTB hits
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system.cpu.dtb.misses 90454 # DTB misses
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system.cpu.dtb.accesses 63182192 # DTB accesses
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system.cpu.itb.inst_hits 12277036 # ITB inst hits
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system.cpu.itb.inst_misses 11490 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 2578 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 12288526 # ITB inst accesses
|
|
system.cpu.itb.hits 12277036 # DTB hits
|
|
system.cpu.itb.misses 11490 # DTB misses
|
|
system.cpu.itb.accesses 12288526 # DTB accesses
|
|
system.cpu.numCycles 472097236 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued
|
|
system.cpu.iq.rate 0.263176 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 220577 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 11563754 # Number of branches executed
|
|
system.cpu.iew.exec_stores 12214366 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.257379 # Inst execution rate
|
|
system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 47207424 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 60458632 # Number of instructions committed
|
|
system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27386920 # Number of memory references committed
|
|
system.cpu.commit.loads 15654712 # Number of loads committed
|
|
system.cpu.commit.membars 403607 # Number of memory barriers committed
|
|
system.cpu.commit.branches 9961406 # Number of branches committed
|
|
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 68855494 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 991273 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 242460133 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 201635862 # The number of ROB writes
|
|
system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 60308251 # Number of Instructions Simulated
|
|
system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 550197994 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 88410647 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 8198 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2906 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
|
|
system.cpu.icache.replacements 980802 # number of replacements
|
|
system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 11213050 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1060138 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78782 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 78782 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 78782 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 78782 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 78782 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 78782 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981356 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 981356 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 981356 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 981356 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 981356 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 981356 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11396806498 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11396806498 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11396806498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11396806498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11396806498 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11396806498 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079959 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.079959 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.079959 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11613.325336 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11613.325336 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 64377 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 51361.576516 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1911659 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 129770 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 14.731132 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 2498200145000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 36918.334944 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 32.795639 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 8184.403113 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6226.042472 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.563329 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000500 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.124884 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.095002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.783715 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79915 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11190 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 967706 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 386775 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1445586 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 607265 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 607265 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 112880 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 112880 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 79915 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 11190 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 967706 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 499655 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1558466 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 79915 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 11190 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 967706 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 499655 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1558466 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12360 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12360 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143917 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 156325 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12360 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143917 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 156325 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3160000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 702880500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 627994499 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1334152999 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 589500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 589500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6741992998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6741992998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3160000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 702880500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7369987497 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8076145997 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3160000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 702880500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7369987497 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8076145997 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79961 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11192 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 980066 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 397492 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1468711 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 607265 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 607265 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246080 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 246080 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79961 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 11192 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 980066 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 643572 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1714791 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79961 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 11192 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 980066 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 643572 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1714791 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000575 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000179 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012611 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.015745 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985145 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985145 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.105263 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.105263 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541287 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541287 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000575 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000179 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012611 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223622 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.091163 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000575 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000179 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012611 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223622 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.091163 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68695.652174 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56867.354369 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58597.975086 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57693.102659 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 202.021933 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 202.021933 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50615.563048 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50615.563048 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68695.652174 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56867.354369 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51209.985596 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51662.536363 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68695.652174 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56867.354369 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51209.985596 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51662.536363 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 59127 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 59127 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12347 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 23051 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12347 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143856 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 156251 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12347 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143856 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 156251 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2584839 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93252 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 548548146 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 492444540 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043670777 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29186917 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29186917 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5081813058 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5081813058 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2584839 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93252 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 548548146 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5574257598 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6125483835 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2584839 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93252 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 548548146 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5574257598 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6125483835 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079407 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167001894776 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167006974183 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26372604056 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26372604056 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079407 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193374498832 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193379578239 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026808 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015695 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985145 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985145 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.105263 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.105263 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541287 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541287 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223527 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.091120 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223527 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.091120 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46626 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44427.646068 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46212.888514 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45276.594378 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.370459 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.370459 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38151.749685 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38151.749685 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 643060 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.992813 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 21518829 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 643572 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 33.436553 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 42289000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.992813 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13762862 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13762862 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 7262343 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 7262343 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 242888 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 242888 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 21025205 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 21025205 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 21025205 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 21025205 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 731521 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 731521 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2960125 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2960125 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13538 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 13538 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3691646 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3691646 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3691646 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3691646 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9676520000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9676520000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104419203240 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 104419203240 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181802500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 181802500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 271000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 271000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 114095723240 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 114095723240 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 114095723240 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 114095723240 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 14494383 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 14494383 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10222468 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10222468 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256426 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 256426 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247620 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247620 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 24716851 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 24716851 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 24716851 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 24716851 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050469 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.050469 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289570 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.289570 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052795 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052795 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000077 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000077 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 607265 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|