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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Andreas Hansson fce3433b2e stats: Update stats for regressions using SimpleDDR3 
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
2013-01-31 07:49:16 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.401347 # Number of seconds simulated
sim_ticks 2401347058000 # Number of ticks simulated
final_tick 2401347058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 247220 # Simulator instruction rate (inst/s)
host_op_rate 317493 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9839599535 # Simulator tick rate (ticks/s)
host_mem_usage 400552 # Number of bytes of host memory used
host_seconds 244.05 # Real time elapsed on the host
sim_insts 60333921 # Number of instructions simulated
sim_ops 77484019 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 501472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 7131280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 85632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 677504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1269180 # Number of bytes read from this memory
system.physmem.bytes_read::total 124661740 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 501472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 85632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 764064 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3746368 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1495356 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data 1321004 # Number of bytes written to this memory
system.physmem.bytes_written::total 6762184 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14038 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 111460 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1338 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10586 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 19845 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14512426 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58537 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 373839 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data 330251 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812491 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47814443 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 208829 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2969700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 35660 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 282135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 73692 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 528528 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51913254 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 208829 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 35660 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 73692 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 318181 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1560111 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 622715 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data 550110 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2815996 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1560111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47814443 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 208829 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3592415 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 35660 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 365195 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 73692 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1078638 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54729250 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 12617453 # Total number of read requests seen
system.physmem.writeReqs 397526 # Total number of write requests seen
system.physmem.cpureqs 54288 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 807516992 # Total number of bytes read from memory
system.physmem.bytesWritten 25441664 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 102873020 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2634764 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 789108 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 788757 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 788840 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 789165 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 789011 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 788682 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 788876 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 788949 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 788591 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 787997 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 788008 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 788277 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 788205 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 788031 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 788257 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 788698 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 24832 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 24781 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 25063 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 24852 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 25063 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 25253 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 25236 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 24651 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 24325 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 24263 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 24366 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 24934 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 24846 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 25132 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 749984 # Number of times wr buffer was full causing retry
system.physmem.totGap 2400311882000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 15 # Categorize read packet sizes
system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 34526 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 1130099 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 17411 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 2351 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 815640 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 791627 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 797680 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2998199 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2260925 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2261235 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2249585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 49266 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 49185 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 91366 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 133537 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 91353 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 6968 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 6962 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6960 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 6958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 3037 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3074 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 3384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 17292 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 17287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 17285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 17280 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 17275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 17269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 17264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 17259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 17259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 14298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 14254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 14208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 14055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 14034 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 14010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 13970 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 13934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 13913 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 277194471582 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 353012127832 # Sum of mem lat for all requests
system.physmem.totBusLat 63087260000 # Total cycles spent in databus access
system.physmem.totBankLat 12730396250 # Total cycles spent in bank access
system.physmem.avgQLat 21969.13 # Average queueing delay per request
system.physmem.avgBankLat 1008.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27978.08 # Average memory access latency
system.physmem.avgRdBW 336.28 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 10.59 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 42.84 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.71 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 0.39 # Average write queue length over time
system.physmem.readRowHits 12562851 # Number of row buffer hits during reads
system.physmem.writeRowHits 391169 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.40 # Row buffer hit rate for writes
system.physmem.avgGap 184426.87 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 63262 # number of replacements
system.l2c.tagsinuse 50352.279574 # Cycle average of tags in use
system.l2c.total_refs 1759649 # Total number of references to valid blocks.
system.l2c.sampled_refs 128652 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.677588 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2374416909500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36834.025606 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 5156.727312 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3775.205663 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 795.394812 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 755.555046 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.dtb.walker 5.900240 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 1436.095715 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 1592.381720 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.562043 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.078685 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.057605 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.012137 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.011529 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.021913 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.024298 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.768315 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 8915 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3218 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 460985 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 169797 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 2555 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1118 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 134527 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 65561 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 28959 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 4314 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 283968 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 137931 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1301848 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 597795 # number of Writeback hits
system.l2c.Writeback_hits::total 597795 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 61039 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 19134 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 33458 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113631 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 8915 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3218 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 460985 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 230836 # number of demand (read+write) hits
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system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 145949840 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 124327253 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 383656903 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5062472 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9850985 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 14913457 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 312092166 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 723390596 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1035482762 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 58196898 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 366881314 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 337512 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 145949840 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 847717849 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1419139665 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56252 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 58196898 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 366881314 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 337512 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 145949840 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 847717849 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1419139665 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25146563500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26567091024 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 51713654524 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647324364 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9537940251 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 10185264615 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25793887864 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36105031275 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 61898919139 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018136 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018242 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.005957 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992079 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985000 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.505786 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.335210 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348001 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.111361 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.113643 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.106460 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.022534 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.113643 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.106460 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.022534 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45242.896780 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48508.487320 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 48662.722349 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.734531 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.973755 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32347.861318 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40507.928995 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 37645.705010 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 8069329 # DTB read hits
system.cpu0.dtb.read_misses 6237 # DTB read misses
system.cpu0.dtb.write_hits 6635324 # DTB write hits
system.cpu0.dtb.write_misses 2059 # DTB write misses
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5724 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 8075566 # DTB read accesses
system.cpu0.dtb.write_accesses 6637383 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 14704653 # DTB hits
system.cpu0.dtb.misses 8296 # DTB misses
system.cpu0.dtb.accesses 14712949 # DTB accesses
system.cpu0.itb.inst_hits 32681523 # ITB inst hits
system.cpu0.itb.inst_misses 3486 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 32685009 # ITB inst accesses
system.cpu0.itb.hits 32681523 # DTB hits
system.cpu0.itb.misses 3486 # DTB misses
system.cpu0.itb.accesses 32685009 # DTB accesses
system.cpu0.numCycles 114009309 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 32183346 # Number of instructions committed
system.cpu0.committedOps 42389974 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 37541413 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5201 # Number of float alu accesses
system.cpu0.num_func_calls 1186772 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4235639 # number of instructions that are conditional controls
system.cpu0.num_int_insts 37541413 # number of integer instructions
system.cpu0.num_fp_insts 5201 # number of float instructions
system.cpu0.num_int_register_reads 191262498 # number of times the integer registers were read
system.cpu0.num_int_register_writes 39620034 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3719 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1484 # number of times the floating registers were written
system.cpu0.num_mem_refs 15366811 # number of memory refs
system.cpu0.num_load_insts 8436504 # Number of load instructions
system.cpu0.num_store_insts 6930307 # Number of store instructions
system.cpu0.num_idle_cycles 13418269361.007845 # Number of idle cycles
system.cpu0.num_busy_cycles -13304260052.007845 # Number of busy cycles
system.cpu0.not_idle_fraction -116.694507 # Percentage of non-idle cycles
system.cpu0.idle_fraction 117.694507 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed
system.cpu0.icache.replacements 892035 # number of replacements
system.cpu0.icache.tagsinuse 511.603883 # Cycle average of tags in use
system.cpu0.icache.total_refs 44343596 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 892547 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 49.682085 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 8110895000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 479.105953 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 18.181823 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst 14.316107 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.935754 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.035511 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst 0.027961 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999226 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 32215079 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 8406427 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3722090 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 44343596 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 32215079 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 8406427 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3722090 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 44343596 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 32215079 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 8406427 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3722090 # number of overall hits
system.cpu0.icache.overall_hits::total 44343596 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 469123 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 136142 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 311123 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 916388 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 469123 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 136142 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 311123 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 916388 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 469123 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 136142 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 311123 # number of overall misses
system.cpu0.icache.overall_misses::total 916388 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1835025000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152863490 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 5987888490 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1835025000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4152863490 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 5987888490 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1835025000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4152863490 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 5987888490 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32684202 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8542569 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 4033213 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 45259984 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32684202 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 8542569 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 4033213 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 45259984 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32684202 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 8542569 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 4033213 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 45259984 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014353 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015937 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.077140 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.020247 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014353 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015937 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.077140 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.020247 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014353 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015937 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.077140 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.020247 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.757474 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.979706 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6534.228395 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.757474 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.979706 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6534.228395 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.757474 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.979706 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6534.228395 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 3311 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.638191 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.ReadReq_mshr_hits::total 23827 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 23827 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 23827 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 23827 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 23827 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136142 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287296 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 423438 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 136142 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 287296 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 423438 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 136142 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 287296 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 423438 # number of overall MSHR misses
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system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3387046990 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4949787990 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1562741000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3387046990 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4949787990 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1562741000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3387046990 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4949787990 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009356 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009356 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009356 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.522409 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.522409 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.522409 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 629918 # number of replacements
system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use
system.cpu0.dcache.total_refs 23229670 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 630430 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 36.847342 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 495.731477 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 9.808064 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data 6.457575 # Average occupied blocks per requestor
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system.cpu0.dcache.occ_percent::cpu1.data 0.019156 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data 0.012612 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
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system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73575 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 238748 # number of LoadLockedReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 247396 # number of StoreCondReq hits
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system.cpu0.dcache.overall_hits::cpu1.data 3267799 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6567439 # number of overall hits
system.cpu0.dcache.overall_hits::total 22740527 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::total 515759 # number of ReadReq misses
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system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3901 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 12005 # number of LoadLockedReq misses
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system.cpu0.dcache.overall_misses::total 1300704 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::total 4955257500 # number of ReadReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52022500 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.StoreCondReq_miss_latency::total 77000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.demand_miss_latency::total 23448185899 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::total 23448185899 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::total 13824794 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu2.data 2709029 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35914 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77476 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 250753 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137363 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35914 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74124 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13243403 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 3362131 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 24041231 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13243403 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 3362131 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7435697 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24041231 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023846 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032878 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059436 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.037307 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027489 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021165 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216802 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.076832 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046424 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048087 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050351 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000067 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025531 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028057 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116769 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.054103 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028057 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116769 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.054103 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13954.531478 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.601074 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9607.699526 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24682.982211 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30255.936926 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23559.521239 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.619572 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13335.683158 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6216.576426 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15400 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 18027.303598 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18027.303598 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 9913 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3463 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.061243 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 76.955556 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.writebacks::writebacks 597795 # number of writebacks
system.cpu0.dcache.writebacks::total 597795 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143860 # number of ReadReq MSHR hits
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system.cpu0.dcache.WriteReq_mshr_hits::total 535045 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 436 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 436 # number of LoadLockedReq MSHR hits
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system.cpu0.dcache.ReadReq_mshr_misses::total 202119 # number of ReadReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280597500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13851108534 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15131706034 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28752682000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42856172534 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71608854534 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032878 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029000 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014620 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021165 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019298 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007984 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048087 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044724 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020706 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000067 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11954.531478 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12995.622802 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12660.583617 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22682.982211 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26629.640793 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25212.557818 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.619572 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11591.486291 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11424.884438 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 2193182 # DTB read hits
system.cpu1.dtb.read_misses 2113 # DTB read misses
system.cpu1.dtb.write_hits 1470431 # DTB write hits
system.cpu1.dtb.write_misses 386 # DTB write misses
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1737 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 73 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 2195295 # DTB read accesses
system.cpu1.dtb.write_accesses 1470817 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 3663613 # DTB hits
system.cpu1.dtb.misses 2499 # DTB misses
system.cpu1.dtb.accesses 3666112 # DTB accesses
system.cpu1.itb.inst_hits 8542569 # ITB inst hits
system.cpu1.itb.inst_misses 1142 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 843 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 8543711 # ITB inst accesses
system.cpu1.itb.hits 8542569 # DTB hits
system.cpu1.itb.misses 1142 # DTB misses
system.cpu1.itb.accesses 8543711 # DTB accesses
system.cpu1.numCycles 574622770 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 8323313 # Number of instructions committed
system.cpu1.committedOps 10568521 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 9455667 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses
system.cpu1.num_func_calls 319891 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1162179 # number of instructions that are conditional controls
system.cpu1.num_int_insts 9455667 # number of integer instructions
system.cpu1.num_fp_insts 2078 # number of float instructions
system.cpu1.num_int_register_reads 54536858 # number of times the integer registers were read
system.cpu1.num_int_register_writes 10267786 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
system.cpu1.num_mem_refs 3838385 # number of memory refs
system.cpu1.num_load_insts 2289184 # Number of load instructions
system.cpu1.num_store_insts 1549201 # Number of store instructions
system.cpu1.num_idle_cycles 539990839.742371 # Number of idle cycles
system.cpu1.num_busy_cycles 34631930.257629 # Number of busy cycles
system.cpu1.not_idle_fraction 0.060269 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.939731 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 4693263 # Number of BP lookups
system.cpu2.branchPred.condPredicted 3812182 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 221977 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 3118720 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 2512857 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 80.573344 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 412180 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 21663 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 10844301 # DTB read hits
system.cpu2.dtb.read_misses 26001 # DTB read misses
system.cpu2.dtb.write_hits 3253591 # DTB write hits
system.cpu2.dtb.write_misses 6154 # DTB write misses
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 3046 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 434 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 10870302 # DTB read accesses
system.cpu2.dtb.write_accesses 3259745 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 14097892 # DTB hits
system.cpu2.dtb.misses 32155 # DTB misses
system.cpu2.dtb.accesses 14130047 # DTB accesses
system.cpu2.itb.inst_hits 4034633 # ITB inst hits
system.cpu2.itb.inst_misses 4571 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 1620 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 986 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 4039204 # ITB inst accesses
system.cpu2.itb.hits 4034633 # DTB hits
system.cpu2.itb.misses 4571 # DTB misses
system.cpu2.itb.accesses 4039204 # DTB accesses
system.cpu2.numCycles 88320298 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9410725 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 32093241 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 4693263 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 2925037 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 6776745 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 1793565 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 51693 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles 19502883 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 35787 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 57273 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 4033217 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 303741 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2092 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 37067906 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.039760 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.425875 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 30296325 81.73% 81.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 382563 1.03% 82.76% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 507321 1.37% 84.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 805393 2.17% 86.31% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 652342 1.76% 88.07% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 346651 0.94% 89.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 996850 2.69% 91.69% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 239087 0.64% 92.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 2841374 7.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 37067906 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.053139 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.363373 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 10025306 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 19435128 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 6133360 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 293839 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1179201 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 610191 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 53369 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36416807 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 180085 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 1179201 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 10595473 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 6672537 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 11193536 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 5837719 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1588398 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 34213134 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2954 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 427229 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 898663 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents 11044 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 36672264 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 156364458 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 156337893 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 26565 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 25643428 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 11028835 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 232388 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 208734 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3368643 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6480999 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3820565 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 539245 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 769553 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 31495381 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 514788 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 34101978 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 55239 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 7293710 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 19517466 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 157489 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 37067906 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.919987 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.574944 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 24513061 66.13% 66.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3940276 10.63% 76.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 2351629 6.34% 83.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 1969211 5.31% 88.42% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 2763009 7.45% 95.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 888704 2.40% 98.27% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 473497 1.28% 99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 133879 0.36% 99.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 34640 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 37067906 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 16450 1.07% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 1406460 91.72% 92.80% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 110474 7.20% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 61347 0.18% 0.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 19254237 56.46% 56.64% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 25603 0.08% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 363 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.72% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 11339596 33.25% 89.97% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3420808 10.03% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 34101978 # Type of FU issued
system.cpu2.iq.rate 0.386117 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1533384 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.044965 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 106886012 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 39309169 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 27255453 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 6518 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 3637 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3015 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 35570601 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 3414 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 207005 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1561439 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1810 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 9237 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 573725 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 5369512 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 345439 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 1179201 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 4914537 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 93208 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 32084127 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 61095 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6480999 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3820565 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 371831 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 32634 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 9237 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 106581 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 88238 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 194819 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 33130261 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 11055368 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 971717 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 73958 # number of nop insts executed
system.cpu2.iew.exec_refs 14443007 # number of memory reference insts executed
system.cpu2.iew.exec_branches 3675866 # Number of branches executed
system.cpu2.iew.exec_stores 3387639 # Number of stores executed
system.cpu2.iew.exec_rate 0.375115 # Inst execution rate
system.cpu2.iew.wb_sent 32719575 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 27258468 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 15578435 # num instructions producing a value
system.cpu2.iew.wb_consumers 28336805 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.308632 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.549760 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 7236388 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 357299 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 169355 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 35888560 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.684756 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.712853 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 27290790 76.04% 76.04% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4165435 11.61% 87.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1253109 3.49% 91.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 644489 1.80% 92.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 571851 1.59% 94.53% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 314297 0.88% 95.41% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 396110 1.10% 96.51% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 285595 0.80% 97.31% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 966884 2.69% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 35888560 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 19876644 # Number of instructions committed
system.cpu2.commit.committedOps 24574906 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 8166400 # Number of memory references committed
system.cpu2.commit.loads 4919560 # Number of loads committed
system.cpu2.commit.membars 94646 # Number of memory barriers committed
system.cpu2.commit.branches 3146883 # Number of branches committed
system.cpu2.commit.fp_insts 2975 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 21821277 # Number of committed integer instructions.
system.cpu2.commit.function_calls 294032 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 966884 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 66205278 # The number of ROB reads
system.cpu2.rob.rob_writes 64842405 # The number of ROB writes
system.cpu2.timesIdled 359398 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 51252392 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 3567238209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 19827262 # Number of Instructions Simulated
system.cpu2.committedOps 24525524 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 19827262 # Number of Instructions Simulated
system.cpu2.cpi 4.454488 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 4.454488 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.224493 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.224493 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 153057849 # number of integer regfile reads
system.cpu2.int_regfile_writes 29069811 # number of integer regfile writes
system.cpu2.fp_regfile_reads 22288 # number of floating regfile reads
system.cpu2.fp_regfile_writes 20782 # number of floating regfile writes
system.cpu2.misc_regfile_reads 9001591 # number of misc regfile reads
system.cpu2.misc_regfile_writes 241415 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981127238281 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 981127238281 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981127238281 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 981127238281 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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