fce3433b2e
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
578 lines
66 KiB
Plaintext
578 lines
66 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000017 # Number of seconds simulated
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sim_ticks 16783500 # Number of ticks simulated
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final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 84096 # Simulator instruction rate (inst/s)
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host_op_rate 84062 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 264753473 # Simulator tick rate (ticks/s)
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host_mem_usage 230292 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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sim_insts 5327 # Number of instructions simulated
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sim_ops 5327 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 423 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27072 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 16708000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 423 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2673172 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests
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system.physmem.totBusLat 2115000 # Total cycles spent in databus access
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system.physmem.totBankLat 8208750 # Total cycles spent in bank access
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system.physmem.avgQLat 6319.56 # Average queueing delay per request
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system.physmem.avgBankLat 19406.03 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 30725.58 # Average memory access latency
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system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 12.60 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.77 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 300 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 39498.82 # Average gap between requests
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system.cpu.branchPred.lookups 1636 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 584 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 33568 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 1472 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3957 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
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system.cpu.activity 18.604028 # Percentage of cycles cpu is active
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system.cpu.comLoads 715 # Number of Load instructions committed
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system.cpu.comStores 673 # Number of Store instructions committed
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system.cpu.comBranches 1115 # Number of Branches instructions committed
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system.cpu.comNops 173 # Number of Nop instructions committed
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system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2526 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
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system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use
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system.cpu.icache.total_refs 895 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits
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system.cpu.icache.overall_hits::total 895 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 362 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 914 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|