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regressions: x86: stats updates due to new x87 insts

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This commit is contained in:
Nilay Vaish 2013-03-11 17:45:09 -05:00
parent 5c940fec0a
commit 53a0597805
71 changed files with 3223 additions and 3198 deletions
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21
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -503,6 +503,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -535,6 +536,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=64
mem_sched_policy=fcfs
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false

1
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/si
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:48:34
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -42,4 +42,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 607445544000 because target called exit()
Exiting @ tick 607412415000 because target called exit()

1005
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -77,7 +77,7 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -128,6 +128,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:52:14
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:35
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -41,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 963992671500 because target called exit()
Exiting @ tick 963992672000 because target called exit()

62
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992671500 # Number of ticks simulated
final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 963992672000 # Number of ticks simulated
final_tick 963992672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 911190 # Simulator instruction rate (inst/s)
host_op_rate 1678916 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 998130396 # Simulator tick rate (ticks/s)
host_mem_usage 284224 # Number of bytes of host memory used
host_seconds 965.80 # Real time elapsed on the host
host_inst_rate 595979 # Simulator instruction rate (inst/s)
host_op_rate 1098124 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 652844357 # Simulator tick rate (ticks/s)
host_mem_usage 283988 # Number of bytes of host memory used
host_seconds 1476.60 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
sim_ops 1621493928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452911 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586471 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory
system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558817 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory
system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9846686433 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959167 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686433 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686433 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740222 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740222 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686433 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699389 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 9846686428 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959163 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686428 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686428 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740221 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740221 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985344 # number of cpu cycles simulated
system.cpu.numCycles 1927985345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354438 # number of integer instructions
system.cpu.num_int_insts 1621354440 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read
system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228179 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
system.cpu.num_mem_refs 607228180 # number of memory refs
system.cpu.num_load_insts 419042122 # Number of load instructions
system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1927985344 # Number of busy cycles
system.cpu.num_busy_cycles 1927985345 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -168,6 +168,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -200,6 +201,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:22:44
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@ -41,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1800193397000 because target called exit()
Exiting @ tick 1800193398000 because target called exit()

76
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.800193 # Number of seconds simulated
sim_ticks 1800193397000 # Number of ticks simulated
final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 1800193398000 # Number of ticks simulated
final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 575805 # Simulator instruction rate (inst/s)
host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1177876462 # Simulator tick rate (ticks/s)
host_mem_usage 292800 # Number of bytes of host memory used
host_seconds 1528.34 # Real time elapsed on the host
host_inst_rate 392596 # Simulator instruction rate (inst/s)
host_op_rate 723379 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 803099848 # Simulator tick rate (ticks/s)
host_mem_usage 292568 # Number of bytes of host memory used
host_seconds 2241.56 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
sim_ops 1621493928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 25668 # To
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3600386794 # number of cpu cycles simulated
system.cpu.numCycles 3600386796 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354438 # number of integer instructions
system.cpu.num_int_insts 1621354440 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read
system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228179 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
system.cpu.num_mem_refs 607228180 # number of memory refs
system.cpu.num_load_insts 419042122 # Number of load instructions
system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3600386794 # Number of busy cycles
system.cpu.num_busy_cycles 3600386796 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 660.197306 # Cycle average of tags in use
system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use
system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 660.197306 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
@ -136,12 +136,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2532 # number of replacements
system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 22211.029315 # Cycle average of tags in use
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21021.301355 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 21021.301343 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy
@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4094.905740 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786132 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 1372.670235 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 771788000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.905740 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 418844796 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844796 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 606786132 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 606786132 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 606786132 # number of overall hits
system.cpu.dcache.overall_hits::total 606786132 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 6851581000
system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 419042122 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042122 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 607228180 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 607228180 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 607228180 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228180 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses

21
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -503,6 +503,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -535,6 +536,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=64
mem_sched_policy=fcfs
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false

1
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:36:34
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 65982862500 because target called exit()
Exiting @ tick 66030660000 because target called exit()

1157
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -77,7 +77,7 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -128,6 +128,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:49:17
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 168950039500 because target called exit()
Exiting @ tick 168950040000 because target called exit()

62
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950039500 # Number of ticks simulated
final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 951900 # Simulator instruction rate (inst/s)
host_op_rate 1676143 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1017943887 # Simulator tick rate (ticks/s)
host_mem_usage 420484 # Number of bytes of host memory used
host_seconds 165.97 # Real time elapsed on the host
host_inst_rate 540700 # Simulator instruction rate (inst/s)
host_op_rate 952086 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 578214744 # Simulator tick rate (ticks/s)
host_mem_usage 420252 # Number of bytes of host memory used
host_seconds 292.19 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10308191209 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245314255 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553505464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191209 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191209 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319681 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319681 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191209 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900080 # number of cpu cycles simulated
system.cpu.numCycles 337900081 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186173 # number of integer instructions
system.cpu.num_int_insts 278186175 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219136 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 337900080 # Number of busy cycles
system.cpu.num_busy_cycles 337900081 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -168,6 +168,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -200,6 +201,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:31:05
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 365989064000 because target called exit()
Exiting @ tick 365989065000 because target called exit()

78
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.365989 # Number of seconds simulated
sim_ticks 365989064000 # Number of ticks simulated
final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 365989065000 # Number of ticks simulated
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 496442 # Simulator instruction rate (inst/s)
host_op_rate 874155 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1150035399 # Simulator tick rate (ticks/s)
host_mem_usage 428932 # Number of bytes of host memory used
host_seconds 318.24 # Real time elapsed on the host
host_inst_rate 284823 # Simulator instruction rate (inst/s)
host_op_rate 501527 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 659807143 # Simulator tick rate (ticks/s)
host_mem_usage 428704 # Number of bytes of host memory used
host_seconds 554.69 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 140419 # To
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 731978128 # number of cpu cycles simulated
system.cpu.numCycles 731978130 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186173 # number of integer instructions
system.cpu.num_int_insts 278186175 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219136 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 731978128 # Number of busy cycles
system.cpu.num_busy_cycles 731978130 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use
system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 318 # number of replacements
system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
@ -274,22 +274,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
@ -306,14 +306,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 28097140000
system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses

21
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -503,6 +503,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -535,6 +536,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=64
mem_sched_policy=fcfs
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false

1
tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

8
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -3,14 +3,15 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:49:19
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *********info: Increasing stack size by one page.
info: Increasing stack size by one page.
****************************************
58924 words stored in 3784810 bytes
@ -24,7 +25,6 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
@ -81,4 +81,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 434474519000 because target called exit()
Exiting @ tick 434778577000 because target called exit()

1309
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -77,7 +77,7 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -128,6 +128,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:35:03
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -71,4 +71,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 885229327500 because target called exit()
Exiting @ tick 885229328000 because target called exit()

60
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885229 # Number of seconds simulated
sim_ticks 885229327500 # Number of ticks simulated
final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 885229328000 # Number of ticks simulated
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 978383 # Simulator instruction rate (inst/s)
host_op_rate 1809140 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1047426540 # Simulator tick rate (ticks/s)
host_mem_usage 293648 # Number of bytes of host memory used
host_seconds 845.15 # Real time elapsed on the host
host_inst_rate 607816 # Simulator instruction rate (inst/s)
host_op_rate 1123920 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 650709398 # Simulator tick rate (ticks/s)
host_mem_usage 293412 # Number of bytes of host memory used
host_seconds 1360.41 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory
system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102186 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449251 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9654872760 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2581992694 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236865453 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654872760 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654872760 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120443518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120443518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654872760 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 9654872754 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236865449 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654872754 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654872754 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120443517 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120443517 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308971 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458656 # number of cpu cycles simulated
system.cpu.numCycles 1770458657 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317560 # number of integer instructions
system.cpu.num_int_insts 1528317562 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 533262342 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1770458656 # Number of busy cycles
system.cpu.num_busy_cycles 1770458657 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -168,6 +168,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -200,6 +201,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:08:30
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@ -71,4 +71,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 1647872848000 because target called exit()
Exiting @ tick 1647872849000 because target called exit()

76
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.647873 # Number of seconds simulated
sim_ticks 1647872848000 # Number of ticks simulated
final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 1647872849000 # Number of ticks simulated
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 579757 # Simulator instruction rate (inst/s)
host_op_rate 1072035 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1155389699 # Simulator tick rate (ticks/s)
host_mem_usage 301076 # Number of bytes of host memory used
host_seconds 1426.25 # Real time elapsed on the host
host_inst_rate 379189 # Simulator instruction rate (inst/s)
host_op_rate 701163 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 755680972 # Simulator tick rate (ticks/s)
host_mem_usage 300836 # Number of bytes of host memory used
host_seconds 2180.65 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 73248 # To
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3295745696 # number of cpu cycles simulated
system.cpu.numCycles 3295745698 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317560 # number of integer instructions
system.cpu.num_int_insts 1528317562 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 533262342 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3295745696 # Number of busy cycles
system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1253 # number of replacements
@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 348459 # number of replacements
system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor
system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
@ -274,22 +274,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits
system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
@ -306,14 +306,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 48668884500
system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses

3
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
View file

@ -77,7 +77,7 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -128,6 +128,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 17:13:04
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -26,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2846007227000 because target called exit()
Exiting @ tick 2846007227500 because target called exit()

54
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007227000 # Number of ticks simulated
final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1019064 # Simulator instruction rate (inst/s)
host_op_rate 1587794 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 964157561 # Simulator tick rate (ticks/s)
host_mem_usage 283172 # Number of bytes of host memory used
host_seconds 2951.81 # Real time elapsed on the host
host_inst_rate 922936 # Simulator instruction rate (inst/s)
host_op_rate 1438019 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 873209138 # Simulator tick rate (ticks/s)
host_mem_usage 283960 # Number of bytes of host memory used
host_seconds 3259.25 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862595 # Number of ops (including micro ops) simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 11281019511 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253378 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019511 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019511 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019511 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998589 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014455 # number of cpu cycles simulated
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862525 # number of integer instructions
system.cpu.num_int_insts 4686862527 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713083 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5692014455 # Number of busy cycles
system.cpu.num_busy_cycles 5692014456 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
View file

@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -168,6 +168,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -200,6 +201,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:35:45
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@ -26,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 5882580525000 because target called exit()
Exiting @ tick 5882580526000 because target called exit()

74
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.882581 # Number of seconds simulated
sim_ticks 5882580525000 # Number of ticks simulated
final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 5882580526000 # Number of ticks simulated
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 639726 # Simulator instruction rate (inst/s)
host_op_rate 996751 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1251043124 # Simulator tick rate (ticks/s)
host_mem_usage 291744 # Number of bytes of host memory used
host_seconds 4702.14 # Real time elapsed on the host
host_inst_rate 579739 # Simulator instruction rate (inst/s)
host_op_rate 903286 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1133733281 # Simulator tick rate (ticks/s)
host_mem_usage 291512 # Number of bytes of host memory used
host_seconds 5188.68 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862595 # Number of ops (including micro ops) simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 7344 # To
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11765161050 # number of cpu cycles simulated
system.cpu.numCycles 11765161052 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862525 # number of integer instructions
system.cpu.num_int_insts 4686862527 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713083 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11765161050 # Number of busy cycles
system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926197 # number of replacements
system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor
system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits
system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 200710756000
system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses

21
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -503,6 +503,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -535,6 +536,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=64
mem_sched_policy=fcfs
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false

1
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 19:08:30
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 82648140000 because target called exit()
122 123 124 Exiting @ tick 82877188500 because target called exit()

1148
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
View file

@ -77,7 +77,7 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -128,6 +128,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:05:52
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:35
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 131393067500 because target called exit()
122 123 124 Exiting @ tick 131393068000 because target called exit()

62
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393067500 # Number of ticks simulated
final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 131393068000 # Number of ticks simulated
final_tick 131393068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 897941 # Simulator instruction rate (inst/s)
host_op_rate 1505028 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 893330062 # Simulator tick rate (ticks/s)
host_mem_usage 308196 # Number of bytes of host memory used
host_seconds 147.08 # Real time elapsed on the host
host_inst_rate 538543 # Simulator instruction rate (inst/s)
host_op_rate 902645 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 535777601 # Simulator tick rate (ticks/s)
host_mem_usage 308992 # Number of bytes of host memory used
host_seconds 245.24 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
sim_ops 221362963 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423750 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378686 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory
system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 56682004 # Number of read requests responded to by this memory
system.physmem.num_reads::total 230176371 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory
system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10563380264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362558055 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925938319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563380264 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563380264 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759721901 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759721901 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563380264 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122279956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685660219 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 10563380223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362558061 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925938285 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563380223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563380223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759721898 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759721898 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786136 # number of cpu cycles simulated
system.cpu.numCycles 262786137 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses
system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339552 # number of integer instructions
system.cpu.num_int_insts 220339554 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read
system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written
system.cpu.num_int_register_reads 616958558 # number of times the integer registers were read
system.cpu.num_int_register_writes 257597203 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165303 # number of memory refs
system.cpu.num_load_insts 56649586 # Number of load instructions
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 262786136 # Number of busy cycles
system.cpu.num_busy_cycles 262786137 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
View file

@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -168,6 +168,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -200,6 +201,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:30:54
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 250953956000 because target called exit()
122 123 124 Exiting @ tick 250953957000 because target called exit()

76
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.250954 # Number of seconds simulated
sim_ticks 250953956000 # Number of ticks simulated
final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 250953957000 # Number of ticks simulated
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 580885 # Simulator instruction rate (inst/s)
host_op_rate 973614 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1103763503 # Simulator tick rate (ticks/s)
host_mem_usage 316652 # Number of bytes of host memory used
host_seconds 227.36 # Real time elapsed on the host
host_inst_rate 308460 # Simulator instruction rate (inst/s)
host_op_rate 517006 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 586117013 # Simulator tick rate (ticks/s)
host_mem_usage 316420 # Number of bytes of host memory used
host_seconds 428.16 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
sim_ops 221362963 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
@ -28,35 +28,35 @@ system.physmem.bw_total::cpu.inst 724276 # To
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 501907912 # number of cpu cycles simulated
system.cpu.numCycles 501907914 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses
system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339552 # number of integer instructions
system.cpu.num_int_insts 220339554 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read
system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written
system.cpu.num_int_register_reads 616958558 # number of times the integer registers were read
system.cpu.num_int_register_writes 257597203 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165303 # number of memory refs
system.cpu.num_load_insts 56649586 # Number of load instructions
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 501907912 # Number of busy cycles
system.cpu.num_busy_cycles 501907914 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2836 # number of replacements
system.cpu.icache.tagsinuse 1455.296648 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use
system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1455.296648 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1829.978587 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 228.178363 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
@ -265,22 +265,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 41 # number of replacements
system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use
system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
@ -297,14 +297,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 104356500
system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses

1
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
View file

@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 18:48:24
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:21:58
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 15014000 because target called exit()
Exiting @ tick 15471000 because target called exit()

589
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000015 # Number of seconds simulated
sim_ticks 15468000 # Number of ticks simulated
final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 15471000 # Number of ticks simulated
final_tick 15471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 31901 # Simulator instruction rate (inst/s)
host_op_rate 57781 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 91692634 # Simulator tick rate (ticks/s)
host_mem_usage 241568 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_inst_rate 25126 # Simulator instruction rate (inst/s)
host_op_rate 45518 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 72243012 # Simulator tick rate (ticks/s)
host_mem_usage 287412 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19392 # Nu
system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1253685027 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 604085855 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1857770882 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1253685027 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1253685027 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1253685027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 604085855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1857770882 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1253441924 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 603968716 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1857410639 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1253441924 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1253441924 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1253441924 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 603968716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1857410639 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 451 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 15452000 # Total gap between requests
system.physmem.totGap 15455000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
@ -157,9 +157,9 @@ system.physmem.avgQLat 4211.75 # Av
system.physmem.avgBankLat 19969.51 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29181.26 # Average memory access latency
system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s
system.physmem.avgRdBW 1857.41 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1857.41 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 14.51 # Data bus utilization in percentage
@ -169,318 +169,319 @@ system.physmem.readRowHits 333 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 34261.64 # Average gap between requests
system.cpu.branchPred.lookups 2995 # Number of BP lookups
system.cpu.branchPred.condPredicted 2995 # Number of conditional branches predicted
system.physmem.avgGap 34268.29 # Average gap between requests
system.cpu.branchPred.lookups 2992 # Number of BP lookups
system.cpu.branchPred.condPredicted 2992 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 2485 # Number of BTB lookups
system.cpu.branchPred.BTBLookups 2482 # Number of BTB lookups
system.cpu.branchPred.BTBHits 793 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 31.911469 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 31.950040 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 30937 # number of cpu cycles simulated
system.cpu.numCycles 30943 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 8904 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14405 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2995 # Number of branches that fetch encountered
system.cpu.fetch.icacheStallCycles 8896 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2992 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3911 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2416 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 3684 # Number of cycles fetch has spent blocked
system.cpu.fetch.Cycles 3908 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2410 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 3707 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched
system.cpu.fetch.CacheLines 1872 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 18552 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.371173 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.873073 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 18558 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.369490 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.871739 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 14740 79.45% 79.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 189 1.02% 80.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 154 0.83% 81.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 193 1.04% 82.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 163 0.88% 83.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 168 0.91% 84.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 265 1.43% 85.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 160 0.86% 86.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2520 13.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 14749 79.48% 79.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 190 1.02% 80.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 168 0.91% 84.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 264 1.42% 85.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 160 0.86% 86.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2518 13.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 18552 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.096810 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.465624 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 9434 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3628 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3523 # Number of cycles decode is running
system.cpu.fetch.rateDist::total 18558 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.096694 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.464952 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3518 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1823 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 24308 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1823 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9778 # Number of cycles rename is idle
system.cpu.decode.SquashCycles 1817 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 24275 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1817 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9777 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3309 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 767 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 22819 # Number of instructions processed by rename
system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3304 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 22769 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 24896 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 54742 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 54726 # Number of integer rename lookups
system.cpu.rename.LSQFullEvents 649 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 24875 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 54688 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 54672 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 13835 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2054 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2204 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1750 # Number of stores inserted to the mem dependence unit.
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 13812 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 34 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2061 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 20351 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 17307 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9863 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 18552 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.932891 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.792260 # Number of insts issued each cycle
system.cpu.iq.iqInstsAdded 20301 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 17266 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9813 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 13640 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 18558 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.930380 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.788216 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 13164 70.96% 70.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1399 7.54% 78.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1053 5.68% 84.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 693 3.74% 87.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 728 3.92% 91.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 621 3.35% 95.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 594 3.20% 98.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 258 1.39% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 13171 70.97% 70.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1403 7.56% 78.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1055 5.68% 84.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 693 3.73% 87.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 728 3.92% 91.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 621 3.35% 95.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 18552 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 18558 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 134 76.57% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 20 11.43% 88.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 21 12.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 20 11.56% 87.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 21 12.14% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 13916 80.41% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1905 11.01% 91.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1482 8.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 13880 80.39% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1903 11.02% 91.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 17307 # Type of FU issued
system.cpu.iq.rate 0.559427 # Inst issue rate
system.cpu.iq.fu_busy_cnt 175 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010112 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 53542 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 30256 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 15949 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 17266 # Type of FU issued
system.cpu.iq.rate 0.557994 # Inst issue rate
system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010020 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 53460 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 30157 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 15915 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 17474 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 17432 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 160 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 1149 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 815 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedStores 813 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1823 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 1817 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 20386 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispatchedInsts 20337 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2204 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1750 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 607 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 16378 # Number of executed instructions
system.cpu.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 662 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 16344 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 929 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecSquashedInsts 922 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3145 # number of memory reference insts executed
system.cpu.iew.exec_branches 1625 # Number of branches executed
system.cpu.iew.exec_stores 1365 # Number of stores executed
system.cpu.iew.exec_rate 0.529398 # Inst execution rate
system.cpu.iew.wb_sent 16147 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 15953 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10136 # num instructions producing a value
system.cpu.iew.wb_consumers 15661 # num instructions consuming a value
system.cpu.iew.exec_refs 3142 # number of memory reference insts executed
system.cpu.iew.exec_branches 1619 # Number of branches executed
system.cpu.iew.exec_stores 1362 # Number of stores executed
system.cpu.iew.exec_rate 0.528197 # Inst execution rate
system.cpu.iew.wb_sent 16113 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 15919 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10115 # num instructions producing a value
system.cpu.iew.wb_consumers 15622 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.515661 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.647213 # average fanout of values written-back
system.cpu.iew.wb_rate 0.514462 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.647484 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 10639 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 10589 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 16729 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.582581 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.458500 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 16741 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.582223 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.458057 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 13195 78.88% 78.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1327 7.93% 86.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 13206 78.88% 78.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1328 7.93% 86.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 118 0.71% 98.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 118 0.70% 98.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 16729 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 16741 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 1987 # Number of memory references committed
system.cpu.commit.loads 1052 # Number of loads committed
system.cpu.commit.refs 1988 # Number of memory references committed
system.cpu.commit.loads 1053 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1208 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9652 # Number of committed integer instructions.
system.cpu.commit.int_insts 9654 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 36893 # The number of ROB reads
system.cpu.rob.rob_writes 42622 # The number of ROB writes
system.cpu.rob.rob_reads 36856 # The number of ROB reads
system.cpu.rob.rob_writes 42518 # The number of ROB writes
system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
system.cpu.cpi 5.750372 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.750372 # CPI: Total CPI of All Threads
system.cpu.ipc 0.173902 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.173902 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 28821 # number of integer regfile reads
system.cpu.int_regfile_writes 17168 # number of integer regfile writes
system.cpu.cpi 5.751487 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.751487 # CPI: Total CPI of All Threads
system.cpu.ipc 0.173868 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.173868 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 28772 # number of integer regfile reads
system.cpu.int_regfile_writes 17143 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.misc_regfile_reads 7143 # number of misc regfile reads
system.cpu.misc_regfile_reads 7129 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 144.824422 # Cycle average of tags in use
system.cpu.icache.total_refs 1475 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 144.801510 # Cycle average of tags in use
system.cpu.icache.total_refs 1474 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 4.848684 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 144.824422 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070715 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070715 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits
system.cpu.icache.overall_hits::total 1475 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses
system.cpu.icache.overall_misses::total 399 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20611500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20611500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20611500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20611500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20611500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20611500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51657.894737 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51657.894737 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51657.894737 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51657.894737 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 144.801510 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070704 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070704 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits
system.cpu.icache.overall_hits::total 1474 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses
system.cpu.icache.overall_misses::total 398 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20575500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20575500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20575500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20575500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20575500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20575500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1872 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1872 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1872 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1872 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1872 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1872 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212607 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.212607 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.212607 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.212607 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.212607 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.212607 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51697.236181 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51697.236181 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51697.236181 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51697.236181 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51697.236181 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51697.236181 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
@ -489,12 +490,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
@ -507,12 +508,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000
system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162393 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.162393 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.162393 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency
@ -521,16 +522,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316
system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 177.956413 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 144.938671 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 33.017743 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004423 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005431 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -646,22 +647,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use
system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 83.486269 # Cycle average of tags in use
system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 15.643836 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 83.496642 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020385 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020385 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits
system.cpu.dcache.occ_blocks::cpu.data 83.486269 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020382 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020382 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
system.cpu.dcache.overall_hits::total 2284 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 2285 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2285 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2285 # number of overall hits
system.cpu.dcache.overall_hits::total 2285 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
@ -678,22 +679,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 10866500
system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1553 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1553 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2487 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2487 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2487 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2487 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081830 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081830 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2488 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2488 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2488 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2488 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081777 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081777 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.081624 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081624 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081624 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081624 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.081592 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081592 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081592 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081592 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency
@ -732,14 +733,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000
system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046392 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046392 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046362 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046362 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.059509 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.059509 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.059486 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.059486 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency

3
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
View file

@ -77,7 +77,7 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -128,6 +128,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
View file

@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:30:54
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:21:58
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 5614500 because target called exit()
Exiting @ tick 5615000 because target called exit()

62
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 5614500 # Number of ticks simulated
final_tick 5614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 59484 # Simulator instruction rate (inst/s)
host_op_rate 107725 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 62039506 # Simulator tick rate (ticks/s)
host_mem_usage 277020 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_inst_rate 54091 # Simulator instruction rate (inst/s)
host_op_rate 97967 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56419373 # Simulator tick rate (ticks/s)
host_mem_usage 276792 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory
system.physmem.bytes_read::total 61976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory
system.physmem.bytes_read::total 61978 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory
system.physmem.bytes_written::total 7112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7917 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory
system.physmem.num_writes::total 935 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9780390061 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1258170808 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11038560869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9780390061 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9780390061 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1266720100 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1266720100 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9780390061 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2524890907 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12305280969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 11230 # number of cpu cycles simulated
system.cpu.numCycles 11231 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9653 # number of integer instructions
system.cpu.num_int_insts 9655 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
system.cpu.num_int_register_reads 24822 # number of times the integer registers were read
system.cpu.num_int_register_writes 11063 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1987 # number of memory refs
system.cpu.num_load_insts 1052 # Number of load instructions
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11230 # Number of busy cycles
system.cpu.num_busy_cycles 11231 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

67
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
View file

@ -1,24 +1,24 @@
Real time: Jan/23/2013 16:34:52
Real time: Mar/11/2013 13:21:59
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.54
Virtual_time_in_minutes: 0.009
Virtual_time_in_hours: 0.00015
Virtual_time_in_days: 6.25e-06
Virtual_time_in_seconds: 0.6
Virtual_time_in_minutes: 0.01
Virtual_time_in_hours: 0.000166667
Virtual_time_in_days: 6.94444e-06
Ruby_current_time: 121759
Ruby_start_time: 0
Ruby_cycles: 121759
mbytes_resident: 66.3984
mbytes_total: 290.648
resident_ratio: 0.22849
mbytes_resident: 66.582
mbytes_total: 163.426
resident_ratio: 0.407486
ruby_cycles_executed: [ 121760 ]
@ -29,17 +29,17 @@ Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8852 average: 1 | standard deviation: 0 | 0 8852 ]
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8853 average: 1 | standard deviation: 0 | 0 8853 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 1 max: 125 count: 8851 average: 12.7565 | standard deviation: 22.8681 | 0 0 0 7474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0877 | standard deviation: 28.194 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66404 | standard deviation: 18.01 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency: [binsize: 1 max: 125 count: 8852 average: 12.755 | standard deviation: 22.8655 | 0 0 0 7475 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD: [binsize: 1 max: 101 count: 1045 average: 33.0842 | standard deviation: 31.8534 | 0 0 0 546 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0845 | standard deviation: 28.1878 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.6639 | standard deviation: 18.0088 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 7474 average: 3 | standard deviation: 0 | 0 0 0 7474 ]
miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7124 | standard deviation: 6.32886 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 7475 average: 3 | standard deviation: 0 | 0 0 0 7475 ]
miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7095 | standard deviation: 6.31582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -50,12 +50,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1376
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average: 3 | standard deviation: 0 | 0 0 0 545 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 546 average: 3 | standard deviation: 0 | 0 0 0 546 ]
miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ]
miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9016 | standard deviation: 6.43269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.8898 | standard deviation: 6.41669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ]
miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4045 | standard deviation: 5.68761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4029 | standard deviation: 5.66282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
@ -72,7 +72,6 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1377 average: 0 | standard deviation: 0 | 1377 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1373 average: 0 | standard deviation: 0 | 1373 ]
@ -89,7 +88,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 13733
page_reclaims: 14769
page_faults: 0
swaps: 0
block_inputs: 0
@ -152,7 +151,7 @@ Cache Stats: system.ruby.l1_cntrl0.cacheMemory
--- L1Cache ---
- Event Counts -
Load [1044 ] 1044
Load [1045 ] 1045
Ifetch [6864 ] 6864
Store [943 ] 943
Data [1377 ] 1377
@ -171,7 +170,7 @@ I Replacement [0 ] 0
II Writeback_Nack [0 ] 0
M Load [545 ] 545
M Load [546 ] 546
M Ifetch [6241 ] 6241
M Store [688 ] 688
M Fwd_GETX [0 ] 0
@ -194,18 +193,18 @@ Memory controller: system.ruby.dir_cntrl0.memBuffer:
memory_reads: 1377
memory_writes: 1373
memory_refreshes: 846
memory_total_request_delays: 1964
memory_delays_per_request: 0.714182
memory_total_request_delays: 1968
memory_delays_per_request: 0.715636
memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 4
memory_delays_stalled_at_head_of_bank_queue: 1960
memory_stalls_for_bank_busy: 826
memory_delays_behind_head_of_bank_queue: 3
memory_delays_stalled_at_head_of_bank_queue: 1965
memory_stalls_for_bank_busy: 823
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 62
memory_stalls_for_bus: 1041
memory_stalls_for_arbitration: 65
memory_stalls_for_bus: 1044
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 31
memory_stalls_for_read_write_turnaround: 33
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54

5
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
View file

@ -1,7 +1,6 @@
Warning: rounding error > tolerance
warn: rounding error > tolerance
0.072760 rounded to 0
Warning: rounding error > tolerance
warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

4
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 16:34:52
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:21:58
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second

26
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 0.000122 # Nu
sim_ticks 121759 # Number of ticks simulated
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 20307 # Simulator instruction rate (inst/s)
host_op_rate 36781 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 459428 # Simulator tick rate (ticks/s)
host_mem_usage 167176 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
host_inst_rate 25458 # Simulator instruction rate (inst/s)
host_op_rate 46114 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 575943 # Simulator tick rate (ticks/s)
host_mem_usage 167352 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -22,19 +22,19 @@ system.cpu.numCycles 121759 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9653 # number of integer instructions
system.cpu.num_int_insts 9655 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
system.cpu.num_int_register_reads 24822 # number of times the integer registers were read
system.cpu.num_int_register_writes 11063 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1987 # number of memory refs
system.cpu.num_load_insts 1052 # Number of load instructions
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 121759 # Number of busy cycles

4
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
View file

@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@ -168,6 +168,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@ -200,6 +201,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave

1
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

6
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
View file

@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 23 2013 19:18:31
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:21:58
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 28357000 because target called exit()
Exiting @ tick 28358000 because target called exit()

122
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
sim_ticks 28357000 # Number of ticks simulated
final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 28358000 # Number of ticks simulated
final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 55225 # Simulator instruction rate (inst/s)
host_op_rate 100013 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 290910277 # Simulator tick rate (ticks/s)
host_mem_usage 285604 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 48918 # Simulator instruction rate (inst/s)
host_op_rate 88604 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 257715326 # Simulator tick rate (ticks/s)
host_mem_usage 285372 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
@ -19,46 +19,46 @@ system.physmem.bytes_inst_read::total 14528 # Nu
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 512324999 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 302429735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 814754734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 512324999 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 512324999 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 512324999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 302429735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 814754734 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 56714 # number of cpu cycles simulated
system.cpu.numCycles 56716 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9653 # number of integer instructions
system.cpu.num_int_insts 9655 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
system.cpu.num_int_register_reads 24822 # number of times the integer registers were read
system.cpu.num_int_register_writes 11063 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1987 # number of memory refs
system.cpu.num_load_insts 1052 # Number of load instructions
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 56714 # Number of busy cycles
system.cpu.num_busy_cycles 56716 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 105.553131 # Cycle average of tags in use
system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use
system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 105.553131 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.051540 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.051540 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
@ -129,16 +129,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 105.561241 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 28.476285 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -254,22 +254,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
system.cpu.dcache.overall_hits::total 1853 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
system.cpu.dcache.overall_hits::total 1854 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
@ -286,22 +286,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7370000
system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
@ -334,14 +334,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000
system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency