update stats for preceeding changes
This commit is contained in:
Ali Saidi
parent
ddd6af414c
commit
1dbf9bb4ca
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@ -11,14 +11,15 @@ type=LinuxAlphaSystem
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children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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console=/dist/m5/system/binaries/console
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clock=1000
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console=/projects/pd/randd/dist/binaries/console
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init_param=0
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kernel=/dist/m5/system/binaries/vmlinux
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kernel=/projects/pd/randd/dist/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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memories=system.physmem
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num_work_ids=16
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pal=/dist/m5/system/binaries/ts_osfpal
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pal=/projects/pd/randd/dist/binaries/ts_osfpal
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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@ -34,18 +35,17 @@ system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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clock=1000
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delay=50000
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nack_delay=4000
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ranges=8796093022208:18446744073709551615
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req_size=16
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resp_size=16
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write_ack=false
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master=system.iobus.slave[0]
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slave=system.membus.master[0]
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[system.cpu0]
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type=DerivO3CPU
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children=dcache dtb fuPool icache interrupts itb tracer
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children=dcache dtb fuPool icache interrupts isa itb tracer
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BTBEntries=4096
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BTBTagSize=16
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LFSTSize=1024
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@ -93,6 +93,7 @@ iewToFetchDelay=1
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iewToRenameDelay=1
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instShiftAmt=2
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interrupts=system.cpu0.interrupts
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isa=system.cpu0.isa
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issueToExecuteDelay=1
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issueWidth=8
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itb=system.cpu0.itb
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@ -111,7 +112,6 @@ numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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phase=0
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predType=tournament
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profile=0
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progress_interval=0
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@ -145,16 +145,18 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=32768
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subblock_size=0
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system=system
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@ -437,16 +439,18 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=32768
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subblock_size=0
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system=system
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@ -460,6 +464,9 @@ mem_side=system.toL2Bus.slave[0]
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[system.cpu0.interrupts]
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type=AlphaInterrupts
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[system.cpu0.isa]
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type=AlphaISA
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[system.cpu0.itb]
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type=AlphaTLB
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size=48
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@ -469,7 +476,7 @@ type=ExeTracer
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[system.cpu1]
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type=DerivO3CPU
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children=dcache dtb fuPool icache interrupts itb tracer
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children=dcache dtb fuPool icache interrupts isa itb tracer
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BTBEntries=4096
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BTBTagSize=16
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LFSTSize=1024
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@ -517,6 +524,7 @@ iewToFetchDelay=1
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iewToRenameDelay=1
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instShiftAmt=2
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interrupts=system.cpu1.interrupts
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isa=system.cpu1.isa
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issueToExecuteDelay=1
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issueWidth=8
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itb=system.cpu1.itb
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@ -535,7 +543,6 @@ numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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phase=0
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predType=tournament
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profile=0
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progress_interval=0
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@ -569,16 +576,18 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=32768
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subblock_size=0
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system=system
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@ -861,16 +870,18 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=32768
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subblock_size=0
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system=system
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@ -884,6 +895,9 @@ mem_side=system.toL2Bus.slave[2]
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[system.cpu1.interrupts]
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type=AlphaInterrupts
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[system.cpu1.isa]
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type=AlphaISA
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[system.cpu1.itb]
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type=AlphaTLB
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size=48
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@ -908,7 +922,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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image_file=/dist/m5/system/disks/linux-latest.img
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image_file=/projects/pd/randd/dist/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -928,7 +942,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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image_file=/dist/m5/system/disks/linux-bigswap2.img
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image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -951,16 +965,18 @@ type=BaseCache
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addr_ranges=0:8589934591
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assoc=8
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block_size=64
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clock=1000
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forward_snoops=false
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hash_delay=1
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hit_latency=50
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is_top_level=true
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latency=50000
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max_miss_count=0
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=50
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size=1024
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subblock_size=0
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system=system
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@ -976,20 +992,22 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=8
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=20
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is_top_level=false
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latency=10000
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max_miss_count=0
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mshrs=92
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=20
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size=4194304
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subblock_size=0
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system=system
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tgts_per_mshr=16
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tgts_per_mshr=12
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trace_addr=0
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two_queue=false
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write_buffers=8
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@ -1010,9 +1028,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side
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[system.membus.badaddr_responder]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=0
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=true
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ret_data16=65535
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@ -1025,14 +1044,28 @@ warn_access=
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pio=system.membus.default
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[system.physmem]
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type=SimpleMemory
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type=SimpleDRAM
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addr_mapping=openmap
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banks_per_rank=8
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clock=1000
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conf_table_reported=false
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file=
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in_addr_map=true
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latency=30000
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latency_var=0
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lines_per_rowbuffer=64
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mem_sched_policy=fcfs
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null=false
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page_policy=open
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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tBURST=4000
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tCL=14000
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tRCD=14000
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tREFI=7800000
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tRFC=300000
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tRP=14000
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tWTR=1000
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write_buffer_size=32
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write_thresh_perc=70
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zero=false
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port=system.membus.master[1]
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@ -1044,7 +1077,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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image_file=/dist/m5/system/disks/linux-latest.img
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image_file=/projects/pd/randd/dist/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -1057,7 +1090,7 @@ port=3456
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[system.toL2Bus]
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type=CoherentBus
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block_size=64
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clock=1000
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clock=500
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header_cycles=1
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use_default_range=false
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width=8
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@ -1072,10 +1105,11 @@ system=system
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[system.tsunami.backdoor]
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type=AlphaBackdoor
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clock=1000
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cpu=system.cpu0
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disk=system.simple_disk
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pio_addr=8804682956800
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pio_latency=1000
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pio_latency=100000
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platform=system.tsunami
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system=system
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terminal=system.terminal
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@ -1083,8 +1117,9 @@ pio=system.iobus.master[24]
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[system.tsunami.cchip]
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type=TsunamiCChip
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clock=1000
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pio_addr=8803072344064
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pio_latency=1000
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pio_latency=100000
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system=system
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tsunami=system.tsunami
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pio=system.iobus.master[0]
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@ -1140,12 +1175,10 @@ dma_write_delay=0
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dma_write_factor=0
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hardware_address=00:90:00:00:00:01
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intr_delay=10000000
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max_backoff_delay=10000000
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min_backoff_delay=4000
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pci_bus=0
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pci_dev=1
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pci_func=0
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pio_latency=1000
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pio_latency=30000
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platform=system.tsunami
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rss=false
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rx_delay=1000000
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@ -1162,9 +1195,10 @@ pio=system.iobus.master[27]
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[system.tsunami.fake_OROM]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8796093677568
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pio_latency=1000
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pio_latency=100000
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pio_size=393216
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ret_bad_addr=false
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ret_data16=65535
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@ -1178,9 +1212,10 @@ pio=system.iobus.master[8]
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[system.tsunami.fake_ata0]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848432
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1194,9 +1229,10 @@ pio=system.iobus.master[19]
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[system.tsunami.fake_ata1]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848304
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1210,9 +1246,10 @@ pio=system.iobus.master[20]
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[system.tsunami.fake_pnp_addr]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848569
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1226,9 +1263,10 @@ pio=system.iobus.master[9]
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[system.tsunami.fake_pnp_read0]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848451
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1242,9 +1280,10 @@ pio=system.iobus.master[11]
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[system.tsunami.fake_pnp_read1]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848515
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1258,9 +1297,10 @@ pio=system.iobus.master[12]
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[system.tsunami.fake_pnp_read2]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848579
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1274,9 +1314,10 @@ pio=system.iobus.master[13]
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[system.tsunami.fake_pnp_read3]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848643
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1290,9 +1331,10 @@ pio=system.iobus.master[14]
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[system.tsunami.fake_pnp_read4]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848707
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1306,9 +1348,10 @@ pio=system.iobus.master[15]
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[system.tsunami.fake_pnp_read5]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848771
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1322,9 +1365,10 @@ pio=system.iobus.master[16]
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[system.tsunami.fake_pnp_read6]
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type=IsaFake
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clock=1000
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fake_mem=false
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pio_addr=8804615848835
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pio_latency=1000
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pio_latency=100000
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pio_size=8
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ret_bad_addr=false
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ret_data16=65535
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@ -1338,9 +1382,10 @@ pio=system.iobus.master[17]
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[system.tsunami.fake_pnp_read7]
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type=IsaFake
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clock=1000
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fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1354,9 +1399,10 @@ pio=system.iobus.master[18]
|
|||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1370,9 +1416,10 @@ pio=system.iobus.master[10]
|
|||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1386,9 +1433,10 @@ pio=system.iobus.master[7]
|
|||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1402,9 +1450,10 @@ pio=system.iobus.master[2]
|
|||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1418,9 +1467,10 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1434,9 +1484,10 @@ pio=system.iobus.master[4]
|
|||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1450,9 +1501,10 @@ pio=system.iobus.master[5]
|
|||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1466,9 +1518,10 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clock=1000
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1512,16 +1565,15 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
|
|
@ -1530,9 +1582,10 @@ pio=system.iobus.master[25]
|
|||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clock=1000
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
|
|
@ -1541,8 +1594,9 @@ pio=system.iobus.master[22]
|
|||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clock=1000
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
|
@ -1550,7 +1604,8 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
clock=1000
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
|
|
@ -1558,8 +1613,9 @@ pio=system.iobus.default
|
|||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clock=1000
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 26 2012 21:20:05
|
||||
gem5 started Jul 26 2012 22:30:48
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 13:40:49
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 112168000
|
||||
Exiting @ tick 1900530295500 because m5_exit instruction encountered
|
||||
info: Launching CPU 1 @ 107840000
|
||||
Exiting @ tick 1897857556000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,17 +8,18 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
clock=1000
|
||||
console=/projects/pd/randd/dist/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
pal=/projects/pd/randd/dist/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
|
@ -34,18 +35,17 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb tracer
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -93,6 +93,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -111,7 +112,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -145,16 +145,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -163,7 +165,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -437,16 +439,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -455,15 +459,55 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
|
|
@ -484,7 +528,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -504,7 +548,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -527,16 +571,18 @@ type=BaseCache
|
|||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -547,31 +593,6 @@ write_buffers=8
|
|||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
|
|
@ -582,13 +603,14 @@ use_default_range=false
|
|||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
|
|
@ -601,14 +623,28 @@ warn_access=
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -620,7 +656,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -630,16 +666,6 @@ number=0
|
|||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
|
|
@ -648,10 +674,11 @@ system=system
|
|||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
clock=1000
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
|
|
@ -659,8 +686,9 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clock=1000
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -716,12 +744,10 @@ dma_write_delay=0
|
|||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
|
|
@ -738,9 +764,10 @@ pio=system.iobus.master[27]
|
|||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -754,9 +781,10 @@ pio=system.iobus.master[8]
|
|||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -770,9 +798,10 @@ pio=system.iobus.master[19]
|
|||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -786,9 +815,10 @@ pio=system.iobus.master[20]
|
|||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -802,9 +832,10 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -818,9 +849,10 @@ pio=system.iobus.master[11]
|
|||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -834,9 +866,10 @@ pio=system.iobus.master[12]
|
|||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -850,9 +883,10 @@ pio=system.iobus.master[13]
|
|||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -866,9 +900,10 @@ pio=system.iobus.master[14]
|
|||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -882,9 +917,10 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -898,9 +934,10 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -914,9 +951,10 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -930,9 +968,10 @@ pio=system.iobus.master[18]
|
|||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -946,9 +985,10 @@ pio=system.iobus.master[10]
|
|||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -962,9 +1002,10 @@ pio=system.iobus.master[7]
|
|||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -978,9 +1019,10 @@ pio=system.iobus.master[2]
|
|||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -994,9 +1036,10 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1010,9 +1053,10 @@ pio=system.iobus.master[4]
|
|||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1026,9 +1070,10 @@ pio=system.iobus.master[5]
|
|||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
|
|
@ -1042,9 +1087,10 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clock=1000
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1088,16 +1134,15 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
|
|
@ -1106,9 +1151,10 @@ pio=system.iobus.master[25]
|
|||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clock=1000
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
|
|
@ -1117,8 +1163,9 @@ pio=system.iobus.master[22]
|
|||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clock=1000
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
|
@ -1126,7 +1173,8 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
clock=1000
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
|
|
@ -1134,8 +1182,9 @@ pio=system.iobus.default
|
|||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clock=1000
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 26 2012 21:20:05
|
||||
gem5 started Jul 26 2012 22:30:38
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 13:34:06
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1864423957500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1854349611000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1
|
||||
clock=1000
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
|
|
@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1
|
||||
clock=1000
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -69,7 +70,7 @@ read_only=true
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=checker dcache dtb fuPool icache interrupts itb tracer
|
||||
children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -167,7 +168,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
type=O3Checker
|
||||
children=dtb itb tracer
|
||||
checker=Null
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
|
|
@ -200,10 +201,10 @@ walker=system.cpu.checker.dtb.walker
|
|||
|
||||
[system.cpu.checker.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[5]
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.checker.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -213,10 +214,10 @@ walker=system.cpu.checker.itb.walker
|
|||
|
||||
[system.cpu.checker.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[4]
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.checker.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -226,10 +227,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -237,7 +238,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -246,7 +247,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -256,10 +257,10 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
|
|
@ -529,10 +530,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -540,7 +541,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -549,7 +550,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -562,10 +563,47 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -589,18 +627,18 @@ type=BaseCache
|
|||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
hit_latency=50000
|
||||
is_top_level=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50000
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -611,33 +649,6 @@ write_buffers=8
|
|||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=10000
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=10000
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
|
|
@ -648,11 +659,11 @@ use_default_range=false
|
|||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -668,15 +679,28 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
|
|
@ -691,7 +715,7 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1
|
||||
clock=1000
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -700,7 +724,7 @@ pio=system.membus.master[5]
|
|||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -747,7 +771,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1
|
||||
clock=1000
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -778,7 +802,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -787,7 +811,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -804,7 +828,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
clock=1
|
||||
clock=1000
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -818,7 +842,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -828,7 +852,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -838,7 +862,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -848,7 +872,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -862,7 +886,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -875,7 +899,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -904,7 +928,7 @@ pio=system.membus.master[6]
|
|||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -914,7 +938,7 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
|
|
@ -926,7 +950,7 @@ port=system.membus.master[1]
|
|||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1
|
||||
clock=1000
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -938,7 +962,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -951,7 +975,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -961,7 +985,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -971,7 +995,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -981,7 +1005,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -991,7 +1015,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1
|
||||
clock=1000
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1005,7 +1029,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1
|
||||
clock=1000
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1018,7 +1042,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1
|
||||
clock=1000
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1033,7 +1057,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1043,7 +1067,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1053,7 +1077,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1063,7 +1087,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1077,16 +1101,6 @@ number=0
|
|||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
|
|
|
|||
|
|
@ -10,34 +10,27 @@ warn: instruction 'mcr icialluis' unimplemented
|
|||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
|
||||
warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc
|
||||
warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
|
||||
warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:35:22
|
||||
gem5 compiled Nov 1 2012 15:18:10
|
||||
gem5 started Nov 2 2012 01:09:00
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2537929870500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2523500318000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -12,9 +12,10 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview
|
|||
atags_addr=256
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1
|
||||
clock=1000
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
|
|
@ -23,7 +24,6 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -39,7 +39,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1
|
||||
clock=1000
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -69,7 +69,7 @@ read_only=true
|
|||
|
||||
[system.cpu0]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb tracer
|
||||
children=dcache dtb fuPool icache interrupts isa itb tracer
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -117,6 +117,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu0.interrupts
|
||||
isa=system.cpu0.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu0.itb
|
||||
|
|
@ -168,10 +169,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -179,7 +180,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -198,7 +199,7 @@ walker=system.cpu0.dtb.walker
|
|||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -471,10 +472,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -482,7 +483,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -496,6 +497,23 @@ mem_side=system.toL2Bus.slave[0]
|
|||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -504,7 +522,7 @@ walker=system.cpu0.itb.walker
|
|||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
|
@ -514,7 +532,7 @@ type=ExeTracer
|
|||
|
||||
[system.cpu1]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb tracer
|
||||
children=dcache dtb fuPool icache interrupts isa itb tracer
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -562,6 +580,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu1.interrupts
|
||||
isa=system.cpu1.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu1.itb
|
||||
|
|
@ -613,10 +632,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -624,7 +643,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -643,7 +662,7 @@ walker=system.cpu1.dtb.walker
|
|||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
|
@ -916,10 +935,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -927,7 +946,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -941,6 +960,23 @@ mem_side=system.toL2Bus.slave[4]
|
|||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -949,7 +985,7 @@ walker=system.cpu1.itb.walker
|
|||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
|
@ -976,18 +1012,18 @@ type=BaseCache
|
|||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
hit_latency=50000
|
||||
is_top_level=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50000
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -1003,22 +1039,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=10000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=10000
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -1039,7 +1075,7 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
|||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -1055,15 +1091,28 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
|
|
@ -1078,7 +1127,7 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1
|
||||
clock=1000
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1087,7 +1136,7 @@ pio=system.membus.master[5]
|
|||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -1134,7 +1183,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1
|
||||
clock=1000
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -1165,7 +1214,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -1174,7 +1223,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -1191,7 +1240,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
clock=1
|
||||
clock=1000
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -1205,7 +1254,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -1215,7 +1264,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -1225,7 +1274,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -1235,7 +1284,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -1249,7 +1298,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -1262,7 +1311,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -1291,7 +1340,7 @@ pio=system.membus.master[6]
|
|||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -1301,7 +1350,7 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
|
|
@ -1313,7 +1362,7 @@ port=system.membus.master[1]
|
|||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1
|
||||
clock=1000
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -1325,7 +1374,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1338,7 +1387,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1348,7 +1397,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1358,7 +1407,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1368,7 +1417,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1378,7 +1427,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1
|
||||
clock=1000
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1392,7 +1441,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1
|
||||
clock=1000
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1405,7 +1454,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1
|
||||
clock=1000
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1420,7 +1469,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1430,7 +1479,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1440,7 +1489,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1450,7 +1499,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1467,7 +1516,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented
|
|||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:18:35
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 21:14:52
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2616878893500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2593146078000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1
|
||||
clock=1000
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
|
|
@ -23,7 +24,6 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -39,7 +39,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1
|
||||
clock=1000
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -69,7 +69,7 @@ read_only=true
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb tracer
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -117,6 +117,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -168,10 +169,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -179,7 +180,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -188,7 +189,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -198,10 +199,10 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
|
|
@ -471,10 +472,10 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -482,7 +483,7 @@ prefetch_on_access=false
|
|||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -491,11 +492,28 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -504,10 +522,47 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -531,18 +586,18 @@ type=BaseCache
|
|||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
hit_latency=50000
|
||||
is_top_level=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50000
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -553,33 +608,6 @@ write_buffers=8
|
|||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=10000
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=10000
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
|
|
@ -590,11 +618,11 @@ use_default_range=false
|
|||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -610,15 +638,28 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
|
|
@ -633,7 +674,7 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1
|
||||
clock=1000
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -642,7 +683,7 @@ pio=system.membus.master[5]
|
|||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -689,7 +730,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1
|
||||
clock=1000
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -720,7 +761,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -729,7 +770,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -746,7 +787,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
clock=1
|
||||
clock=1000
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -760,7 +801,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -770,7 +811,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -780,7 +821,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -790,7 +831,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -804,7 +845,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -817,7 +858,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -846,7 +887,7 @@ pio=system.membus.master[6]
|
|||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -856,7 +897,7 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
|
|
@ -868,7 +909,7 @@ port=system.membus.master[1]
|
|||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1
|
||||
clock=1000
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -880,7 +921,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -893,7 +934,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -903,7 +944,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -913,7 +954,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -923,7 +964,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -933,7 +974,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1
|
||||
clock=1000
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -947,7 +988,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1
|
||||
clock=1000
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -960,7 +1001,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1
|
||||
clock=1000
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -975,7 +1016,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -985,7 +1026,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -995,7 +1036,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1005,7 +1046,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1
|
||||
clock=1000
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1019,16 +1060,6 @@ number=0
|
|||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
|
|
|
|||
|
|
@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented
|
|||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:10:34
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 21:11:31
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2537929870500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2523500318000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,15 +8,15 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxX86System
|
||||
children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||
children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
|
||||
acpi_description_table_pointer=system.acpi_description_table_pointer
|
||||
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
clock=1
|
||||
clock=1000
|
||||
e820_table=system.e820_table
|
||||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
|
|
@ -52,7 +52,7 @@ oem_table_id=
|
|||
|
||||
[system.apicbridge]
|
||||
type=Bridge
|
||||
clock=1
|
||||
clock=1000
|
||||
delay=50000
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
|
|
@ -62,7 +62,7 @@ slave=system.iobus.master[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1
|
||||
clock=1000
|
||||
delay=50000
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
|
|
@ -72,7 +72,7 @@ slave=system.membus.master[1]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb dtb_walker_cache fuPool icache interrupts itb itb_walker_cache tracer
|
||||
children=dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -120,6 +120,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -171,17 +172,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -190,7 +192,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -200,7 +202,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.dtb_walker_cache.cpu_side
|
||||
|
||||
|
|
@ -209,17 +211,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -228,7 +231,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dtb.walker.port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
mem_side=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
|
|
@ -498,17 +501,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -517,11 +521,11 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -530,6 +534,9 @@ int_master=system.membus.slave[4]
|
|||
int_slave=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -538,7 +545,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.itb_walker_cache.cpu_side
|
||||
|
||||
|
|
@ -547,17 +554,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -566,7 +574,44 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.itb.walker.port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
mem_side=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[3]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -950,17 +995,18 @@ type=BaseCache
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -971,32 +1017,6 @@ write_buffers=8
|
|||
cpu_side=system.iobus.master[18]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[3]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
|
|
@ -1007,11 +1027,11 @@ use_default_range=false
|
|||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
|
||||
slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -1034,7 +1054,7 @@ system=system
|
|||
|
||||
[system.pc.behind_pci]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854779128
|
||||
pio_latency=100000
|
||||
|
|
@ -1052,7 +1072,7 @@ pio=system.iobus.master[12]
|
|||
[system.pc.com_1]
|
||||
type=Uart8250
|
||||
children=terminal
|
||||
clock=1
|
||||
clock=1000
|
||||
pio_addr=9223372036854776824
|
||||
pio_latency=100000
|
||||
platform=system.pc
|
||||
|
|
@ -1076,7 +1096,7 @@ port=3456
|
|||
|
||||
[system.pc.fake_com_2]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776568
|
||||
pio_latency=100000
|
||||
|
|
@ -1093,7 +1113,7 @@ pio=system.iobus.master[14]
|
|||
|
||||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776808
|
||||
pio_latency=100000
|
||||
|
|
@ -1110,7 +1130,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776552
|
||||
pio_latency=100000
|
||||
|
|
@ -1127,7 +1147,7 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776818
|
||||
pio_latency=100000
|
||||
|
|
@ -1144,7 +1164,7 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
clock=1
|
||||
clock=1000
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854775936
|
||||
pio_latency=100000
|
||||
|
|
@ -1162,7 +1182,7 @@ pio=system.iobus.master[11]
|
|||
[system.pc.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
clock=1
|
||||
clock=1000
|
||||
pio_latency=30000
|
||||
platform=system.pc
|
||||
size=16777216
|
||||
|
|
@ -1185,7 +1205,7 @@ speaker=system.pc.south_bridge.speaker
|
|||
[system.pc.south_bridge.cmos]
|
||||
type=Cmos
|
||||
children=int_pin
|
||||
clock=1
|
||||
clock=1000
|
||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||
pio_addr=9223372036854775920
|
||||
pio_latency=100000
|
||||
|
|
@ -1198,7 +1218,7 @@ type=X86IntSourcePin
|
|||
|
||||
[system.pc.south_bridge.dma1]
|
||||
type=I8237
|
||||
clock=1
|
||||
clock=1000
|
||||
pio_addr=9223372036854775808
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1245,7 +1265,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1
|
||||
clock=1000
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
|
||||
|
|
@ -1277,7 +1297,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/projects/pd/randd/dist/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1297,7 +1317,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
@ -1380,7 +1400,7 @@ number=12
|
|||
[system.pc.south_bridge.io_apic]
|
||||
type=I82094AA
|
||||
apic_id=1
|
||||
clock=1
|
||||
clock=1000
|
||||
external_int_pic=system.pc.south_bridge.pic1
|
||||
int_latency=1000
|
||||
pio_addr=4273995776
|
||||
|
|
@ -1392,7 +1412,7 @@ pio=system.iobus.master[10]
|
|||
[system.pc.south_bridge.keyboard]
|
||||
type=I8042
|
||||
children=keyboard_int_pin mouse_int_pin
|
||||
clock=1
|
||||
clock=1000
|
||||
command_port=9223372036854775908
|
||||
data_port=9223372036854775904
|
||||
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
|
|
@ -1411,7 +1431,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pic1]
|
||||
type=I8259
|
||||
children=output
|
||||
clock=1
|
||||
clock=1000
|
||||
mode=I8259Master
|
||||
output=system.pc.south_bridge.pic1.output
|
||||
pio_addr=9223372036854775840
|
||||
|
|
@ -1426,7 +1446,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pic2]
|
||||
type=I8259
|
||||
children=output
|
||||
clock=1
|
||||
clock=1000
|
||||
mode=I8259Slave
|
||||
output=system.pc.south_bridge.pic2.output
|
||||
pio_addr=9223372036854775968
|
||||
|
|
@ -1441,7 +1461,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pit]
|
||||
type=I8254
|
||||
children=int_pin
|
||||
clock=1
|
||||
clock=1000
|
||||
int_pin=system.pc.south_bridge.pit.int_pin
|
||||
pio_addr=9223372036854775872
|
||||
pio_latency=100000
|
||||
|
|
@ -1453,7 +1473,7 @@ type=X86IntSourcePin
|
|||
|
||||
[system.pc.south_bridge.speaker]
|
||||
type=PcSpeaker
|
||||
clock=1
|
||||
clock=1000
|
||||
i8254=system.pc.south_bridge.pit
|
||||
pio_addr=9223372036854775905
|
||||
pio_latency=100000
|
||||
|
|
@ -1461,15 +1481,28 @@ system=system
|
|||
pio=system.iobus.master[9]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
@ -1494,13 +1527,3 @@ starting_addr_segment=0
|
|||
vendor=
|
||||
version=
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,6 @@ warn: Don't know what interrupt to clear for console.
|
|||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:31:43
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 18:26:17
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5167941639500 because m5_exit instruction encountered
|
||||
Exiting @ tick 5132789913000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -54,8 +55,6 @@ do_quiesce=true
|
|||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
|
|
@ -63,6 +62,7 @@ globalHistoryBits=13
|
|||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -76,7 +76,6 @@ memBlockSize=64
|
|||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -94,20 +93,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -123,20 +124,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -153,22 +159,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -178,10 +186,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -191,12 +199,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -214,18 +222,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:09:56
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 11:21:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -39,4 +39,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 274137499500 because target called exit()
|
||||
Exiting @ tick 269661304500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.269731 # Number of seconds simulated
|
||||
sim_ticks 269730745500 # Number of ticks simulated
|
||||
final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.269661 # Number of seconds simulated
|
||||
sim_ticks 269661304500 # Number of ticks simulated
|
||||
final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 168515 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 168515 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75522303 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 218132 # Number of bytes of host memory used
|
||||
host_seconds 3571.54 # Real time elapsed on the host
|
||||
host_inst_rate 125304 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 125304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56142087 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214336 # Number of bytes of host memory used
|
||||
host_seconds 4803.19 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu
|
|||
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 26294 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1014 # Total number of write requests seen
|
||||
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 74 # Tr
|
|||
system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 269730693500 # Total gap between requests
|
||||
system.physmem.totGap 269661252500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
|
||||
|
|
@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh
|
|||
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
|
|
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 360576187 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 364261179 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 105120000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 554708000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 13720.56 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 21107.61 # Average bank access latency per request
|
||||
system.physmem.totBankLat 554778000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 13860.78 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 21110.27 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 38828.17 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 38971.05 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -187,31 +187,31 @@ system.physmem.peakBW 16000.00 # Th
|
|||
system.physmem.busUtil 0.04 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 12.19 # Average write queue length over time
|
||||
system.physmem.readRowHits 17405 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 17406 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9877350.72 # Average gap between requests
|
||||
system.physmem.avgGap 9874807.84 # Average gap between requests
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114517567 # DTB read hits
|
||||
system.cpu.dtb.read_hits 114517568 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114520198 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453373 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 114520199 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453362 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39455675 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153970940 # DTB hits
|
||||
system.cpu.dtb.write_accesses 39455664 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153970930 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 153975873 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25065868 # ITB hits
|
||||
system.cpu.dtb.data_accesses 153975863 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 24997854 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 25065890 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 24997876 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 539461492 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 539322610 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 155053642 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 154928367 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.593626 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.582759 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
|
|
@ -272,72 +272,72 @@ system.cpu.committedInsts 601856964 # Nu
|
|||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 30 # number of replacements
|
||||
system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25064833 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1035 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24996820 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1034 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -346,158 +346,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786041 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179322 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3731128500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6376983000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6376983000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1042 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 22.846686 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.756059 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.203653 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.592503 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661766 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014514 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698198 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
|
||||
|
|
@ -522,17 +414,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42280500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472681500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 514962000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1146890000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1146890000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42280500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1619571500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1661852000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42280500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1619571500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1661852000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -557,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -589,17 +481,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -611,17 +503,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786016 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179347 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -451,22 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -489,12 +499,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -512,18 +522,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:10:10
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 11:21:56
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -39,4 +39,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 135504709500 because target called exit()
|
||||
Exiting @ tick 133778696500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:54:44
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 18:59:47
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 164735271500 because target called exit()
|
||||
Exiting @ tick 164568389500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
|
@ -451,22 +459,24 @@ size=64
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -494,7 +504,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -516,14 +526,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 17:04:37
|
||||
gem5 started Aug 13 2012 18:13:42
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Oct 30 2012 11:11:57
|
||||
gem5 started Oct 30 2012 14:00:44
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 389171398000 because target called exit()
|
||||
Exiting @ tick 387281648500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,17 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -430,17 +432,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -462,6 +465,9 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -470,30 +476,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -503,10 +510,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -521,7 +528,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:44:55
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 16:17:19
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -20,10 +18,10 @@ Uncompressing Data
|
|||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
info: Increasing stack size by one page.
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
|
|
@ -42,4 +40,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 609566727000 because target called exit()
|
||||
Exiting @ tick 607235830000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 11:53:48
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 19:23:29
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 28505597000 because target called exit()
|
||||
Exiting @ tick 26786364500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,17 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -430,17 +432,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -462,6 +465,9 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -470,30 +476,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -503,10 +510,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -521,9 +528,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 23:05:45
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 16:29:18
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -18,7 +16,6 @@ All Rights Reserved.
|
|||
nodes : 500
|
||||
active arcs : 1905
|
||||
simplex iterations : 1502
|
||||
info: Increasing stack size by one page.
|
||||
flow value : 4990014995
|
||||
new implicit arcs : 23867
|
||||
active arcs : 25772
|
||||
|
|
@ -26,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 64346039000 because target called exit()
|
||||
Exiting @ tick 66000220500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:11:01
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 19:35:49
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 205972871500 because target called exit()
|
||||
Exiting @ tick 206019870500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,17 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -430,17 +432,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -462,6 +465,9 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -470,30 +476,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -503,10 +510,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -521,9 +528,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,17 +1,15 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:33:09
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 16:49:35
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
Reading the dictionary files: *********info: Increasing stack size by one page.
|
||||
**************************************info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -24,7 +22,7 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
****************************************
|
||||
**
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
|
|
@ -82,4 +80,4 @@ Echoing of input sentence turned on.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 433562236500 because target called exit()
|
||||
Exiting @ tick 434496110500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -54,8 +55,6 @@ do_quiesce=true
|
|||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
|
|
@ -63,6 +62,7 @@ globalHistoryBits=13
|
|||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -76,7 +76,6 @@ memBlockSize=64
|
|||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -94,20 +93,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -123,20 +124,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -153,22 +159,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -178,10 +186,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -191,12 +199,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -214,18 +222,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:12:34
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 11:24:52
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.133333
|
||||
Exiting @ tick 141187061500 because target called exit()
|
||||
Exiting @ tick 139846906500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.141089 # Number of seconds simulated
|
||||
sim_ticks 141089296500 # Number of ticks simulated
|
||||
final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.139847 # Number of seconds simulated
|
||||
sim_ticks 139846906500 # Number of ticks simulated
|
||||
final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 83115 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 83115 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29414893 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223012 # Number of bytes of host memory used
|
||||
host_seconds 4796.53 # Real time elapsed on the host
|
||||
host_inst_rate 122154 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 122154 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42850332 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220236 # Number of bytes of host memory used
|
||||
host_seconds 3263.61 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -37,7 +37,7 @@ system.physmem.bytesConsumedWr 0 # by
|
|||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
|
||||
|
|
@ -48,7 +48,7 @@ system.physmem.perBankRdReqs::8 407 # Tr
|
|||
system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 141089244500 # Total gap between requests
|
||||
system.physmem.totGap 139846854500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 39617295 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 39390791 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 29312000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 106246000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5406.29 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14498.64 # Average bank access latency per request
|
||||
system.physmem.totBankLat 105924000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5375.38 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14454.69 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 23904.93 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 23830.08 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 6442 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6444 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 19253444.94 # Average gap between requests
|
||||
system.physmem.avgGap 19083904.82 # Average gap between requests
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754611 # DTB read hits
|
||||
system.cpu.dtb.read_hits 94754613 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754632 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521102 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 94754634 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521103 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73521137 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275713 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73521138 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275716 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275769 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 49091192 # ITB hits
|
||||
system.cpu.itb.fetch_misses 88817 # ITB misses
|
||||
system.cpu.dtb.data_accesses 168275772 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611354 # ITB hits
|
||||
system.cpu.itb.fetch_misses 44520 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 49180009 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 48655874 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 282178594 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 279693814 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168699560 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.273696 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.213631 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -265,245 +265,137 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1982 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49086683 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49086683 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4508 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606847 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4507 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4507 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4507 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4507 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4507 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 195448500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 195448500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 195448500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 195448500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 195448500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 195448500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611354 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611354 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611354 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611354 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 43365.542489 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 67.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3910 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3910 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3910 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3910 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3910 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3910 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172100500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 172100500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172100500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 172100500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172100500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 172100500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 170297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 170297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170297500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 170297500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44015.473146 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44015.473146 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43632.462209 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43632.462209 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3285.555145 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254416 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.703276 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3285.555145 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802137 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802137 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501231 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501231 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254416 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254416 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254416 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254416 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19498 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19498 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20802 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20802 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20802 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20802 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64930000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 64930000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 710139000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 710139000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 775069000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 775069000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 775069000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 775069000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49792.944785 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49792.944785 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36421.120115 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 36421.120115 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37259.350062 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37259.350062 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 15899 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.717757 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16296 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16296 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16650 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16650 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16650 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16650 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48068500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48068500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153897000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 153897000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201965500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 201965500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 201965500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 201965500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50598.421053 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50598.421053 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48062.773267 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48062.773267 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3908.656926 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 760 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3907.773744 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.161119 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.653922 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2910.300742 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.702262 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011311 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088815 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.670185 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2909.388487 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.715072 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088787 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119283 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 551 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_percent::total 0.119256 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 674 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 551 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 544 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 734 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 551 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 727 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 544 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 734 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 727 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
|
||||
|
|
@ -515,52 +407,52 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 162633000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45642500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 208275500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150126000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 150126000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 162633000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 195768500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 358401500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 162633000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 195768500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 358401500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3910 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160908500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45014500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 205923000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151967500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 151967500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 160908500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 196982000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 357890500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 160908500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 196982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 357890500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3910 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3903 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 8062 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3910 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 8055 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3903 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 8062 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859079 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 8055 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.860620 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.861231 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.862474 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859079 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.860620 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.908956 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859079 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.909745 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908956 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48417.088419 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55391.383495 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49790.939517 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47734.817170 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47734.817170 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48908.501638 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48908.501638 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48838.769105 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48838.769105 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -580,39 +472,147 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120134545 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35298214 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155432759 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111138322 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111138322 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120134545 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146436536 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 266571081 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120134545 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146436536 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 266571081 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118404553 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34670717 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153075270 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112966799 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112966799 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118404553 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147637516 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 266042069 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118404553 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147637516 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 266042069 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861231 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.908956 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.908956 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35764.973206 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42837.638350 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37158.202008 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35338.099205 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35338.099205 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254423 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20795 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -451,22 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -489,12 +499,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -512,18 +522,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:15:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 11:29:31
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.066667
|
||||
Exiting @ tick 80362284000 because target called exit()
|
||||
Exiting @ tick 77336466500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 13:21:28
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 19:45:28
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -12,5 +12,5 @@ Eon, Version 1.1
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.070000
|
||||
Exiting @ tick 70907303500 because target called exit()
|
||||
OO-style eon Time= 0.060000
|
||||
Exiting @ tick 68267465500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -451,22 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -489,12 +499,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -512,18 +522,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:41:27
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 12:07:24
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 646278131000 because target called exit()
|
||||
Exiting @ tick 626365181000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:46:31
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 20:00:53
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 653190727500 because target called exit()
|
||||
Exiting @ tick 624867585500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -54,8 +55,6 @@ do_quiesce=true
|
|||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
|
|
@ -63,6 +62,7 @@ globalHistoryBits=13
|
|||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -76,7 +76,6 @@ memBlockSize=64
|
|||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -94,20 +93,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -123,20 +124,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -153,22 +159,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -178,10 +186,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -191,12 +199,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -214,18 +222,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:54:39
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 12:19:26
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 47910283500 because target called exit()
|
||||
Exiting @ tick 43266024500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,64 +1,64 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.043596 # Number of seconds simulated
|
||||
sim_ticks 43595903500 # Number of ticks simulated
|
||||
final_tick 43595903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.043266 # Number of seconds simulated
|
||||
sim_ticks 43266024500 # Number of ticks simulated
|
||||
final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 146921 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 146921 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72505010 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252940 # Number of bytes of host memory used
|
||||
host_seconds 601.28 # Real time elapsed on the host
|
||||
host_inst_rate 113775 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 113775 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55722813 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252752 # Number of bytes of host memory used
|
||||
host_seconds 776.45 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10138304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 454912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 454912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 7108 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158411 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10434742 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 232551758 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 242986500 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10434742 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10434742 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 167350770 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 167350770 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 167350770 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10434742 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 232551758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 410337269 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165519 # Total number of read requests seen
|
||||
system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165517 # Total number of read requests seen
|
||||
system.physmem.writeReqs 113997 # Total number of write requests seen
|
||||
system.physmem.cpureqs 279516 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 10593216 # Total number of bytes read from memory
|
||||
system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 10593088 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10672 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10220 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10695 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 10332 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 10519 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 10219 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 10232 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10218 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 10332 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 9920 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 10624 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 10240 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis
|
||||
|
|
@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 7374 # Tr
|
|||
system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 43595883500 # Total gap between requests
|
||||
system.physmem.totGap 43266004500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165519 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165517 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
|
|
@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 71904 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 70293 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 17020 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 6297 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -138,13 +138,13 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 3115 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 4887 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4930 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
|
||||
|
|
@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4956 # Wh
|
|||
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 1842 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 70 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 9323896604 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11720942604 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 662068000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1734978000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 56331.96 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10482.17 # Average bank access latency per request
|
||||
system.physmem.totBankLat 1734068000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 56247.27 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10476.68 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 70814.13 # Average memory access latency
|
||||
system.physmem.avgRdBW 242.99 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 167.35 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 242.99 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 167.35 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 70723.94 # Average memory access latency
|
||||
system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 2.56 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 2.58 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.27 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.36 # Average write queue length over time
|
||||
system.physmem.readRowHits 151893 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 41557 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 91.77 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 36.45 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 155969.19 # Average gap between requests
|
||||
system.physmem.avgWrQLen 10.35 # Average write queue length over time
|
||||
system.physmem.readRowHits 151965 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 41713 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 154790.12 # Average gap between requests
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20277538 # DTB read hits
|
||||
system.cpu.dtb.read_hits 20277550 # DTB read hits
|
||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20367686 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14728672 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 20367698 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14728696 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14735924 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006210 # DTB hits
|
||||
system.cpu.dtb.write_accesses 14735948 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006246 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35103610 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12476759 # ITB hits
|
||||
system.cpu.itb.fetch_misses 12943 # ITB misses
|
||||
system.cpu.dtb.data_accesses 35103646 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12367278 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11044 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 12489702 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 12378322 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 87191808 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 86532050 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 18827150 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 12439421 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 5024981 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 16201522 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 5047120 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1660945 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.lookups 18742312 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 12317439 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 4774431 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 15498318 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 4661486 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 31.152135 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 8476186 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10350964 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74333119 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.BTBHitPct 30.077367 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126652369 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 65259 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 292889 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14121677 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35064639 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4680318 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 234163 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4914481 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 8857790 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.683882 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44776328 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35060577 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 77836216 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 230753 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16919077 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 70272731 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 80.595566 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 80.401850 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
||||
system.cpu.comStores 14613377 # Number of Store instructions committed
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
|
|
@ -272,302 +272,194 @@ system.cpu.committedInsts 88340673 # Nu
|
|||
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.986995 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.986995 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.013176 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.013176 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 33768817 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 53422991 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.270654 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 44539685 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42652123 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 48.917581 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 44072021 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43119787 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.453943 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65076368 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22115440 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.364126 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 41085926 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46105882 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 52.878686 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 85196 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.917223 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12358549 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 87242 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.658249 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 84282 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.917223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.932088 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.932088 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12358549 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12358549 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12358549 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12358549 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12358549 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12358549 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 118203 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 118203 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 118203 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 118203 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 118203 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 118203 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1846898500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1846898500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1846898500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1846898500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1846898500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1846898500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12476752 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12476752 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12476752 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12476752 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12476752 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12476752 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15624.802247 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15624.802247 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15624.802247 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15624.802247 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12250113 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12250113 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12250113 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117156 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117156 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117156 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117156 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117156 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117156 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1822166500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1822166500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 12.750000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30961 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30961 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30961 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30961 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30961 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30961 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87242 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 87242 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 87242 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 87242 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 87242 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 87242 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1292347500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1292347500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1292347500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1292347500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1292347500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1292347500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006992 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006992 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006992 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14813.363976 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14813.363976 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200251 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.664341 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33754987 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.184647 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 249990000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.664341 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995768 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995768 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180268 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180268 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574719 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574719 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33754987 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33754987 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33754987 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33754987 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96370 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96370 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038658 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038658 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1135028 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1135028 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135028 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135028 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3954988500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3954988500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 91520281000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 91520281000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95475269500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95475269500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95475269500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95475269500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071076 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071076 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032532 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032532 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032532 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032532 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.623327 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.623327 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88113.971105 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 88113.971105 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 84117.105041 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 84117.105041 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 6175044 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 397 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116295 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.098104 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 397 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168353 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168353 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35603 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35603 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895078 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895078 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930681 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930681 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930681 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930681 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1939972500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1939972500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14546837500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14546837500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16486810000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16486810000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16486810000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 16486810000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31924.770023 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31924.770023 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101315.207550 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101315.207550 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 131596 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30981.821005 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 152256 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.930353 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 131593 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30981.522130 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 151339 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163652 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.924761 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27273.690706 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2026.855781 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1681.274518 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.832327 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061855 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945490 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 80134 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33057 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 113191 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168353 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168353 # number of Writeback hits
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27280.254395 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2018.521657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1682.746078 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.832527 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051353 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79223 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33054 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 112277 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168350 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168350 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 80134 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 126070 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 80134 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 126070 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 7108 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 27520 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 34628 # number of ReadReq misses
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 79223 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45933 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 125156 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 79223 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 45933 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 125156 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 7105 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 27521 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 34626 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 130891 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 7108 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158411 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 165519 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7108 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158411 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165519 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 400938500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1545176500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1946115000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14274056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 14274056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 400938500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15819232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 16220171000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 400938500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15819232500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 16220171000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 87242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 147819 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168353 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168353 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 7105 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 165517 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7105 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165517 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 397918500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1540033500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1937952000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14268456500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 14268456500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 397918500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15808490000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 16206408500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 397918500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15808490000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 16206408500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 87242 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 291589 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 87242 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 291589 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081475 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454298 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.234259 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 86328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 290673 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 86328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 290673 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082302 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.235707 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081475 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775206 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.567645 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081475 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775206 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.567645 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56406.654474 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56147.401890 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56200.617997 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109052.998296 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109052.998296 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56406.654474 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99861.957187 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 97995.825253 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56406.654474 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99861.957187 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 97995.825253 # average overall miss latency
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082302 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.569427 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082302 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569427 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56005.418719 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55958.486247 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55968.116444 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109010.218426 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109010.218426 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 97913.860812 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 97913.860812 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -578,50 +470,158 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7108 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27520 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7105 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 34626 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7108 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158411 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7108 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158411 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 310665087 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1192490455 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1503155542 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12652907225 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12652907225 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310665087 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13845397680 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14156062767 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310665087 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13845397680 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14156062767 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454298 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.234259 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7105 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165517 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7105 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165517 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307703601 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1187367459 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1495071060 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12647339647 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12647339647 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307703601 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13834707106 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14142410707 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307703601 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13834707106 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14142410707 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235707 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775206 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.567645 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775206 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.567645 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43706.399409 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43331.775254 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43408.673386 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96667.511326 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96667.511326 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569427 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43308.036735 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43144.052142 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43177.700572 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96624.975338 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96624.975338 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200249 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574731 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574731 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33755002 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33755002 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33755002 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33755002 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038646 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038646 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1135013 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1135013 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135013 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135013 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3942448000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3942448000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 91414151500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 91414151500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95356599500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95356599500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95356599500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95356599500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168350 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -451,22 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -489,12 +499,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -512,18 +522,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 10:05:33
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 12:32:34
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 21619648000 because target called exit()
|
||||
Exiting @ tick 24414646000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 11:57:39
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 20:20:38
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 24260940500 because target called exit()
|
||||
Exiting @ tick 26292466000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -54,8 +55,6 @@ do_quiesce=true
|
|||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
|
|
@ -63,6 +62,7 @@ globalHistoryBits=13
|
|||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -76,7 +76,6 @@ memBlockSize=64
|
|||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -94,20 +93,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -123,20 +124,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -153,22 +159,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -178,10 +186,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -191,12 +199,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -214,18 +222,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 10:10:01
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 12:40:49
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -23,4 +23,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 996061088500 because target called exit()
|
||||
Exiting @ tick 985089830500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,66 +1,66 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.987579 # Number of seconds simulated
|
||||
sim_ticks 987579062500 # Number of ticks simulated
|
||||
final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.985090 # Number of seconds simulated
|
||||
sim_ticks 985089830500 # Number of ticks simulated
|
||||
final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79028 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79028 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42888030 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 458304 # Number of bytes of host memory used
|
||||
host_seconds 23026.92 # Real time elapsed on the host
|
||||
host_inst_rate 109003 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 109003 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59005665 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 485696 # Number of bytes of host memory used
|
||||
host_seconds 16694.83 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959686 # Total number of read requests seen
|
||||
system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959687 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1018055 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 125419904 # Total number of bytes read from memory
|
||||
system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 125419968 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65155520 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis
|
||||
|
|
@ -69,7 +69,7 @@ system.physmem.perBankWrReqs::6 63395 # Tr
|
|||
system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis
|
||||
|
|
@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 65307 # Tr
|
|||
system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 987579010500 # Total gap between requests
|
||||
system.physmem.totGap 985089778500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 1959686 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 1959687 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
|
|
@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -138,9 +138,9 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see
|
||||
|
|
@ -161,9 +161,9 @@ system.physmem.wrQLenPdf::19 44263 # Wh
|
|||
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
|
|
@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 7836436000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 57753850000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 10004.34 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29479.65 # Average bank access latency per request
|
||||
system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 7836420000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 57752478000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 10025.42 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29479.01 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 43483.99 # Average memory access latency
|
||||
system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 43504.43 # Average memory access latency
|
||||
system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 1.21 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.09 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.28 # Average write queue length over time
|
||||
system.physmem.readRowHits 834542 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 194109 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHits 834572 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 194113 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 331653.76 # Average gap between requests
|
||||
system.physmem.avgGap 330817.71 # Average gap between requests
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444784364 # DTB read hits
|
||||
system.cpu.dtb.read_hits 444784566 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449681442 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833165 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 449681644 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833172 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162534469 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605617529 # DTB hits
|
||||
system.cpu.dtb.write_accesses 162534476 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605617738 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 612215911 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232120860 # ITB hits
|
||||
system.cpu.dtb.data_accesses 612216120 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 231916745 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 232120882 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 231916767 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 1975158126 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1970179662 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 326556831 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 252596788 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 138232865 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 218937552 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 135479530 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.BTBHitPct 61.880444 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617988746 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617888959 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.834230 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.773501 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 444595663 # Number of Load instructions committed
|
||||
system.cpu.comStores 160728502 # Number of Store instructions committed
|
||||
system.cpu.comBranches 214632552 # Number of Branches instructions committed
|
||||
|
|
@ -272,72 +272,72 @@ system.cpu.committedInsts 1819780127 # Nu
|
|||
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232119756 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1104 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232120860 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 231915637 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1108 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53230.978261 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54087.545126 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -346,203 +346,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 63
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46993000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46993000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46993000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46993000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46993000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46993000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47313000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47313000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47313000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47313000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47313000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47313000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54706.635623 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54706.635623 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55079.161816 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55079.161816 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107377 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.124534 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593539067 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111473 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.141944 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12681076000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.124534 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996612 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996612 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268755 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268755 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156270312 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156270312 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593539067 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593539067 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593539067 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593539067 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326908 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326908 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4458190 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4458190 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11785098 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11785098 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11785098 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11785098 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 160313092500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 160313092500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195290221000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195290221000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 355603313500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 355603313500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 355603313500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 355603313500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027737 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027737 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21880.047149 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43804.822361 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43804.822361 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30173.980182 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 30173.980182 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9234267 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4818811 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 358092 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65601 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.787415 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 73.456365 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693297 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693297 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568993 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2568993 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2673625 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2673625 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2673625 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2673625 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222276 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222276 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889197 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889197 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111473 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111473 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111473 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111473 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144007395000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144007395000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67943434500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 67943434500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211950829500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 211950829500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211950829500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 211950829500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19939.336990 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19939.336990 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35964.187165 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35964.187165 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926955 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30885.794112 # Cycle average of tags in use
|
||||
system.cpu.l2cache.replacements 1926956 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30892.708902 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8958711 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1956748 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578367 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 67633900002 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15038.473814 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 35.309498 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15812.010801 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458938 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001078 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.482544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.942560 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044303 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044303 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693297 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3693297 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108343 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1108343 # number of ReadExReq hits
|
||||
system.cpu.l2cache.sampled_refs 1956749 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578365 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 67095700002 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.085957 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 35.170225 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15821.452721 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458865 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.482832 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.942771 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044304 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044304 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693296 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3693296 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108342 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1108342 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7152646 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7152646 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7152646 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7152646 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1177531 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1178390 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1177532 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1178391 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1958827 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1959686 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1958828 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1959687 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958827 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959686 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46130000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76211329000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 76257459000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54802656500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 54802656500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46130000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 131013985500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 131060115500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46130000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 131013985500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 131060115500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958828 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959687 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46450000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76219681500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 76266131500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54834553000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 54834553000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46450000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 131054234500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 131100684500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46450000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 131054234500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 131100684500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221834 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222693 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3693297 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3693297 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889639 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889639 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221836 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222695 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3693296 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3693296 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889638 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889638 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111473 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112332 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111474 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112333 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111473 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112332 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111474 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112333 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses
|
||||
|
|
@ -554,17 +446,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54074.505239 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64728.331374 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 64720.565160 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70184.095400 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70184.095400 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66898.787664 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66898.787664 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -576,27 +468,27 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1018055 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177532 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1178391 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958827 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1959686 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958828 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1959687 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958827 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959686 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35264420 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61190782598 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61226047018 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44920930070 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44920930070 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35264420 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106111712668 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 106146977088 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35264420 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106111712668 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 106146977088 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958828 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959687 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35585421 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61199276421 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61234861842 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44953209175 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44953209175 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35585421 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106152485596 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 106188071017 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35585421 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106152485596 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 106188071017 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -608,17 +500,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41426.566938 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51972.495373 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51964.807812 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57536.719982 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57536.719982 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107378 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.173275 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593539212 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111474 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.141953 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12614691000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.173275 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268752 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268752 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156270460 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156270460 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593539212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593539212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593539212 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593539212 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326911 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326911 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4458042 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4458042 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11784953 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11784953 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11784953 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11784953 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 160323624500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 160323624500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195351556000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195351556000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 355675180500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 355675180500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 355675180500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 355675180500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693296 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2568846 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2673479 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2673479 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2673479 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2673479 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222278 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222278 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111474 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111474 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111474 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111474 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144015924000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144015924000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67975303000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 67975303000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -451,22 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -489,12 +499,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -512,18 +522,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 10:10:10
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 12:41:35
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -23,4 +23,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 621254733000 because target called exit()
|
||||
Exiting @ tick 655919824500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 12:45:19
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 20:33:15
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -24,4 +24,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 479173106500 because target called exit()
|
||||
Exiting @ tick 506342716000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -54,8 +55,6 @@ do_quiesce=true
|
|||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
|
|
@ -63,6 +62,7 @@ globalHistoryBits=13
|
|||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -76,7 +76,6 @@ memBlockSize=64
|
|||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -94,20 +93,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -123,20 +124,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -153,22 +159,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -178,10 +186,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -191,12 +199,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -214,18 +222,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 10:35:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
|
||||
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 13:10:16
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 42012413000 because target called exit()
|
||||
122 123 124 Exiting @ tick 41615049000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.041949 # Number of seconds simulated
|
||||
sim_ticks 41948719000 # Number of ticks simulated
|
||||
final_tick 41948719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.041615 # Number of seconds simulated
|
||||
sim_ticks 41615049000 # Number of ticks simulated
|
||||
final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 82495 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 82495 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37654494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221732 # Number of bytes of host memory used
|
||||
host_seconds 1114.04 # Real time elapsed on the host
|
||||
host_inst_rate 117678 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 117678 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53286406 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217828 # Number of bytes of host memory used
|
||||
host_seconds 780.97 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4262728 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3271041 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7533770 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4262728 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4262728 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4262728 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3271041 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7533770 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 41948681000 # Total gap between requests
|
||||
system.physmem.totGap 41614997000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -99,8 +99,8 @@ system.physmem.neitherpktsize::6 0 # ca
|
|||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 991 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 438 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 18563928 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 107349928 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 17845427 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 19752000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 69034000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3759.40 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13980.15 # Average bank access latency per request
|
||||
system.physmem.totBankLat 69230000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3613.90 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14019.85 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 21739.56 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 21633.74 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 4458 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4457 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 8495075.13 # Average gap between requests
|
||||
system.physmem.avgGap 8427500.41 # Average gap between requests
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 19996251 # DTB read hits
|
||||
system.cpu.dtb.read_hits 19996253 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 19996261 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 19996263 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501863 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6501886 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498114 # DTB hits
|
||||
system.cpu.dtb.data_hits 26498116 # DTB hits
|
||||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498147 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 10035746 # ITB hits
|
||||
system.cpu.dtb.data_accesses 26498149 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956935 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 10035795 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 9956984 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 83897439 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 83230099 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 13564910 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 9782241 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 7992573 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 3850501 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 13412629 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 9650146 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 4269214 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 7424481 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 3768497 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 48.175988 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 5999726 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73745307 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.RASInCorrect 126 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 50.757716 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136320779 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206802 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058690 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38528710 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26769089 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 83635742 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10897 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7614848 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 76282591 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.923623 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.841817 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -265,72 +265,72 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.912891 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.912891 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.095421 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.095421 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27675918 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 56221521 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 67.012202 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34449958 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49447481 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 58.938010 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33919397 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49978042 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.570402 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65867839 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18029600 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.490048 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29953374 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53944065 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.297630 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 8127 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.667941 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 10023995 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1001.198062 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65203595 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026504 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.658636 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29370403 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859696 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.711801 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.730683 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945572 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.702941 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.667941 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 10023995 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 10023995 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 10023995 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 10023995 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 10023995 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 10023995 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11751 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11751 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11751 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11751 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11751 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11751 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259062500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259062500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259062500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259062500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259062500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259062500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 10035746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 10035746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 10035746 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 10035746 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 10035746 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 10035746 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22045.996085 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22045.996085 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22045.996085 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22045.996085 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.730683 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728872 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728872 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945572 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945572 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945572 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945572 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945572 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945572 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11363 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11363 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11363 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11363 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11363 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11363 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 253418000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 253418000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 253418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 253418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 253418000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 253418000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956935 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956935 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956935 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956935 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956935 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956935 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22302.032914 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22302.032914 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22302.032914 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -339,171 +339,63 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209799500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209799500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209799500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209799500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209799500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209799500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20954.804235 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20954.804235 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1843 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1843 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1843 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1843 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1843 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1843 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204186500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 204186500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 204186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204186500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 204186500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21448.161765 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21448.161765 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.862848 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488630 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.713000 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.862848 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352017 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488630 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488630 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488630 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488630 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8671 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8671 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8671 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8671 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28479000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 28479000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 330607000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 330607000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 359086000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 359086000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 359086000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 359086000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49528.695652 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49528.695652 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40835.844862 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 40835.844862 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 41412.293853 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 41412.293853 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 11966 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 828 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.451691 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6348 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6348 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6448 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6448 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6448 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6448 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82274500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 82274500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105057500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 105057500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 105057500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 105057500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47964.210526 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47964.210526 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47067.791762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47067.791762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2190.279989 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2190.387059 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.844336 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.341583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.094069 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055583 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839462 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.429033 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.118565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055586 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_percent::total 0.066845 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7297 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6805 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
|
||||
|
|
@ -515,52 +407,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127295000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21759500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 149054500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80257000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 80257000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 127295000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102016500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 229311500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 127295000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102016500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 229311500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127130500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21966500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 149097000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79600500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 79600500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 127130500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101567000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 228697500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 127130500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101567000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 228697500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45560.128848 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51562.796209 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46347.792289 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46606.852497 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46606.852497 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 46438.132847 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 46438.132847 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45501.252684 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52053.317536 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46361.007463 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46225.609756 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46225.609756 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 46313.791009 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 46313.791009 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -580,39 +472,147 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91926812 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16443678 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108370490 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59040867 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59040867 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91926812 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75484545 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 167411357 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91926812 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75484545 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 167411357 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91774816 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16652177 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108426993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58348895 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58348895 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91774816 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75001072 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 166775888 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91774816 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75001072 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 166775888 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.507516 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38966.061611 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33697.291667 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34286.217770 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34286.217770 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32847.106657 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39460.135071 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33714.861007 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33884.375726 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33884.375726 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.892023 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488629 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488629 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8672 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -77,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -95,7 +97,6 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
|
|
@ -129,16 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -421,16 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -451,22 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -476,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -489,12 +499,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -512,18 +522,32 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port[0]
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 10:49:45
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 13:23:29
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 23661066000 because target called exit()
|
||||
122 123 124 Exiting @ tick 23378067000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -432,18 +433,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=3
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=4027589137
|
||||
id_pfr0=49
|
||||
id_pfr1=1
|
||||
midr=890224640
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -540,15 +558,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 21 2012 11:19:00
|
||||
gem5 started Sep 21 2012 13:57:03
|
||||
gem5 compiled Oct 30 2012 11:20:14
|
||||
gem5 started Oct 30 2012 20:48:26
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
|
||||
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
|
||||
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -23,4 +21,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 76020082000 because target called exit()
|
||||
122 123 124 Exiting @ tick 74245032000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,17 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -430,17 +432,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -462,6 +465,9 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -470,30 +476,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -503,10 +510,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -521,7 +528,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:29:07
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 17:50:59
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -26,4 +22,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 84416735500 because target called exit()
|
||||
122 123 124 Exiting @ tick 82887492500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -62,6 +62,7 @@ globalHistoryBits=13
|
|||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -92,22 +93,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -123,22 +124,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -148,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -155,24 +159,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=10000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=10000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -182,10 +186,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -200,7 +204,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -222,15 +226,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 16:51:51
|
||||
gem5 started Aug 13 2012 17:17:12
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 11:20:12
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 21979500 because target called exit()
|
||||
Exiting @ tick 18737000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18769500 # Number of ticks simulated
|
||||
final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 18737000 # Number of ticks simulated
|
||||
final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 10228 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 10227 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30039955 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 216300 # Number of bytes of host memory used
|
||||
host_seconds 0.62 # Real time elapsed on the host
|
||||
host_inst_rate 37767 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 37763 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 110721753 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213516 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
|
|||
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 18755000 # Total gap between requests
|
||||
system.physmem.totGap 18722500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -165,26 +165,26 @@ system.physmem.wrQLenPdf::30 0 # Wh
|
|||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 1862969 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests
|
||||
system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1876000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7924000 # Total cycles spent in bank access
|
||||
system.physmem.totBankLat 7910000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3972.22 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16895.52 # Average bank access latency per request
|
||||
system.physmem.avgBankLat 16865.67 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24867.74 # Average memory access latency
|
||||
system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 24837.89 # Average memory access latency
|
||||
system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.97 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 9.99 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.62 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 401 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 39989.34 # Average gap between requests
|
||||
system.physmem.avgGap 39920.04 # Average gap between requests
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -201,10 +201,10 @@ system.cpu.dtb.data_hits 2048 # DT
|
|||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2058 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 909 # ITB hits
|
||||
system.cpu.itb.fetch_hits 915 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 926 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 932 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 37540 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 37475 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 1605 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 1632 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 1160 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 706 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 1266 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 352 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.BTBHitPct 27.804107 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2181 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 4462 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2152 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 4448 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7397 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 19.704315 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7374 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 19.677118 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1183 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
||||
|
|
@ -265,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu
|
|||
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 556 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 561 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 556 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 353 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17380500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 909 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 909 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 909 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 909 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 909 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.388339 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.388339 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.388339 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.388339 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.388339 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.388339 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49236.543909 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49236.543909 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49236.543909 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49236.543909 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 561 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 354 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -339,46 +339,171 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 51 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 51 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 51 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14765000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14765000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14765000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14765000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14765000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14765000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332233 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.332233 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.332233 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48890.728477 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48890.728477 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 104.285094 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 104.285094 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025460 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025460 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
|
||||
|
|
@ -395,14 +520,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
|
|||
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5354500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14914000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14914000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20268500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20268500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20268500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20268500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -419,14 +544,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55201.030928 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55201.030928 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42611.428571 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42611.428571 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45343.400447 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45343.400447 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -451,14 +576,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3674000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3674000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8753000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8753000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8753000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8753000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -467,139 +592,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53463.157895 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53463.157895 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50328.767123 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50328.767123 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 200.317780 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.356757 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.961023 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004375 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14446500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14446500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8574000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23020500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14446500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8574000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23020500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49050.505051 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49267.123288 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49267.123288 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 49084.221748 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,6 +78,7 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -129,18 +130,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -423,18 +424,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
|
|
@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -455,24 +459,24 @@ size=48
|
|||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -482,10 +486,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
|
|
@ -500,7 +504,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -522,15 +526,28 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 16:51:51
|
||||
gem5 started Aug 13 2012 17:17:12
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Oct 30 2012 11:02:14
|
||||
gem5 started Oct 30 2012 11:20:12
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 12735500 because target called exit()
|
||||
Exiting @ tick 15802500 because target called exit()
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue