628 lines
71 KiB
Plaintext
628 lines
71 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.269661 # Number of seconds simulated
|
|
sim_ticks 269661304500 # Number of ticks simulated
|
|
final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 125304 # Simulator instruction rate (inst/s)
|
|
host_op_rate 125304 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 56142087 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 214336 # Number of bytes of host memory used
|
|
host_seconds 4803.19 # Real time elapsed on the host
|
|
sim_insts 601856964 # Number of instructions simulated
|
|
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 64896 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 26294 # Total number of read requests seen
|
|
system.physmem.writeReqs 1014 # Total number of write requests seen
|
|
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
|
|
system.physmem.bytesRead 1682816 # Total number of bytes read from memory
|
|
system.physmem.bytesWritten 64896 # Total number of bytes written to memory
|
|
system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize()
|
|
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
|
|
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
|
|
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
|
system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis
|
|
system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
|
system.physmem.totGap 269661252500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::6 26294 # Categorize read packet sizes
|
|
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
|
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::6 1014 # categorize write packet sizes
|
|
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
|
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
|
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
|
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
|
system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
|
system.physmem.totQLat 364261179 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 105120000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 554778000 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 13860.78 # Average queueing delay per request
|
|
system.physmem.avgBankLat 21110.27 # Average bank access latency per request
|
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 38971.05 # Average memory access latency
|
|
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.04 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
|
system.physmem.avgWrQLen 12.19 # Average write queue length over time
|
|
system.physmem.readRowHits 17406 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 51 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 9874807.84 # Average gap between requests
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 114517568 # DTB read hits
|
|
system.cpu.dtb.read_misses 2631 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 114520199 # DTB read accesses
|
|
system.cpu.dtb.write_hits 39453362 # DTB write hits
|
|
system.cpu.dtb.write_misses 2302 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 39455664 # DTB write accesses
|
|
system.cpu.dtb.data_hits 153970930 # DTB hits
|
|
system.cpu.dtb.data_misses 4933 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 153975863 # DTB accesses
|
|
system.cpu.itb.fetch_hits 24997854 # ITB hits
|
|
system.cpu.itb.fetch_misses 22 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 24997876 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
system.cpu.numCycles 539322610 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups
|
|
system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted
|
|
system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect
|
|
system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups
|
|
system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits
|
|
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
|
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
|
system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage
|
|
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 154928367 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 90.582759 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
|
system.cpu.comStores 39451321 # Number of Store instructions committed
|
|
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
|
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
|
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 30 # number of replacements
|
|
system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 24996820 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1034 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 1042 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 429942 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 429956 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4125 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4966 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21328 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21328 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 25453 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 26294 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1014 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 451299 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 151786016 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2179347 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|