stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated.
This commit is contained in:
Nilay Vaish
parent
d32ee94231
commit
247e4e9ab4
|
|
@ -1,26 +1,24 @@
|
|||
Real time: May/15/2013 12:08:23
|
||||
Real time: Jun/08/2013 21:48:44
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 796
|
||||
Elapsed_time_in_minutes: 13.2667
|
||||
Elapsed_time_in_hours: 0.221111
|
||||
Elapsed_time_in_days: 0.00921296
|
||||
Elapsed_time_in_seconds: 452
|
||||
Elapsed_time_in_minutes: 7.53333
|
||||
Elapsed_time_in_hours: 0.125556
|
||||
Elapsed_time_in_days: 0.00523148
|
||||
|
||||
Virtual_time_in_seconds: 792.33
|
||||
Virtual_time_in_minutes: 13.2055
|
||||
Virtual_time_in_hours: 0.220092
|
||||
Virtual_time_in_days: 0.00917049
|
||||
Virtual_time_in_seconds: 451.44
|
||||
Virtual_time_in_minutes: 7.524
|
||||
Virtual_time_in_hours: 0.1254
|
||||
Virtual_time_in_days: 0.005225
|
||||
|
||||
Ruby_current_time: 10410297758
|
||||
Ruby_current_time: 10410298653
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 10410297758
|
||||
Ruby_cycles: 10410298653
|
||||
|
||||
mbytes_resident: 606.461
|
||||
mbytes_total: 851.852
|
||||
resident_ratio: 0.711942
|
||||
|
||||
ruby_cycles_executed: [ 10410297759 10410297759 ]
|
||||
mbytes_resident: 603.562
|
||||
mbytes_total: 845.523
|
||||
resident_ratio: 0.713842
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0
|
||||
|
|
@ -30,18 +28,18 @@ DMA-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151886718 average: 1.00011 | standard deviation: 0.0104983 | 0 151869977 16741 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151894334 average: 1.00011 | standard deviation: 0.010498 | 0 151877593 16741 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_RMW_Read: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 2 max: 273 count: 151894333 average: 3.45796 | standard deviation: 5.18178 | 0 149239567 0 0 0 0 0 0 0 967464 591 1434698 471 54488 562 16355 155 88 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3746 6141 8990 10313 51758 198 522 84 112 132 6 26 8 7 13 3 10 5 5 28 6 18 2 7 7 8 479 4505 10311 18263 13957 43735 864 879 2392 323 819 20 28 57 18 19 14 12 60 8 31 14 18 43 23 32 13 29 21 85 141 121 139 253 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 220 count: 14873782 average: 5.10749 | standard deviation: 8.69963 | 0 13484760 0 0 0 0 0 0 0 129532 100 1200232 299 19462 338 4825 113 55 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 925 785 3670 3475 2363 76 103 37 42 35 3 4 3 3 1 2 1 0 2 1 2 3 1 3 1 4 8 1414 2823 4592 6409 5895 325 281 248 108 123 9 10 5 12 3 3 0 6 2 7 7 2 8 9 8 8 12 4 27 22 46 51 30 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 273 count: 9469041 average: 5.2084 | standard deviation: 15.5209 | 0 9119543 0 0 0 0 0 0 0 27234 17 178584 110 14328 126 1523 26 15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 767 3342 3842 6354 49276 86 397 33 58 94 2 21 3 2 12 1 7 2 2 22 3 13 1 3 4 2 469 1037 3063 9469 7160 37435 384 483 2032 204 689 4 12 49 6 14 8 11 46 5 22 5 10 34 5 21 4 14 12 24 82 60 85 221 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 212 count: 126382608 average: 3.11852 | standard deviation: 2.02576 | 0 125570339 0 0 0 0 0 0 0 794822 440 412 31 47 16 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1944 1905 1015 43 50 21 20 11 2 1 1 0 1 2 0 0 2 3 0 5 1 2 0 0 1 2 2 2037 4356 4144 206 200 153 98 109 4 5 6 5 3 0 2 3 1 8 1 2 2 6 1 9 3 1 3 5 34 36 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_RMW_Read: [binsize: 2 max: 215 count: 490938 average: 6.04036 | standard deviation: 9.43363 | 0 425802 0 0 0 0 0 0 0 10414 26 32627 15 12080 33 8513 8 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 85 391 391 44 15 1 3 9 2 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 49 16 125 166 0 12 1 6 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 338982 average: 5.45592 | standard deviation: 7.80247 | 0 300141 0 0 0 0 0 0 0 5462 8 22843 16 8571 49 1494 8 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 24 72 50 25 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 9 20 42 57 39 2 5 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338982 average: 3 | standard deviation: 0 | 0 0 0 338982 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 273 count: 151894333 average: 3.45796 | standard deviation: 5.18178 | 0 149239567 0 0 0 0 0 0 0 967464 591 1434698 471 54488 562 16355 155 88 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3746 6141 8990 10313 51758 198 522 84 112 132 6 26 8 7 13 3 10 5 5 28 6 18 2 7 7 8 479 4505 10311 18263 13957 43735 864 879 2392 323 819 20 28 57 18 19 14 12 60 8 31 14 18 43 23 32 13 29 21 85 141 121 139 253 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -52,12 +50,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_RMW_Read_NULL: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ]
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 220 count: 14873782 average: 5.10749 | standard deviation: 8.69963 | 0 13484760 0 0 0 0 0 0 0 129532 100 1200232 299 19462 338 4825 113 55 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 925 785 3670 3475 2363 76 103 37 42 35 3 4 3 3 1 2 1 0 2 1 2 3 1 3 1 4 8 1414 2823 4592 6409 5895 325 281 248 108 123 9 10 5 12 3 3 0 6 2 7 7 2 8 9 8 8 12 4 27 22 46 51 30 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 273 count: 9469041 average: 5.2084 | standard deviation: 15.5209 | 0 9119543 0 0 0 0 0 0 0 27234 17 178584 110 14328 126 1523 26 15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 767 3342 3842 6354 49276 86 397 33 58 94 2 21 3 2 12 1 7 2 2 22 3 13 1 3 4 2 469 1037 3063 9469 7160 37435 384 483 2032 204 689 4 12 49 6 14 8 11 46 5 22 5 10 34 5 21 4 14 12 24 82 60 85 221 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 126382608 average: 3.11852 | standard deviation: 2.02576 | 0 125570339 0 0 0 0 0 0 0 794822 440 412 31 47 16 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1944 1905 1015 43 50 21 20 11 2 1 1 0 1 2 0 0 2 3 0 5 1 2 0 0 1 2 2 2037 4356 4144 206 200 153 98 109 4 5 6 5 3 0 2 3 1 8 1 2 2 6 1 9 3 1 3 5 34 36 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_RMW_Read_NULL: [binsize: 2 max: 215 count: 490938 average: 6.04036 | standard deviation: 9.43363 | 0 425802 0 0 0 0 0 0 0 10414 26 32627 15 12080 33 8513 8 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 85 391 391 44 15 1 3 9 2 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 49 16 125 166 0 12 1 6 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 338982 average: 5.45592 | standard deviation: 7.80247 | 0 300141 0 0 0 0 0 0 0 5462 8 22843 16 8571 49 1494 8 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 24 72 50 25 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 9 20 42 57 39 2 5 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338982 average: 3 | standard deviation: 0 | 0 0 0 338982 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -67,14 +65,13 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 13 count: 10870925 average: 0.594928 | standard deviation: 1.42414 | 9253812 1012 651 887 1612847 1000 118 100 122 292 7 8 8 61 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098339 average: 1.04364 | standard deviation: 1.75794 | 4507669 499 240 245 1588105 876 117 99 116 289 7 8 8 61 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4691441 average: 0.0216927 | standard deviation: 0.292466 | 4665403 421 342 554 24629 83 1 0 6 2 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 81145 average: 0.0143817 | standard deviation: 0.224975 | 80740 92 69 88 113 41 0 1 0 1 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 13 count: 10872111 average: 0.594835 | standard deviation: 1.42402 | 9255080 1027 577 868 1612870 996 93 113 108 307 2 12 11 47 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098873 average: 1.04349 | standard deviation: 1.75782 | 4508308 488 183 246 1588097 865 93 112 105 304 2 12 11 47 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4691974 average: 0.021726 | standard deviation: 0.292754 | 4665904 440 309 530 24688 96 0 1 3 3 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 5 count: 81264 average: 0.0130439 | standard deviation: 0.207207 | 80868 99 85 92 85 35 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -86,82 +83,82 @@ Total_delay_cycles: [binsize: 1 max: 13 count: 10870925 average: 0.594928 | stan
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 791
|
||||
user_time: 450
|
||||
system_time: 0
|
||||
page_reclaims: 146348
|
||||
page_faults: 22
|
||||
page_reclaims: 147544
|
||||
page_faults: 18
|
||||
swaps: 0
|
||||
block_inputs: 28560
|
||||
block_outputs: 552
|
||||
block_inputs: 16000
|
||||
block_outputs: 528
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 8502765 68022120
|
||||
total_msg_count_Request_Control: 241699 1933592
|
||||
total_msg_count_Response_Data: 8804706 633938832
|
||||
total_msg_count_Response_Control: 10887918 87103344
|
||||
total_msg_count_Writeback_Data: 4768101 343303272
|
||||
total_msg_count_Writeback_Control: 288537 2308296
|
||||
total_msgs: 33493726 total_bytes: 1136609456
|
||||
total_msg_count_Control: 8503962 68031696
|
||||
total_msg_count_Request_Control: 242054 1936432
|
||||
total_msg_count_Response_Data: 8805918 634026096
|
||||
total_msg_count_Response_Control: 10888710 87109680
|
||||
total_msg_count_Writeback_Data: 4768131 343305432
|
||||
total_msg_count_Writeback_Control: 288573 2308584
|
||||
total_msgs: 33497348 total_bytes: 1136717920
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0345328
|
||||
links_utilized_percent_switch_0_link_0: 0.0411595 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.0279062 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.0345415
|
||||
links_utilized_percent_switch_0_link_0: 0.041172 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.0279109 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 902852 7222816 [ 902852 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 39576 2849472 [ 0 39576 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 538021 4304168 [ 0 16306 521715 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 441060 31756320 [ 440947 113 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 43642 349136 [ 43642 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 42325 338600 [ 42325 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 891237 64169064 [ 0 891237 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 508805 4070440 [ 0 508805 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 903142 7225136 [ 903142 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 39642 2854224 [ 0 39642 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 538120 4304960 [ 0 16344 521776 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 441059 31756248 [ 440946 113 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 43648 349184 [ 43648 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0735425
|
||||
links_utilized_percent_switch_1_link_0: 0.0813498 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.0657351 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.0735457
|
||||
links_utilized_percent_switch_1_link_0: 0.0813533 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.0657382 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 1751526 14012208 [ 1751526 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 32667 2352024 [ 0 32667 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1253613 10028904 [ 0 16665 1236948 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 1148307 82678104 [ 1148172 135 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 52537 420296 [ 52537 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 38939 311512 [ 38939 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1742034 125426448 [ 0 1742034 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1220994 9767952 [ 0 1220994 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 1751624 14012992 [ 1751624 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 32707 2354904 [ 0 32707 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1253695 10029560 [ 0 16684 1237011 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 1148318 82678896 [ 1148183 135 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 52543 420344 [ 52543 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.112637
|
||||
links_utilized_percent_switch_2_link_0: 0.0997841 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.125489 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.112646
|
||||
links_utilized_percent_switch_2_link_0: 0.0997896 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.125503 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 79409 635272 [ 79409 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 2682782 193160304 [ 0 2682782 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1723320 13786560 [ 0 1723320 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Control: 2654766 21238128 [ 2654766 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 204249 14705928 [ 0 204249 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1883194 15065552 [ 0 124407 1758787 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 1589377 114435144 [ 1589129 248 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 96191 769528 [ 96191 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 179888 1439104 [ 179888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 79526 636208 [ 79526 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 2683069 193180968 [ 0 2683069 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1723392 13787136 [ 0 1723392 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 0.0067475
|
||||
links_utilized_percent_switch_3_link_0: 0.00517033 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.00832467 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.00674787
|
||||
links_utilized_percent_switch_3_link_0: 0.00517055 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.00832519 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 179877 12951144 [ 0 179877 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 114352 914816 [ 0 114352 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Control: 179888 1439104 [ 179888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 97786 7040592 [ 0 97786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 16577 132616 [ 0 16577 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 179888 12951936 [ 0 179888 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 114363 914904 [ 0 114363 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
|
|
@ -172,495 +169,25 @@ links_utilized_percent_switch_4: 0
|
|||
|
||||
switch_5_inlinks: 5
|
||||
switch_5_outlinks: 5
|
||||
links_utilized_percent_switch_5: 0.0454927
|
||||
links_utilized_percent_switch_5_link_0: 0.0411595 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.0813498 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_2: 0.0997841 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_3: 0.00517033 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5: 0.0454971
|
||||
links_utilized_percent_switch_5_link_0: 0.041172 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.0813533 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_2: 0.0997896 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_3: 0.00517055 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [6569518 8303439 ] 14872957
|
||||
Ifetch [70368031 56008906 ] 126376937
|
||||
Store [5484765 5152067 ] 10636832
|
||||
Inv [16419 16800 ] 33219
|
||||
L1_Replacement [875917 1724584 ] 2600501
|
||||
Fwd_GETX [12082 11527 ] 23609
|
||||
Fwd_GETS [13743 10570 ] 24313
|
||||
Fwd_GET_INSTR [4 0 ] 4
|
||||
Data [398 1087 ] 1485
|
||||
Data_Exclusive [267040 1013910 ] 1280950
|
||||
DataS_fromL1 [10570 13747 ] 24317
|
||||
Data_all_Acks [612950 713223 ] 1326173
|
||||
Ack [11894 9559 ] 21453
|
||||
Ack_all [12292 10646 ] 22938
|
||||
WB_Ack [484589 1200709 ] 1685298
|
||||
PF_Load [0 0 ] 0
|
||||
PF_Ifetch [0 0 ] 0
|
||||
PF_Store [0 0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [298305 1072264 ] 1370569
|
||||
NP Ifetch [352056 459391 ] 811447
|
||||
NP Store [226579 193953 ] 420532
|
||||
NP Inv [5722 3873 ] 9595
|
||||
NP L1_Replacement [0 0 ] 0
|
||||
NP PF_Load [0 0 ] 0
|
||||
NP PF_Ifetch [0 0 ] 0
|
||||
NP PF_Store [0 0 ] 0
|
||||
|
||||
I Load [8252 10124 ] 18376
|
||||
I Ifetch [134 456 ] 590
|
||||
I Store [5632 5779 ] 11411
|
||||
I Inv [0 0 ] 0
|
||||
I L1_Replacement [8759 7985 ] 16744
|
||||
I PF_Load [0 0 ] 0
|
||||
I PF_Ifetch [0 0 ] 0
|
||||
I PF_Store [0 0 ] 0
|
||||
|
||||
S Load [574695 455064 ] 1029759
|
||||
S Ifetch [70015833 55549058 ] 125564891
|
||||
S Store [11894 9559 ] 21453
|
||||
S Inv [10461 12745 ] 23206
|
||||
S L1_Replacement [382569 515890 ] 898459
|
||||
S PF_Load [0 0 ] 0
|
||||
S PF_Store [0 0 ] 0
|
||||
|
||||
E Load [1245572 2614603 ] 3860175
|
||||
E Ifetch [0 0 ] 0
|
||||
E Store [84229 82251 ] 166480
|
||||
E Inv [123 47 ] 170
|
||||
E L1_Replacement [181344 930396 ] 1111740
|
||||
E Fwd_GETX [229 170 ] 399
|
||||
E Fwd_GETS [930 990 ] 1920
|
||||
E Fwd_GET_INSTR [0 0 ] 0
|
||||
E PF_Load [0 0 ] 0
|
||||
E PF_Store [0 0 ] 0
|
||||
|
||||
M Load [4442694 4151384 ] 8594078
|
||||
M Ifetch [0 0 ] 0
|
||||
M Store [5156431 4860525 ] 10016956
|
||||
M Inv [113 135 ] 248
|
||||
M L1_Replacement [303245 270313 ] 573558
|
||||
M Fwd_GETX [11853 11357 ] 23210
|
||||
M Fwd_GETS [12813 9580 ] 22393
|
||||
M Fwd_GET_INSTR [4 0 ] 4
|
||||
M PF_Load [0 0 ] 0
|
||||
M PF_Store [0 0 ] 0
|
||||
|
||||
IS Load [0 0 ] 0
|
||||
IS Ifetch [0 0 ] 0
|
||||
IS Store [0 0 ] 0
|
||||
IS Inv [0 0 ] 0
|
||||
IS L1_Replacement [0 0 ] 0
|
||||
IS Data_Exclusive [267040 1013910 ] 1280950
|
||||
IS DataS_fromL1 [10570 13747 ] 24317
|
||||
IS Data_all_Acks [381137 514578 ] 895715
|
||||
IS PF_Load [0 0 ] 0
|
||||
IS PF_Store [0 0 ] 0
|
||||
|
||||
IM Load [0 0 ] 0
|
||||
IM Ifetch [0 0 ] 0
|
||||
IM Store [0 0 ] 0
|
||||
IM Inv [0 0 ] 0
|
||||
IM L1_Replacement [0 0 ] 0
|
||||
IM Data [398 1087 ] 1485
|
||||
IM Data_all_Acks [231813 198645 ] 430458
|
||||
IM Ack [0 0 ] 0
|
||||
IM PF_Load [0 0 ] 0
|
||||
IM PF_Store [0 0 ] 0
|
||||
|
||||
SM Load [0 0 ] 0
|
||||
SM Ifetch [0 0 ] 0
|
||||
SM Store [0 0 ] 0
|
||||
SM Inv [0 0 ] 0
|
||||
SM L1_Replacement [0 0 ] 0
|
||||
SM Ack [11894 9559 ] 21453
|
||||
SM Ack_all [12292 10646 ] 22938
|
||||
SM PF_Load [0 0 ] 0
|
||||
SM PF_Store [0 0 ] 0
|
||||
|
||||
IS_I Load [0 0 ] 0
|
||||
IS_I Ifetch [0 0 ] 0
|
||||
IS_I Store [0 0 ] 0
|
||||
IS_I Inv [0 0 ] 0
|
||||
IS_I L1_Replacement [0 0 ] 0
|
||||
IS_I Data_Exclusive [0 0 ] 0
|
||||
IS_I DataS_fromL1 [0 0 ] 0
|
||||
IS_I Data_all_Acks [0 0 ] 0
|
||||
IS_I PF_Load [0 0 ] 0
|
||||
IS_I PF_Store [0 0 ] 0
|
||||
|
||||
M_I Load [0 0 ] 0
|
||||
M_I Ifetch [8 1 ] 9
|
||||
M_I Store [0 0 ] 0
|
||||
M_I Inv [0 0 ] 0
|
||||
M_I L1_Replacement [0 0 ] 0
|
||||
M_I Fwd_GETX [0 0 ] 0
|
||||
M_I Fwd_GETS [0 0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 0 ] 0
|
||||
M_I WB_Ack [484589 1200709 ] 1685298
|
||||
M_I PF_Load [0 0 ] 0
|
||||
M_I PF_Store [0 0 ] 0
|
||||
|
||||
SINK_WB_ACK Load [0 0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 0 ] 0
|
||||
SINK_WB_ACK Store [0 0 ] 0
|
||||
SINK_WB_ACK Inv [0 0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 0 ] 0
|
||||
SINK_WB_ACK PF_Load [0 0 ] 0
|
||||
SINK_WB_ACK PF_Store [0 0 ] 0
|
||||
|
||||
PF_IS Load [0 0 ] 0
|
||||
PF_IS Ifetch [0 0 ] 0
|
||||
PF_IS Store [0 0 ] 0
|
||||
PF_IS Inv [0 0 ] 0
|
||||
PF_IS L1_Replacement [0 0 ] 0
|
||||
PF_IS Data_Exclusive [0 0 ] 0
|
||||
PF_IS DataS_fromL1 [0 0 ] 0
|
||||
PF_IS Data_all_Acks [0 0 ] 0
|
||||
PF_IS PF_Load [0 0 ] 0
|
||||
PF_IS PF_Store [0 0 ] 0
|
||||
|
||||
PF_IM Load [0 0 ] 0
|
||||
PF_IM Ifetch [0 0 ] 0
|
||||
PF_IM Store [0 0 ] 0
|
||||
PF_IM Inv [0 0 ] 0
|
||||
PF_IM L1_Replacement [0 0 ] 0
|
||||
PF_IM Data [0 0 ] 0
|
||||
PF_IM Data_all_Acks [0 0 ] 0
|
||||
PF_IM Ack [0 0 ] 0
|
||||
PF_IM PF_Load [0 0 ] 0
|
||||
PF_IM PF_Store [0 0 ] 0
|
||||
|
||||
PF_SM Load [0 0 ] 0
|
||||
PF_SM Ifetch [0 0 ] 0
|
||||
PF_SM Store [0 0 ] 0
|
||||
PF_SM Inv [0 0 ] 0
|
||||
PF_SM L1_Replacement [0 0 ] 0
|
||||
PF_SM Ack [0 0 ] 0
|
||||
PF_SM Ack_all [0 0 ] 0
|
||||
|
||||
PF_IS_I Load [0 0 ] 0
|
||||
PF_IS_I Store [0 0 ] 0
|
||||
PF_IS_I Inv [0 0 ] 0
|
||||
PF_IS_I L1_Replacement [0 0 ] 0
|
||||
PF_IS_I Data_Exclusive [0 0 ] 0
|
||||
PF_IS_I DataS_fromL1 [0 0 ] 0
|
||||
PF_IS_I Data_all_Acks [0 0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [812037 ] 812037
|
||||
L1_GETS [1389190 ] 1389190
|
||||
L1_GETX [431946 ] 431946
|
||||
L1_UPGRADE [21453 ] 21453
|
||||
L1_PUTX [1685298 ] 1685298
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [97649 ] 97649
|
||||
L2_Replacement_clean [16703 ] 16703
|
||||
Mem_Data [179877 ] 179877
|
||||
Mem_Ack [114352 ] 114352
|
||||
WB_Data [24047 ] 24047
|
||||
WB_Data_clean [518 ] 518
|
||||
Ack [1736 ] 1736
|
||||
Ack_all [8297 ] 8297
|
||||
Unblock [24317 ] 24317
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [1734346 ] 1734346
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [16486 ] 16486
|
||||
NP L1_GETS [34061 ] 34061
|
||||
NP L1_GETX [129330 ] 129330
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [795239 ] 795239
|
||||
SS L1_GETS [83682 ] 83682
|
||||
SS L1_GETX [1684 ] 1684
|
||||
SS L1_UPGRADE [21453 ] 21453
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [262 ] 262
|
||||
SS L2_Replacement_clean [7865 ] 7865
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [308 ] 308
|
||||
M L1_GETS [1246889 ] 1246889
|
||||
M L1_GETX [277320 ] 277320
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [97222 ] 97222
|
||||
M L2_Replacement_clean [8585 ] 8585
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [4 ] 4
|
||||
MT L1_GETS [24313 ] 24313
|
||||
MT L1_GETX [23609 ] 23609
|
||||
MT L1_PUTX [1685298 ] 1685298
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [165 ] 165
|
||||
MT L2_Replacement_clean [253 ] 253
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [114352 ] 114352
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [114 ] 114
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [51 ] 51
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [134 ] 134
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [119 ] 119
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [1475 ] 1475
|
||||
I_I Ack_all [7865 ] 7865
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [261 ] 261
|
||||
S_I Ack_all [262 ] 262
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [34061 ] 34061
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [16486 ] 16486
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [129330 ] 129330
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [183 ] 183
|
||||
SS_MB L1_GETX [1 ] 1
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [23137 ] 23137
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [62 ] 62
|
||||
MT_MB L1_GETX [2 ] 2
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [1711209 ] 1711209
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [23791 ] 23791
|
||||
MT_IIB WB_Data_clean [518 ] 518
|
||||
MT_IIB Unblock [8 ] 8
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [8 ] 8
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [24309 ] 24309
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 277660
|
||||
memory_reads: 179877
|
||||
memory_writes: 97783
|
||||
memory_refreshes: 595612
|
||||
memory_total_request_delays: 1053031
|
||||
memory_delays_per_request: 3.79252
|
||||
memory_delays_in_input_queue: 41105
|
||||
memory_delays_behind_head_of_bank_queue: 8032
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1003894
|
||||
memory_stalls_for_bank_busy: 993997
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 2275
|
||||
memory_stalls_for_bus: 7591
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 24
|
||||
memory_stalls_for_read_read_turnaround: 7
|
||||
accesses_per_bank: 9197 9271 8435 8566 9408 8743 9113 8368 8530 8379 8370 8376 8453 8237 8220 7443 8424 8515 8423 8429 8600 8511 8363 8339 8693 8492 8814 9468 9371 9231 10342 8536
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [179877 ] 179877
|
||||
Data [97783 ] 97783
|
||||
Memory_Data [179877 ] 179877
|
||||
Memory_Ack [97783 ] 97783
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [16569 ] 16569
|
||||
|
||||
- Transitions -
|
||||
I Fetch [179877 ] 179877
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [97783 ] 97783
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [16569 ] 16569
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [179877 ] 179877
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [97783 ] 97783
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
--- DMA ---
|
||||
- Event Counts -
|
||||
ReadRequest [0 ] 0
|
||||
WriteRequest [0 ] 0
|
||||
Data [0 ] 0
|
||||
Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest [0 ] 0
|
||||
READY WriteRequest [0 ] 0
|
||||
|
||||
BUSY_RD Data [0 ] 0
|
||||
|
||||
BUSY_WR Ack [0 ] 0
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 42325 338600 [ 42325 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 891237 64169064 [ 0 891237 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 508805 4070440 [ 0 508805 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Request_Control: 38939 311512 [ 38939 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1742034 125426448 [ 0 1742034 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 1220994 9767952 [ 0 1220994 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Control: 2654766 21238128 [ 2654766 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Data: 204249 14705928 [ 0 204249 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Control: 1883194 15065552 [ 0 124407 1758787 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Data: 1589377 114435144 [ 1589129 248 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Control: 96191 769528 [ 96191 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Control: 179888 1439104 [ 179888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Data: 97786 7040592 [ 0 97786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Control: 16577 132616 [ 0 16577 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.205149 # Nu
|
|||
sim_ticks 5205149326500 # Number of ticks simulated
|
||||
final_tick 5205149326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 156279 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 299599 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7625516175 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 825184 # Number of bytes of host memory used
|
||||
host_seconds 682.60 # Real time elapsed on the host
|
||||
host_inst_rate 236082 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 452590 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11519487202 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 865820 # Number of bytes of host memory used
|
||||
host_seconds 451.86 # Real time elapsed on the host
|
||||
sim_insts 106675228 # Number of instructions simulated
|
||||
sim_ops 204505420 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory
|
||||
|
|
@ -499,6 +499,23 @@ system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0
|
|||
system.ruby.l2_cntrl0.L2cache.demand_hits 2426890 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 227876 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 2654766 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 277674 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 179888 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 97786 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 595732 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1003550 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 41112 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 8109 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1052771 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.791392 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 993723 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 7525 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 17 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 4 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 2281 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 9206 3.32% 3.32% | 9271 3.34% 6.65% | 8439 3.04% 9.69% | 8570 3.09% 12.78% | 9408 3.39% 16.17% | 8743 3.15% 19.32% | 9113 3.28% 22.60% | 8368 3.01% 25.61% | 8530 3.07% 28.68% | 8379 3.02% 31.70% | 8370 3.01% 34.72% | 8376 3.02% 37.73% | 8453 3.04% 40.78% | 8237 2.97% 43.74% | 8220 2.96% 46.70% | 7443 2.68% 49.38% | 8424 3.03% 52.42% | 8514 3.07% 55.48% | 8423 3.03% 58.52% | 8429 3.04% 61.55% | 8600 3.10% 64.65% | 8511 3.07% 67.72% | 8363 3.01% 70.73% | 8339 3.00% 73.73% | 8693 3.13% 76.86% | 8492 3.06% 79.92% | 8814 3.17% 83.09% | 9464 3.41% 86.50% | 9373 3.38% 89.88% | 9231 3.32% 93.20% | 10342 3.72% 96.93% | 8536 3.07% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 277674 # Number of accesses per bank
|
||||
|
||||
system.cpu0.numCycles 10410298653 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
|
@ -547,5 +564,223 @@ system.cpu1.not_idle_fraction 0.031349 # Pe
|
|||
system.cpu1.idle_fraction 0.968651 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.ruby.l1_cntrl0.Load | 6571015 44.18% 44.18% | 8302767 55.82% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 14873782
|
||||
|
||||
system.ruby.l1_cntrl0.Ifetch | 70375931 55.68% 55.68% | 56006686 44.32% 100.00%
|
||||
system.ruby.l1_cntrl0.Ifetch::total 126382617
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 5485961 51.57% 51.57% | 5151982 48.43% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 10637943
|
||||
|
||||
system.ruby.l1_cntrl0.Inv | 16457 49.46% 49.46% | 16819 50.54% 100.00%
|
||||
system.ruby.l1_cntrl0.Inv::total 33276
|
||||
|
||||
system.ruby.l1_cntrl0.L1_Replacement | 876181 33.69% 33.69% | 1724616 66.31% 100.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement::total 2600797
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETX | 12094 51.19% 51.19% | 11533 48.81% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETX::total 23627
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETS | 13770 56.53% 56.53% | 10587 43.47% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETS::total 24357
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4
|
||||
|
||||
system.ruby.l1_cntrl0.Data | 401 26.93% 26.93% | 1088 73.07% 100.00%
|
||||
system.ruby.l1_cntrl0.Data::total 1489
|
||||
|
||||
system.ruby.l1_cntrl0.Data_Exclusive | 267049 20.85% 20.85% | 1013902 79.15% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_Exclusive::total 1280951
|
||||
|
||||
system.ruby.l1_cntrl0.DataS_fromL1 | 10587 43.46% 43.46% | 13774 56.54% 100.00%
|
||||
system.ruby.l1_cntrl0.DataS_fromL1::total 24361
|
||||
|
||||
system.ruby.l1_cntrl0.Data_all_Acks | 613200 46.23% 46.23% | 713270 53.77% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_all_Acks::total 1326470
|
||||
|
||||
system.ruby.l1_cntrl0.Ack | 11905 55.38% 55.38% | 9590 44.62% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack::total 21495
|
||||
|
||||
system.ruby.l1_cntrl0.Ack_all | 12306 53.54% 53.54% | 10678 46.46% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack_all::total 22984
|
||||
|
||||
system.ruby.l1_cntrl0.WB_Ack | 484594 28.75% 28.75% | 1200726 71.25% 100.00%
|
||||
system.ruby.l1_cntrl0.WB_Ack::total 1685320
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Load | 298337 21.77% 21.77% | 1072276 78.23% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Load::total 1370613
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Ifetch | 352269 43.40% 43.40% | 459412 56.60% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch::total 811681
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Store | 226598 53.88% 53.88% | 193952 46.12% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Store::total 420550
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Inv | 5731 59.66% 59.66% | 3875 40.34% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Inv::total 9606
|
||||
|
||||
system.ruby.l1_cntrl0.I.Load | 8263 44.89% 44.89% | 10146 55.11% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Load::total 18409
|
||||
|
||||
system.ruby.l1_cntrl0.I.Ifetch | 133 22.62% 22.62% | 455 77.38% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch::total 588
|
||||
|
||||
system.ruby.l1_cntrl0.I.Store | 5637 49.32% 49.32% | 5793 50.68% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Store::total 11430
|
||||
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement | 8785 52.43% 52.43% | 7970 47.57% 100.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement::total 16755
|
||||
|
||||
system.ruby.l1_cntrl0.S.Load | 574881 55.81% 55.81% | 455195 44.19% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Load::total 1030076
|
||||
|
||||
system.ruby.l1_cntrl0.S.Ifetch | 70023521 55.76% 55.76% | 55546818 44.24% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch::total 125570339
|
||||
|
||||
system.ruby.l1_cntrl0.S.Store | 11905 55.38% 55.38% | 9590 44.62% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Store::total 21495
|
||||
|
||||
system.ruby.l1_cntrl0.S.Inv | 10490 45.11% 45.11% | 12762 54.89% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Inv::total 23252
|
||||
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement | 382802 42.59% 42.59% | 515920 57.41% 100.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement::total 898722
|
||||
|
||||
system.ruby.l1_cntrl0.E.Load | 1245602 32.27% 32.27% | 2614611 67.73% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Load::total 3860213
|
||||
|
||||
system.ruby.l1_cntrl0.E.Store | 84222 50.59% 50.59% | 82245 49.41% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Store::total 166467
|
||||
|
||||
system.ruby.l1_cntrl0.E.Inv | 123 72.35% 72.35% | 47 27.65% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Inv::total 170
|
||||
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement | 181362 16.31% 16.31% | 930398 83.69% 100.00%
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement::total 1111760
|
||||
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETX | 229 57.39% 57.39% | 170 42.61% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETX::total 399
|
||||
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETS | 928 48.38% 48.38% | 990 51.62% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETS::total 1918
|
||||
|
||||
system.ruby.l1_cntrl0.M.Load | 4443932 51.71% 51.71% | 4150539 48.29% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Load::total 8594471
|
||||
|
||||
system.ruby.l1_cntrl0.M.Store | 5157599 51.48% 51.48% | 4860402 48.52% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 10018001
|
||||
|
||||
system.ruby.l1_cntrl0.M.Inv | 113 45.56% 45.56% | 135 54.44% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Inv::total 248
|
||||
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement | 303232 52.87% 52.87% | 270328 47.13% 100.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement::total 573560
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX | 11865 51.08% 51.08% | 11363 48.92% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX::total 23228
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETS | 12842 57.23% 57.23% | 9597 42.77% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETS::total 22439
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive | 267049 20.85% 20.85% | 1013902 79.15% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1280951
|
||||
|
||||
system.ruby.l1_cntrl0.IS.DataS_fromL1 | 10587 43.46% 43.46% | 13774 56.54% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.DataS_fromL1::total 24361
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks | 381366 42.56% 42.56% | 514613 57.44% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks::total 895979
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data | 401 26.93% 26.93% | 1088 73.07% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data::total 1489
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks | 231834 53.85% 53.85% | 198657 46.15% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks::total 430491
|
||||
|
||||
system.ruby.l1_cntrl0.SM.Ack | 11905 55.38% 55.38% | 9590 44.62% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.Ack::total 21495
|
||||
|
||||
system.ruby.l1_cntrl0.SM.Ack_all | 12306 53.54% 53.54% | 10678 46.46% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.Ack_all::total 22984
|
||||
|
||||
system.ruby.l1_cntrl0.M_I.Ifetch | 8 88.89% 88.89% | 1 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.M_I.Ifetch::total 9
|
||||
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack | 484594 28.75% 28.75% | 1200726 71.25% 100.00%
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack::total 1685320
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GET_INSTR 812269 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS 1389202 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 431983 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_UPGRADE 21495 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 1685320 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 97653 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement_clean 16710 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Data 179888 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Ack 114363 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data 24092 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data_clean 517 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack 1738 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack_all 8306 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Unblock 24361 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 1734426 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GET_INSTR 16492 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 34063 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 129333 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GET_INSTR 795465 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GETS 83714 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GETX 1688 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_UPGRADE 21495 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement 263 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement_clean 7873 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GET_INSTR 308 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 1246888 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 277332 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 97224 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement_clean 8585 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_GETS 24357 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_GETX 23627 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_PUTX 1685320 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement 166 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement_clean 252 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.Mem_Ack 114363 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.WB_Data 115 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.Ack_all 51 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data 133 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.Ack_all 119 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack 1476 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack_all 7873 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S_I.Ack 262 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S_I.Ack_all 263 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.Mem_Data 34063 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.Mem_Data 16492 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.Mem_Data 129333 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.L1_GETS 124 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 23183 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_GETS 56 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_GETX 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1711243 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.WB_Data 23838 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 517 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.Unblock 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IB.WB_Data 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_SB.Unblock 24355 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Fetch 179888 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data 97786 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 179888 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 97786 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.CleanReplacement 16577 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Fetch 179888 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.Data 97786 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.CleanReplacement 16577 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 179888 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 97786 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -0,0 +1,138 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.233778 # Number of seconds simulated
|
||||
sim_ticks 4467555024 # Number of ticks simulated
|
||||
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3018077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3019263 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6051033 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 556628 # Number of bytes of host memory used
|
||||
host_seconds 738.31 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
|
||||
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 5163367605 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 11533814443 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iobus.throughput 15555081 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 34746591 # Total data (bytes)
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1839325658 # number of integer instructions
|
||||
system.cpu.num_fp_insts 14608322 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 547951940 # number of memory refs
|
||||
system.cpu.num_load_insts 349807670 # Number of load instructions
|
||||
system.cpu.num_store_insts 198144270 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Mar/06/2013 20:38:34
|
||||
Real time: Jun/08/2013 14:12:32
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.68
|
||||
Virtual_time_in_minutes: 0.0113333
|
||||
Virtual_time_in_hours: 0.000188889
|
||||
Virtual_time_in_days: 7.87037e-06
|
||||
Virtual_time_in_seconds: 0.6
|
||||
Virtual_time_in_minutes: 0.01
|
||||
Virtual_time_in_hours: 0.000166667
|
||||
Virtual_time_in_days: 6.94444e-06
|
||||
|
||||
Ruby_current_time: 138616
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 138616
|
||||
|
||||
mbytes_resident: 55.9375
|
||||
mbytes_total: 148.203
|
||||
resident_ratio: 0.377491
|
||||
|
||||
ruby_cycles_executed: [ 138617 ]
|
||||
mbytes_resident: 56.3281
|
||||
mbytes_total: 144.332
|
||||
resident_ratio: 0.390322
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -61,7 +59,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -82,7 +79,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11604
|
||||
page_reclaims: 11627
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 4.89085
|
|||
outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1183 ] 1183
|
||||
Ifetch [6400 ] 6400
|
||||
Store [865 ] 865
|
||||
Inv [1041 ] 1041
|
||||
L1_Replacement [1354 ] 1354
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [583 ] 583
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [907 ] 907
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [436 ] 436
|
||||
PF_Load [0 ] 0
|
||||
PF_Ifetch [0 ] 0
|
||||
PF_Store [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [525 ] 525
|
||||
NP Ifetch [646 ] 646
|
||||
NP Store [191 ] 191
|
||||
NP Inv [356 ] 356
|
||||
NP L1_Replacement [0 ] 0
|
||||
NP PF_Load [0 ] 0
|
||||
NP PF_Ifetch [0 ] 0
|
||||
NP PF_Store [0 ] 0
|
||||
|
||||
I Load [58 ] 58
|
||||
I Ifetch [45 ] 45
|
||||
I Store [25 ] 25
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [556 ] 556
|
||||
I PF_Load [0 ] 0
|
||||
I PF_Ifetch [0 ] 0
|
||||
I PF_Store [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [5709 ] 5709
|
||||
S Store [0 ] 0
|
||||
S Inv [325 ] 325
|
||||
S L1_Replacement [362 ] 362
|
||||
S PF_Load [0 ] 0
|
||||
S PF_Store [0 ] 0
|
||||
|
||||
E Load [452 ] 452
|
||||
E Ifetch [0 ] 0
|
||||
E Store [71 ] 71
|
||||
E Inv [219 ] 219
|
||||
E L1_Replacement [291 ] 291
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
E PF_Load [0 ] 0
|
||||
E PF_Store [0 ] 0
|
||||
|
||||
M Load [148 ] 148
|
||||
M Ifetch [0 ] 0
|
||||
M Store [578 ] 578
|
||||
M Inv [141 ] 141
|
||||
M L1_Replacement [145 ] 145
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
M PF_Load [0 ] 0
|
||||
M PF_Store [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Exclusive [583 ] 583
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [691 ] 691
|
||||
IS PF_Load [0 ] 0
|
||||
IS PF_Store [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [216 ] 216
|
||||
IM Ack [0 ] 0
|
||||
IM PF_Load [0 ] 0
|
||||
IM PF_Store [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [0 ] 0
|
||||
SM PF_Load [0 ] 0
|
||||
SM PF_Store [0 ] 0
|
||||
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
IS_I Store [0 ] 0
|
||||
IS_I Inv [0 ] 0
|
||||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [0 ] 0
|
||||
IS_I PF_Load [0 ] 0
|
||||
IS_I PF_Store [0 ] 0
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [0 ] 0
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [0 ] 0
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [436 ] 436
|
||||
M_I PF_Load [0 ] 0
|
||||
M_I PF_Store [0 ] 0
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 ] 0
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 ] 0
|
||||
SINK_WB_ACK PF_Load [0 ] 0
|
||||
SINK_WB_ACK PF_Store [0 ] 0
|
||||
|
||||
PF_IS Load [0 ] 0
|
||||
PF_IS Ifetch [0 ] 0
|
||||
PF_IS Store [0 ] 0
|
||||
PF_IS Inv [0 ] 0
|
||||
PF_IS L1_Replacement [0 ] 0
|
||||
PF_IS Data_Exclusive [0 ] 0
|
||||
PF_IS DataS_fromL1 [0 ] 0
|
||||
PF_IS Data_all_Acks [0 ] 0
|
||||
PF_IS PF_Load [0 ] 0
|
||||
PF_IS PF_Store [0 ] 0
|
||||
|
||||
PF_IM Load [0 ] 0
|
||||
PF_IM Ifetch [0 ] 0
|
||||
PF_IM Store [0 ] 0
|
||||
PF_IM Inv [0 ] 0
|
||||
PF_IM L1_Replacement [0 ] 0
|
||||
PF_IM Data [0 ] 0
|
||||
PF_IM Data_all_Acks [0 ] 0
|
||||
PF_IM Ack [0 ] 0
|
||||
PF_IM PF_Load [0 ] 0
|
||||
PF_IM PF_Store [0 ] 0
|
||||
|
||||
PF_SM Load [0 ] 0
|
||||
PF_SM Ifetch [0 ] 0
|
||||
PF_SM Store [0 ] 0
|
||||
PF_SM Inv [0 ] 0
|
||||
PF_SM L1_Replacement [0 ] 0
|
||||
PF_SM Ack [0 ] 0
|
||||
PF_SM Ack_all [0 ] 0
|
||||
|
||||
PF_IS_I Load [0 ] 0
|
||||
PF_IS_I Store [0 ] 0
|
||||
PF_IS_I Inv [0 ] 0
|
||||
PF_IS_I L1_Replacement [0 ] 0
|
||||
PF_IS_I Data_Exclusive [0 ] 0
|
||||
PF_IS_I DataS_fromL1 [0 ] 0
|
||||
PF_IS_I Data_all_Acks [0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [691 ] 691
|
||||
L1_GETS [583 ] 583
|
||||
L1_GETX [216 ] 216
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [436 ] 436
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [142 ] 142
|
||||
L2_Replacement_clean [1310 ] 1310
|
||||
Mem_Data [1460 ] 1460
|
||||
Mem_Ack [1452 ] 1452
|
||||
WB_Data [141 ] 141
|
||||
WB_Data_clean [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_all [900 ] 900
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [799 ] 799
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [686 ] 686
|
||||
NP L1_GETS [570 ] 570
|
||||
NP L1_GETX [204 ] 204
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [5 ] 5
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [0 ] 0
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [681 ] 681
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [13 ] 13
|
||||
M L1_GETX [12 ] 12
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [134 ] 134
|
||||
M L2_Replacement_clean [277 ] 277
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [436 ] 436
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [8 ] 8
|
||||
MT L2_Replacement_clean [352 ] 352
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [1452 ] 1452
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [6 ] 6
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [2 ] 2
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [135 ] 135
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [217 ] 217
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [681 ] 681
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [570 ] 570
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [686 ] 686
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [204 ] 204
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [0 ] 0
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [799 ] 799
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [0 ] 0
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [0 ] 0
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [0 ] 0
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1737
|
||||
memory_reads: 1460
|
||||
memory_writes: 277
|
||||
memory_refreshes: 963
|
||||
memory_total_request_delays: 341
|
||||
memory_delays_per_request: 0.196315
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 341
|
||||
memory_stalls_for_bank_busy: 166
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 24
|
||||
memory_stalls_for_bus: 147
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [1460 ] 1460
|
||||
Data [277 ] 277
|
||||
Memory_Data [1460 ] 1460
|
||||
Memory_Ack [277 ] 277
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [1175 ] 1175
|
||||
|
||||
- Transitions -
|
||||
I Fetch [1460 ] 1460
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [277 ] 277
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [1175 ] 1175
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [1460 ] 1460
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [277 ] 277
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu
|
|||
sim_ticks 138616 # Number of ticks simulated
|
||||
final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 20262 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 20260 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 439475 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 154624 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
host_inst_rate 33803 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 33800 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 733103 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 147800 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
|
||||
|
|
@ -29,6 +29,20 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 963 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 341 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 341 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.196315 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 166 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 147 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 24 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 92 5.30% 5.30% | 21 1.21% 6.51% | 45 2.59% 9.10% | 54 3.11% 12.20% | 57 3.28% 15.49% | 174 10.02% 25.50% | 48 2.76% 28.27% | 18 1.04% 29.30% | 19 1.09% 30.40% | 22 1.27% 31.66% | 35 2.01% 33.68% | 37 2.13% 35.81% | 56 3.22% 39.03% | 59 3.40% 42.43% | 44 2.53% 44.96% | 36 2.07% 47.04% | 41 2.36% 49.40% | 24 1.38% 50.78% | 22 1.27% 52.04% | 28 1.61% 53.66% | 32 1.84% 55.50% | 48 2.76% 58.26% | 122 7.02% 65.28% | 36 2.07% 67.36% | 32 1.84% 69.20% | 25 1.44% 70.64% | 35 2.01% 72.65% | 96 5.53% 78.18% | 114 6.56% 84.74% | 185 10.65% 95.39% | 19 1.09% 96.49% | 61 3.51% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1737 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -84,5 +98,79 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 138616 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l2_cntrl0.L1_GET_INSTR 691 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS 583 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 216 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 436 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 142 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement_clean 1310 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Data 1460 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Ack 1452 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data 141 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack_all 900 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 799 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GET_INSTR 686 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 570 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 204 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GET_INSTR 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement_clean 681 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 13 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 12 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 134 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement_clean 277 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_PUTX 436 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement 8 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement_clean 352 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.Mem_Ack 1452 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.WB_Data 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data 135 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.Ack_all 217 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack_all 681 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.Mem_Data 570 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.Mem_Data 686 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.Mem_Data 204 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 799 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 1183 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 865 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Inv 1041 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 1354 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Exclusive 583 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_all_Acks 907 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.WB_Ack 436 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Inv 356 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 45 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 25 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement 556 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch 5709 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Inv 325 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement 362 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Load 452 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Store 71 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Inv 219 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement 291 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 148 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 578 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Inv 141 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 145 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive 583 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks 691 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks 216 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack 436 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Fetch 1460 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data 277 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1460 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 277 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.CleanReplacement 1175 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Fetch 1460 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.Data 277 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.CleanReplacement 1175 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 1460 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 277 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu
|
|||
sim_ticks 117611 # Number of ticks simulated
|
||||
final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 18838 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 18837 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 346683 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 154776 # Number of bytes of host memory used
|
||||
host_seconds 0.34 # Real time elapsed on the host
|
||||
host_inst_rate 28363 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 28361 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 521945 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 148872 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 253 # Number of cache demand hits
|
||||
|
|
@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1303 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1109 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 194 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 817 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 115 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 115 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.088258 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 40 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 55 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 3 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 17 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 74 5.68% 5.68% | 17 1.30% 6.98% | 45 3.45% 10.44% | 40 3.07% 13.51% | 54 4.14% 17.65% | 99 7.60% 25.25% | 29 2.23% 27.48% | 16 1.23% 28.70% | 19 1.46% 30.16% | 22 1.69% 31.85% | 31 2.38% 34.23% | 34 2.61% 36.84% | 52 3.99% 40.83% | 48 3.68% 44.51% | 38 2.92% 47.43% | 30 2.30% 49.73% | 39 2.99% 52.72% | 21 1.61% 54.34% | 21 1.61% 55.95% | 27 2.07% 58.02% | 28 2.15% 60.17% | 37 2.84% 63.01% | 55 4.22% 67.23% | 22 1.69% 68.92% | 31 2.38% 71.30% | 21 1.61% 72.91% | 32 2.46% 75.36% | 69 5.30% 80.66% | 84 6.45% 87.11% | 103 7.90% 95.01% | 13 1.00% 96.01% | 52 3.99% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1303 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -75,5 +89,82 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 117611 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l2_cntrl0.L1_GETS 1171 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 191 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 1354 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.All_Acks 130 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data 130 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data_Exclusive 979 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBCLEANDATA 1058 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBDIRTYDATA 296 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Ack 1093 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 1362 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 1093 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 979 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 130 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_PUTX 1354 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 192 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 61 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 1093 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 1058 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 296 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Data_Exclusive 979 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 979 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGM.Data 130 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.All_Acks 130 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 130 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.Exclusive_Unblock 61 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.Exclusive_Unblock 192 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.Writeback_Ack 1093 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 1183 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 865 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 1379 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data 1362 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack_Data 1354 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.All_acks 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Use_Timeout 1361 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 525 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 646 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 305 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 3467 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 51 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 1086 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Load 112 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Ifetch 2287 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Store 27 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement 17 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_Timeout 1143 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 234 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 339 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement 268 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Load 7 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 257 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement 8 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_Timeout 218 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.All_acks 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data 1171 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 1354 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 130 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 979 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 1093 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Exclusive_Unblock 1109 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Clean_Writeback 899 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Dirty_Writeback 194 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1109 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 194 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 130 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETS 979 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Memory_Ack 193 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 1093 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Exclusive_Unblock 979 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Data 979 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Ack 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Exclusive_Unblock 130 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Memory_Data 130 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Clean_Writeback 899 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Dirty_Writeback 194 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Mar/06/2013 20:46:06
|
||||
Real time: Jun/08/2013 14:14:35
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.61
|
||||
Virtual_time_in_minutes: 0.0101667
|
||||
Virtual_time_in_hours: 0.000169444
|
||||
Virtual_time_in_days: 7.06019e-06
|
||||
Virtual_time_in_seconds: 0.54
|
||||
Virtual_time_in_minutes: 0.009
|
||||
Virtual_time_in_hours: 0.00015
|
||||
Virtual_time_in_days: 6.25e-06
|
||||
|
||||
Ruby_current_time: 113627
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 113627
|
||||
|
||||
mbytes_resident: 54.6523
|
||||
mbytes_total: 146.188
|
||||
resident_ratio: 0.373878
|
||||
|
||||
ruby_cycles_executed: [ 113628 ]
|
||||
mbytes_resident: 55.1719
|
||||
mbytes_total: 142.258
|
||||
resident_ratio: 0.387885
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -69,7 +67,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -90,10 +87,10 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10779
|
||||
page_reclaims: 11340
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_inputs: 16
|
||||
block_outputs: 96
|
||||
|
||||
Network Stats
|
||||
|
|
@ -160,805 +157,3 @@ links_utilized_percent_switch_3: 4.4341
|
|||
outgoing_messages_switch_3_link_2_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1183 ] 1183
|
||||
Ifetch [6400 ] 6400
|
||||
Store [865 ] 865
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [1364 ] 1364
|
||||
Data_Shared [161 ] 161
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [1221 ] 1221
|
||||
Ack [1 ] 1
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_Local_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
Transient_Local_GETS_Last_Token [0 ] 0
|
||||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Request_Timeout [0 ] 0
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [1220 ] 1220
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [525 ] 525
|
||||
NP Ifetch [646 ] 646
|
||||
NP Store [191 ] 191
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [0 ] 0
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Transient_Local_GETS [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Atomic [0 ] 0
|
||||
I L1_Replacement [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_Local_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_Local_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I Transient_Local_GETS_Last_Token [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [153 ] 153
|
||||
S Ifetch [331 ] 331
|
||||
S Store [20 ] 20
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [141 ] 141
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_Local_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_Local_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S Transient_Local_GETS_Last_Token [0 ] 0
|
||||
S Persistent_GETX [0 ] 0
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O Atomic [0 ] 0
|
||||
O L1_Replacement [0 ] 0
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_Local_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_Local_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O Transient_Local_GETS_Last_Token [0 ] 0
|
||||
O Persistent_GETX [0 ] 0
|
||||
O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M Load [184 ] 184
|
||||
M Ifetch [3308 ] 3308
|
||||
M Store [33 ] 33
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [945 ] 945
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
MM Load [220 ] 220
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [330 ] 330
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [268 ] 268
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M_W Load [80 ] 80
|
||||
M_W Ifetch [2115 ] 2115
|
||||
M_W Store [25 ] 25
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [6 ] 6
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
M_W Transient_Local_GETS [0 ] 0
|
||||
M_W Persistent_GETX [0 ] 0
|
||||
M_W Persistent_GETS [0 ] 0
|
||||
M_W Own_Lock_or_Unlock [0 ] 0
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [984 ] 984
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [21 ] 21
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [266 ] 266
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [4 ] 4
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [0 ] 0
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [236 ] 236
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [191 ] 191
|
||||
IM Ack [1 ] 1
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
IM Transient_Local_GETS [0 ] 0
|
||||
IM Transient_GETS_Last_Token [0 ] 0
|
||||
IM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [0 ] 0
|
||||
IM Request_Timeout [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Atomic [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [20 ] 20
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
SM Transient_GETS [0 ] 0
|
||||
SM Transient_Local_GETS [0 ] 0
|
||||
SM Transient_GETS_Last_Token [0 ] 0
|
||||
SM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
SM Persistent_GETX [0 ] 0
|
||||
SM Persistent_GETS [0 ] 0
|
||||
SM Persistent_GETS_Last_Token [0 ] 0
|
||||
SM Own_Lock_or_Unlock [0 ] 0
|
||||
SM Request_Timeout [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM Atomic [0 ] 0
|
||||
OM L1_Replacement [0 ] 0
|
||||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [0 ] 0
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
OM Transient_Local_GETS [0 ] 0
|
||||
OM Transient_GETS_Last_Token [0 ] 0
|
||||
OM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [0 ] 0
|
||||
OM Request_Timeout [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Shared [161 ] 161
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [1010 ] 1010
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
IS Transient_GETS [0 ] 0
|
||||
IS Transient_Local_GETS [0 ] 0
|
||||
IS Transient_GETS_Last_Token [0 ] 0
|
||||
IS Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [0 ] 0
|
||||
IS Request_Timeout [0 ] 0
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
I_L Store [0 ] 0
|
||||
I_L Atomic [0 ] 0
|
||||
I_L L1_Replacement [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_Local_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_Local_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
I_L Persistent_GETX [0 ] 0
|
||||
I_L Persistent_GETS [0 ] 0
|
||||
I_L Persistent_GETS_Last_Token [0 ] 0
|
||||
I_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S_L Load [0 ] 0
|
||||
S_L Ifetch [0 ] 0
|
||||
S_L Store [0 ] 0
|
||||
S_L Atomic [0 ] 0
|
||||
S_L L1_Replacement [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_Local_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_Local_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
IM_L Load [0 ] 0
|
||||
IM_L Ifetch [0 ] 0
|
||||
IM_L Store [0 ] 0
|
||||
IM_L Atomic [0 ] 0
|
||||
IM_L L1_Replacement [0 ] 0
|
||||
IM_L Data_Shared [0 ] 0
|
||||
IM_L Data_Owner [0 ] 0
|
||||
IM_L Data_All_Tokens [0 ] 0
|
||||
IM_L Ack [0 ] 0
|
||||
IM_L Transient_GETX [0 ] 0
|
||||
IM_L Transient_Local_GETX [0 ] 0
|
||||
IM_L Transient_GETS [0 ] 0
|
||||
IM_L Transient_Local_GETS [0 ] 0
|
||||
IM_L Transient_GETS_Last_Token [0 ] 0
|
||||
IM_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM_L Persistent_GETX [0 ] 0
|
||||
IM_L Persistent_GETS [0 ] 0
|
||||
IM_L Own_Lock_or_Unlock [0 ] 0
|
||||
IM_L Request_Timeout [0 ] 0
|
||||
|
||||
SM_L Load [0 ] 0
|
||||
SM_L Ifetch [0 ] 0
|
||||
SM_L Store [0 ] 0
|
||||
SM_L Atomic [0 ] 0
|
||||
SM_L L1_Replacement [0 ] 0
|
||||
SM_L Data_Shared [0 ] 0
|
||||
SM_L Data_Owner [0 ] 0
|
||||
SM_L Data_All_Tokens [0 ] 0
|
||||
SM_L Ack [0 ] 0
|
||||
SM_L Transient_GETX [0 ] 0
|
||||
SM_L Transient_Local_GETX [0 ] 0
|
||||
SM_L Transient_GETS [0 ] 0
|
||||
SM_L Transient_Local_GETS [0 ] 0
|
||||
SM_L Transient_GETS_Last_Token [0 ] 0
|
||||
SM_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
SM_L Persistent_GETX [0 ] 0
|
||||
SM_L Persistent_GETS [0 ] 0
|
||||
SM_L Persistent_GETS_Last_Token [0 ] 0
|
||||
SM_L Own_Lock_or_Unlock [0 ] 0
|
||||
SM_L Request_Timeout [0 ] 0
|
||||
|
||||
IS_L Load [0 ] 0
|
||||
IS_L Ifetch [0 ] 0
|
||||
IS_L Store [0 ] 0
|
||||
IS_L Atomic [0 ] 0
|
||||
IS_L L1_Replacement [0 ] 0
|
||||
IS_L Data_Shared [0 ] 0
|
||||
IS_L Data_Owner [0 ] 0
|
||||
IS_L Data_All_Tokens [0 ] 0
|
||||
IS_L Ack [0 ] 0
|
||||
IS_L Transient_GETX [0 ] 0
|
||||
IS_L Transient_Local_GETX [0 ] 0
|
||||
IS_L Transient_GETS [0 ] 0
|
||||
IS_L Transient_Local_GETS [0 ] 0
|
||||
IS_L Transient_GETS_Last_Token [0 ] 0
|
||||
IS_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS_L Persistent_GETX [0 ] 0
|
||||
IS_L Persistent_GETS [0 ] 0
|
||||
IS_L Own_Lock_or_Unlock [0 ] 0
|
||||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [1122 ] 1122
|
||||
L1_GETS_Last_Token [49 ] 49
|
||||
L1_GETX [211 ] 211
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [1265 ] 1265
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [84 ] 84
|
||||
Writeback_All_Tokens [1270 ] 1270
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [1010 ] 1010
|
||||
NP L1_GETX [166 ] 166
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [81 ] 81
|
||||
NP Writeback_All_Tokens [1192 ] 1192
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [0 ] 0
|
||||
NP Ack [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [1 ] 1
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [69 ] 69
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [3 ] 3
|
||||
I Writeback_All_Tokens [21 ] 21
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [49 ] 49
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [34 ] 34
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
S Writeback_Owned [0 ] 0
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Persistent_GETX [0 ] 0
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [17 ] 17
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [38 ] 38
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [57 ] 57
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Persistent_GETX [0 ] 0
|
||||
O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [112 ] 112
|
||||
M L1_GETX [26 ] 26
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [1124 ] 1124
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
I_L L1_GETX [0 ] 0
|
||||
I_L L1_INV [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [0 ] 0
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [0 ] 0
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [0 ] 0
|
||||
I_L Persistent_GETS [0 ] 0
|
||||
I_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
S_L L1_GETX [0 ] 0
|
||||
S_L L1_INV [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L L2_Replacement [0 ] 0
|
||||
S_L Writeback_Tokens [0 ] 0
|
||||
S_L Writeback_Shared_Data [0 ] 0
|
||||
S_L Writeback_All_Tokens [0 ] 0
|
||||
S_L Writeback_Owned [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1407
|
||||
memory_reads: 1178
|
||||
memory_writes: 229
|
||||
memory_refreshes: 789
|
||||
memory_total_request_delays: 323
|
||||
memory_delays_per_request: 0.229566
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 323
|
||||
memory_stalls_for_bank_busy: 81
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 19
|
||||
memory_stalls_for_bus: 213
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 10
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 41 54 102 33 16 20 22 32 34 53 50 40 31 40 21 21 21 28 38 89 22 31 23 32 72 95 141 15 53
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [278 ] 278
|
||||
GETS [1034 ] 1034
|
||||
Lockdown [0 ] 0
|
||||
Unlockdown [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [9 ] 9
|
||||
Data_All_Tokens [220 ] 220
|
||||
Ack_Owner [29 ] 29
|
||||
Ack_Owner_All_Tokens [904 ] 904
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [34 ] 34
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [1178 ] 1178
|
||||
Memory_Ack [229 ] 229
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [168 ] 168
|
||||
O GETS [1010 ] 1010
|
||||
O Lockdown [0 ] 0
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [34 ] 34
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [17 ] 17
|
||||
NO GETS [0 ] 0
|
||||
NO Lockdown [0 ] 0
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [9 ] 9
|
||||
NO Data_All_Tokens [220 ] 220
|
||||
NO Ack_Owner [29 ] 29
|
||||
NO Ack_Owner_All_Tokens [904 ] 904
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [0 ] 0
|
||||
L GETS [0 ] 0
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [0 ] 0
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [0 ] 0
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [0 ] 0
|
||||
L Tokens [0 ] 0
|
||||
L DMA_READ [0 ] 0
|
||||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [93 ] 93
|
||||
O_W GETS [24 ] 24
|
||||
O_W Lockdown [0 ] 0
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_W Data_Owner [0 ] 0
|
||||
O_W Data_All_Tokens [0 ] 0
|
||||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [229 ] 229
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [0 ] 0
|
||||
L_O_W GETS [0 ] 0
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
L_O_W Data_All_Tokens [0 ] 0
|
||||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [0 ] 0
|
||||
L_O_W Memory_Ack [0 ] 0
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_NO_W GETX [0 ] 0
|
||||
L_NO_W GETS [0 ] 0
|
||||
L_NO_W Lockdown [0 ] 0
|
||||
L_NO_W Unlockdown [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_NO_W Data_Owner [0 ] 0
|
||||
L_NO_W Data_All_Tokens [0 ] 0
|
||||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [0 ] 0
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L_W GETX [0 ] 0
|
||||
DR_L_W GETS [0 ] 0
|
||||
DR_L_W Lockdown [0 ] 0
|
||||
DR_L_W Unlockdown [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L_W Data_Owner [0 ] 0
|
||||
DR_L_W Data_All_Tokens [0 ] 0
|
||||
DR_L_W Ack_Owner [0 ] 0
|
||||
DR_L_W Tokens [0 ] 0
|
||||
DR_L_W Ack_All_Tokens [0 ] 0
|
||||
DR_L_W Request_Timeout [0 ] 0
|
||||
DR_L_W Memory_Data [0 ] 0
|
||||
DR_L_W DMA_READ [0 ] 0
|
||||
DR_L_W DMA_WRITE [0 ] 0
|
||||
DR_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L_W GETX [0 ] 0
|
||||
DW_L_W GETS [0 ] 0
|
||||
DW_L_W Lockdown [0 ] 0
|
||||
DW_L_W Unlockdown [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L_W Data_Owner [0 ] 0
|
||||
DW_L_W Data_All_Tokens [0 ] 0
|
||||
DW_L_W Ack_Owner [0 ] 0
|
||||
DW_L_W Tokens [0 ] 0
|
||||
DW_L_W Ack_All_Tokens [0 ] 0
|
||||
DW_L_W Request_Timeout [0 ] 0
|
||||
DW_L_W Memory_Ack [0 ] 0
|
||||
DW_L_W DMA_READ [0 ] 0
|
||||
DW_L_W DMA_WRITE [0 ] 0
|
||||
DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [0 ] 0
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_W Data_Owner [0 ] 0
|
||||
NO_W Data_All_Tokens [0 ] 0
|
||||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [1178 ] 1178
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW_W GETX [0 ] 0
|
||||
O_DW_W GETS [0 ] 0
|
||||
O_DW_W Lockdown [0 ] 0
|
||||
O_DW_W Unlockdown [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW_W Data_Owner [0 ] 0
|
||||
O_DW_W Data_All_Tokens [0 ] 0
|
||||
O_DW_W Ack_Owner [0 ] 0
|
||||
O_DW_W Tokens [0 ] 0
|
||||
O_DW_W Ack_All_Tokens [0 ] 0
|
||||
O_DW_W Request_Timeout [0 ] 0
|
||||
O_DW_W Memory_Ack [0 ] 0
|
||||
O_DW_W DMA_READ [0 ] 0
|
||||
O_DW_W DMA_WRITE [0 ] 0
|
||||
O_DW_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DR_W GETX [0 ] 0
|
||||
O_DR_W GETS [0 ] 0
|
||||
O_DR_W Lockdown [0 ] 0
|
||||
O_DR_W Unlockdown [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DR_W Data_Owner [0 ] 0
|
||||
O_DR_W Data_All_Tokens [0 ] 0
|
||||
O_DR_W Ack_Owner [0 ] 0
|
||||
O_DR_W Tokens [0 ] 0
|
||||
O_DR_W Ack_All_Tokens [0 ] 0
|
||||
O_DR_W Request_Timeout [0 ] 0
|
||||
O_DR_W Memory_Data [0 ] 0
|
||||
O_DR_W DMA_READ [0 ] 0
|
||||
O_DR_W DMA_WRITE [0 ] 0
|
||||
O_DR_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW GETX [0 ] 0
|
||||
O_DW GETS [0 ] 0
|
||||
O_DW Lockdown [0 ] 0
|
||||
O_DW Unlockdown [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW Data_Owner [0 ] 0
|
||||
O_DW Data_All_Tokens [0 ] 0
|
||||
O_DW Ack_Owner [0 ] 0
|
||||
O_DW Ack_Owner_All_Tokens [0 ] 0
|
||||
O_DW Tokens [0 ] 0
|
||||
O_DW Ack_All_Tokens [0 ] 0
|
||||
O_DW Request_Timeout [0 ] 0
|
||||
O_DW DMA_READ [0 ] 0
|
||||
O_DW DMA_WRITE [0 ] 0
|
||||
O_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DW GETX [0 ] 0
|
||||
NO_DW GETS [0 ] 0
|
||||
NO_DW Lockdown [0 ] 0
|
||||
NO_DW Unlockdown [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DW Data_Owner [0 ] 0
|
||||
NO_DW Data_All_Tokens [0 ] 0
|
||||
NO_DW Tokens [0 ] 0
|
||||
NO_DW Request_Timeout [0 ] 0
|
||||
NO_DW DMA_READ [0 ] 0
|
||||
NO_DW DMA_WRITE [0 ] 0
|
||||
NO_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DR GETX [0 ] 0
|
||||
NO_DR GETS [0 ] 0
|
||||
NO_DR Lockdown [0 ] 0
|
||||
NO_DR Unlockdown [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DR Data_Owner [0 ] 0
|
||||
NO_DR Data_All_Tokens [0 ] 0
|
||||
NO_DR Tokens [0 ] 0
|
||||
NO_DR Request_Timeout [0 ] 0
|
||||
NO_DR DMA_READ [0 ] 0
|
||||
NO_DR DMA_WRITE [0 ] 0
|
||||
NO_DR DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L GETX [0 ] 0
|
||||
DW_L GETS [0 ] 0
|
||||
DW_L Lockdown [0 ] 0
|
||||
DW_L Unlockdown [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L Data_Owner [0 ] 0
|
||||
DW_L Data_All_Tokens [0 ] 0
|
||||
DW_L Ack_Owner [0 ] 0
|
||||
DW_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DW_L Tokens [0 ] 0
|
||||
DW_L Request_Timeout [0 ] 0
|
||||
DW_L DMA_READ [0 ] 0
|
||||
DW_L DMA_WRITE [0 ] 0
|
||||
DW_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L GETX [0 ] 0
|
||||
DR_L GETS [0 ] 0
|
||||
DR_L Lockdown [0 ] 0
|
||||
DR_L Unlockdown [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L Data_Owner [0 ] 0
|
||||
DR_L Data_All_Tokens [0 ] 0
|
||||
DR_L Ack_Owner [0 ] 0
|
||||
DR_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DR_L Tokens [0 ] 0
|
||||
DR_L Request_Timeout [0 ] 0
|
||||
DR_L DMA_READ [0 ] 0
|
||||
DR_L DMA_WRITE [0 ] 0
|
||||
DR_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu
|
|||
sim_ticks 113627 # Number of ticks simulated
|
||||
final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 26434 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 26432 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 469977 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 153588 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_inst_rate 34924 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 34920 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 620890 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 145676 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
|
||||
|
|
@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1407 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1178 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 229 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 789 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 323 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 323 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.229566 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 81 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 213 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 10 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 19 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 75 5.33% 5.33% | 17 1.21% 6.54% | 45 3.20% 9.74% | 41 2.91% 12.65% | 54 3.84% 16.49% | 102 7.25% 23.74% | 33 2.35% 26.08% | 16 1.14% 27.22% | 20 1.42% 28.64% | 22 1.56% 30.21% | 32 2.27% 32.48% | 34 2.42% 34.90% | 53 3.77% 38.66% | 50 3.55% 42.22% | 40 2.84% 45.06% | 31 2.20% 47.26% | 40 2.84% 50.11% | 21 1.49% 51.60% | 21 1.49% 53.09% | 21 1.49% 54.58% | 28 1.99% 56.57% | 38 2.70% 59.28% | 89 6.33% 65.60% | 22 1.56% 67.16% | 31 2.20% 69.37% | 23 1.63% 71.00% | 32 2.27% 73.28% | 72 5.12% 78.39% | 95 6.75% 85.15% | 141 10.02% 95.17% | 15 1.07% 96.23% | 53 3.77% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1407 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -75,5 +89,85 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 113627 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l2_cntrl0.L1_GETS 1122 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS_Last_Token 49 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 211 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 1265 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Shared_Data 84 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_All_Tokens 1270 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 1010 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 166 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_Shared_Data 81 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 1192 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L2_Replacement 69 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_Shared_Data 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_All_Tokens 21 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETS_Last_Token 49 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L2_Replacement 34 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L1_GETX 17 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L2_Replacement 38 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Writeback_All_Tokens 57 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 112 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 26 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 1124 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 1183 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 865 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 1364 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Shared 161 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_All_Tokens 1221 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ack 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Use_TimeoutNoStarvers 1220 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Load 153 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch 331 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Store 20 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement 141 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 184 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 3308 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 33 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 945 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 220 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 330 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement 268 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Load 80 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Ifetch 2115 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Store 25 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers 984 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Load 21 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 266 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement 4 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers 236 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_All_Tokens 191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Ack 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.SM.Data_All_Tokens 20 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Shared 161 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_All_Tokens 1010 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 278 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 1034 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_Owner 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_All_Tokens 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner 29 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 904 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_All_Tokens 34 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1178 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 229 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETX 168 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETS 1010 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Ack_All_Tokens 34 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETX 17 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_Owner 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_All_Tokens 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner 29 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 904 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.GETX 93 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.GETS 24 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Memory_Ack 229 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Memory_Data 1178 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Mar/06/2013 20:34:50
|
||||
Real time: Jun/08/2013 13:27:45
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.61
|
||||
Virtual_time_in_minutes: 0.0101667
|
||||
Virtual_time_in_hours: 0.000169444
|
||||
Virtual_time_in_days: 7.06019e-06
|
||||
Virtual_time_in_seconds: 0.51
|
||||
Virtual_time_in_minutes: 0.0085
|
||||
Virtual_time_in_hours: 0.000141667
|
||||
Virtual_time_in_days: 5.90278e-06
|
||||
|
||||
Ruby_current_time: 93341
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 93341
|
||||
|
||||
mbytes_resident: 53.8438
|
||||
mbytes_total: 146.117
|
||||
resident_ratio: 0.36855
|
||||
|
||||
ruby_cycles_executed: [ 93342 ]
|
||||
mbytes_resident: 55.2734
|
||||
mbytes_total: 143.172
|
||||
resident_ratio: 0.386118
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -68,7 +66,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -89,10 +86,10 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11071
|
||||
page_faults: 0
|
||||
page_reclaims: 15392
|
||||
page_faults: 3
|
||||
swaps: 0
|
||||
block_inputs: 24
|
||||
block_inputs: 2160
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
|
|
@ -144,749 +141,3 @@ links_utilized_percent_switch_2: 4.80443
|
|||
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1191 ] 1191
|
||||
Ifetch [6411 ] 6411
|
||||
Store [892 ] 892
|
||||
L2_Replacement [1143 ] 1143
|
||||
L1_to_L2 [1354 ] 1354
|
||||
Trigger_L2_to_L1D [138 ] 138
|
||||
Trigger_L2_to_L1I [65 ] 65
|
||||
Complete_L2_to_L1 [203 ] 203
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [1159 ] 1159
|
||||
Writeback_Ack [1143 ] 1143
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [1159 ] 1159
|
||||
Flush_line [0 ] 0
|
||||
Block_Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [420 ] 420
|
||||
I Ifetch [581 ] 581
|
||||
I Store [158 ] 158
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
I Trigger_L2_to_L1I [0 ] 0
|
||||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S L2_Replacement [0 ] 0
|
||||
S L1_to_L2 [0 ] 0
|
||||
S Trigger_L2_to_L1D [0 ] 0
|
||||
S Trigger_L2_to_L1I [0 ] 0
|
||||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
S Flush_line [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O L2_Replacement [0 ] 0
|
||||
O L1_to_L2 [0 ] 0
|
||||
O Trigger_L2_to_L1D [0 ] 0
|
||||
O Trigger_L2_to_L1I [0 ] 0
|
||||
O Other_GETX [0 ] 0
|
||||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [304 ] 304
|
||||
M Ifetch [5754 ] 5754
|
||||
M Store [60 ] 60
|
||||
M L2_Replacement [923 ] 923
|
||||
M L1_to_L2 [1061 ] 1061
|
||||
M Trigger_L2_to_L1D [68 ] 68
|
||||
M Trigger_L2_to_L1I [65 ] 65
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [354 ] 354
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [614 ] 614
|
||||
MM L2_Replacement [220 ] 220
|
||||
MM L1_to_L2 [293 ] 293
|
||||
MM Trigger_L2_to_L1D [70 ] 70
|
||||
MM Trigger_L2_to_L1I [0 ] 0
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
MM Flush_line [0 ] 0
|
||||
|
||||
IR Load [0 ] 0
|
||||
IR Ifetch [0 ] 0
|
||||
IR Store [0 ] 0
|
||||
IR L1_to_L2 [0 ] 0
|
||||
IR Flush_line [0 ] 0
|
||||
|
||||
SR Load [0 ] 0
|
||||
SR Ifetch [0 ] 0
|
||||
SR Store [0 ] 0
|
||||
SR L1_to_L2 [0 ] 0
|
||||
SR Flush_line [0 ] 0
|
||||
|
||||
OR Load [0 ] 0
|
||||
OR Ifetch [0 ] 0
|
||||
OR Store [0 ] 0
|
||||
OR L1_to_L2 [0 ] 0
|
||||
OR Flush_line [0 ] 0
|
||||
|
||||
MR Load [62 ] 62
|
||||
MR Ifetch [65 ] 65
|
||||
MR Store [6 ] 6
|
||||
MR L1_to_L2 [0 ] 0
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [43 ] 43
|
||||
MMR Ifetch [0 ] 0
|
||||
MMR Store [27 ] 27
|
||||
MMR L1_to_L2 [0 ] 0
|
||||
MMR Flush_line [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [0 ] 0
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [158 ] 158
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM L2_Replacement [0 ] 0
|
||||
SM L1_to_L2 [0 ] 0
|
||||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
SM Flush_line [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM L2_Replacement [0 ] 0
|
||||
OM L1_to_L2 [0 ] 0
|
||||
OM Other_GETX [0 ] 0
|
||||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
OM All_acks_no_sharers [0 ] 0
|
||||
OM Flush_line [0 ] 0
|
||||
|
||||
ISM Load [0 ] 0
|
||||
ISM Ifetch [0 ] 0
|
||||
ISM Store [0 ] 0
|
||||
ISM L2_Replacement [0 ] 0
|
||||
ISM L1_to_L2 [0 ] 0
|
||||
ISM Ack [0 ] 0
|
||||
ISM All_acks_no_sharers [0 ] 0
|
||||
ISM Flush_line [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [0 ] 0
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [1001 ] 1001
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [0 ] 0
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [0 ] 0
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [158 ] 158
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [0 ] 0
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [1001 ] 1001
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
SS Store [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L1_to_L2 [0 ] 0
|
||||
SS Ack [0 ] 0
|
||||
SS Shared_Ack [0 ] 0
|
||||
SS All_acks [0 ] 0
|
||||
SS All_acks_no_sharers [0 ] 0
|
||||
SS Flush_line [0 ] 0
|
||||
|
||||
OI Load [0 ] 0
|
||||
OI Ifetch [0 ] 0
|
||||
OI Store [0 ] 0
|
||||
OI L2_Replacement [0 ] 0
|
||||
OI L1_to_L2 [0 ] 0
|
||||
OI Other_GETX [0 ] 0
|
||||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [8 ] 8
|
||||
MI Ifetch [11 ] 11
|
||||
MI Store [27 ] 27
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [1143 ] 1143
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
II Store [0 ] 0
|
||||
II L2_Replacement [0 ] 0
|
||||
II L1_to_L2 [0 ] 0
|
||||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
II Flush_line [0 ] 0
|
||||
|
||||
IT Load [0 ] 0
|
||||
IT Ifetch [0 ] 0
|
||||
IT Store [0 ] 0
|
||||
IT L2_Replacement [0 ] 0
|
||||
IT L1_to_L2 [0 ] 0
|
||||
IT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
ST Ifetch [0 ] 0
|
||||
ST Store [0 ] 0
|
||||
ST L2_Replacement [0 ] 0
|
||||
ST L1_to_L2 [0 ] 0
|
||||
ST Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
OT Ifetch [0 ] 0
|
||||
OT Store [0 ] 0
|
||||
OT L2_Replacement [0 ] 0
|
||||
OT L1_to_L2 [0 ] 0
|
||||
OT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [0 ] 0
|
||||
MT Complete_L2_to_L1 [133 ] 133
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [0 ] 0
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [0 ] 0
|
||||
MMT Complete_L2_to_L1 [70 ] 70
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [0 ] 0
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
MM_F Ifetch [0 ] 0
|
||||
MM_F Store [0 ] 0
|
||||
MM_F L1_to_L2 [0 ] 0
|
||||
MM_F Other_GETX [0 ] 0
|
||||
MM_F Other_GETS [0 ] 0
|
||||
MM_F Merged_GETS [0 ] 0
|
||||
MM_F Other_GETS_No_Mig [0 ] 0
|
||||
MM_F NC_DMA_GETS [0 ] 0
|
||||
MM_F Invalidate [0 ] 0
|
||||
MM_F Ack [0 ] 0
|
||||
MM_F All_acks [0 ] 0
|
||||
MM_F All_acks_no_sharers [0 ] 0
|
||||
MM_F Flush_line [0 ] 0
|
||||
MM_F Block_Ack [0 ] 0
|
||||
|
||||
IM_F Load [0 ] 0
|
||||
IM_F Ifetch [0 ] 0
|
||||
IM_F Store [0 ] 0
|
||||
IM_F L2_Replacement [0 ] 0
|
||||
IM_F L1_to_L2 [0 ] 0
|
||||
IM_F Other_GETX [0 ] 0
|
||||
IM_F Other_GETS [0 ] 0
|
||||
IM_F Other_GETS_No_Mig [0 ] 0
|
||||
IM_F NC_DMA_GETS [0 ] 0
|
||||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [0 ] 0
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
ISM_F Ifetch [0 ] 0
|
||||
ISM_F Store [0 ] 0
|
||||
ISM_F L2_Replacement [0 ] 0
|
||||
ISM_F L1_to_L2 [0 ] 0
|
||||
ISM_F Ack [0 ] 0
|
||||
ISM_F All_acks_no_sharers [0 ] 0
|
||||
ISM_F Flush_line [0 ] 0
|
||||
|
||||
SM_F Load [0 ] 0
|
||||
SM_F Ifetch [0 ] 0
|
||||
SM_F Store [0 ] 0
|
||||
SM_F L2_Replacement [0 ] 0
|
||||
SM_F L1_to_L2 [0 ] 0
|
||||
SM_F Other_GETX [0 ] 0
|
||||
SM_F Other_GETS [0 ] 0
|
||||
SM_F Other_GETS_No_Mig [0 ] 0
|
||||
SM_F NC_DMA_GETS [0 ] 0
|
||||
SM_F Invalidate [0 ] 0
|
||||
SM_F Ack [0 ] 0
|
||||
SM_F Data [0 ] 0
|
||||
SM_F Exclusive_Data [0 ] 0
|
||||
SM_F Flush_line [0 ] 0
|
||||
|
||||
OM_F Load [0 ] 0
|
||||
OM_F Ifetch [0 ] 0
|
||||
OM_F Store [0 ] 0
|
||||
OM_F L2_Replacement [0 ] 0
|
||||
OM_F L1_to_L2 [0 ] 0
|
||||
OM_F Other_GETX [0 ] 0
|
||||
OM_F Other_GETS [0 ] 0
|
||||
OM_F Merged_GETS [0 ] 0
|
||||
OM_F Other_GETS_No_Mig [0 ] 0
|
||||
OM_F NC_DMA_GETS [0 ] 0
|
||||
OM_F Invalidate [0 ] 0
|
||||
OM_F Ack [0 ] 0
|
||||
OM_F All_acks [0 ] 0
|
||||
OM_F All_acks_no_sharers [0 ] 0
|
||||
OM_F Flush_line [0 ] 0
|
||||
|
||||
MM_WF Load [0 ] 0
|
||||
MM_WF Ifetch [0 ] 0
|
||||
MM_WF Store [0 ] 0
|
||||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [0 ] 0
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1379
|
||||
memory_reads: 1159
|
||||
memory_writes: 220
|
||||
memory_refreshes: 649
|
||||
memory_total_request_delays: 167
|
||||
memory_delays_per_request: 0.121102
|
||||
memory_delays_in_input_queue: 1
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 166
|
||||
memory_stalls_for_bank_busy: 114
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 11
|
||||
memory_stalls_for_bus: 33
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 8
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [186 ] 186
|
||||
GETS [1022 ] 1022
|
||||
PUT [1143 ] 1143
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [1159 ] 1159
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [923 ] 923
|
||||
Writeback_Exclusive_Dirty [220 ] 220
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1159 ] 1159
|
||||
Memory_Ack [220 ] 220
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [0 ] 0
|
||||
All_acks_and_shared_data [0 ] 0
|
||||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [0 ] 0
|
||||
PUTF [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
NX GETS [0 ] 0
|
||||
NX PUT [0 ] 0
|
||||
NX Pf_Replacement [0 ] 0
|
||||
NX DMA_READ [0 ] 0
|
||||
NX DMA_WRITE [0 ] 0
|
||||
NX GETF [0 ] 0
|
||||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [1143 ] 1143
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [0 ] 0
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
S PUT [0 ] 0
|
||||
S Pf_Replacement [0 ] 0
|
||||
S DMA_READ [0 ] 0
|
||||
S DMA_WRITE [0 ] 0
|
||||
S GETF [0 ] 0
|
||||
|
||||
O GETX [0 ] 0
|
||||
O GETS [0 ] 0
|
||||
O PUT [0 ] 0
|
||||
O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [158 ] 158
|
||||
E GETS [1001 ] 1001
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [0 ] 0
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
O_R PUT [0 ] 0
|
||||
O_R Pf_Replacement [0 ] 0
|
||||
O_R DMA_READ [0 ] 0
|
||||
O_R DMA_WRITE [0 ] 0
|
||||
O_R Ack [0 ] 0
|
||||
O_R All_acks_and_data_no_sharers [0 ] 0
|
||||
O_R GETF [0 ] 0
|
||||
|
||||
S_R GETX [0 ] 0
|
||||
S_R GETS [0 ] 0
|
||||
S_R PUT [0 ] 0
|
||||
S_R Pf_Replacement [0 ] 0
|
||||
S_R DMA_READ [0 ] 0
|
||||
S_R DMA_WRITE [0 ] 0
|
||||
S_R Ack [0 ] 0
|
||||
S_R Data [0 ] 0
|
||||
S_R All_acks_and_data_no_sharers [0 ] 0
|
||||
S_R GETF [0 ] 0
|
||||
|
||||
NO_R GETX [0 ] 0
|
||||
NO_R GETS [0 ] 0
|
||||
NO_R PUT [0 ] 0
|
||||
NO_R Pf_Replacement [0 ] 0
|
||||
NO_R DMA_READ [0 ] 0
|
||||
NO_R DMA_WRITE [0 ] 0
|
||||
NO_R Ack [0 ] 0
|
||||
NO_R Data [0 ] 0
|
||||
NO_R Exclusive_Data [0 ] 0
|
||||
NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_R GETF [0 ] 0
|
||||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [0 ] 0
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [1159 ] 1159
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
NO_B GETF [0 ] 0
|
||||
|
||||
NO_B_X GETX [0 ] 0
|
||||
NO_B_X GETS [0 ] 0
|
||||
NO_B_X PUT [0 ] 0
|
||||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
NO_B_X GETF [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
NO_B_S PUT [0 ] 0
|
||||
NO_B_S UnblockS [0 ] 0
|
||||
NO_B_S UnblockM [0 ] 0
|
||||
NO_B_S Pf_Replacement [0 ] 0
|
||||
NO_B_S DMA_READ [0 ] 0
|
||||
NO_B_S DMA_WRITE [0 ] 0
|
||||
NO_B_S GETF [0 ] 0
|
||||
|
||||
NO_B_S_W GETX [0 ] 0
|
||||
NO_B_S_W GETS [0 ] 0
|
||||
NO_B_S_W PUT [0 ] 0
|
||||
NO_B_S_W UnblockS [0 ] 0
|
||||
NO_B_S_W Pf_Replacement [0 ] 0
|
||||
NO_B_S_W DMA_READ [0 ] 0
|
||||
NO_B_S_W DMA_WRITE [0 ] 0
|
||||
NO_B_S_W All_Unblocks [0 ] 0
|
||||
NO_B_S_W GETF [0 ] 0
|
||||
|
||||
O_B GETX [0 ] 0
|
||||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
O_B GETF [0 ] 0
|
||||
|
||||
NO_B_W GETX [0 ] 0
|
||||
NO_B_W GETS [0 ] 0
|
||||
NO_B_W PUT [0 ] 0
|
||||
NO_B_W UnblockS [0 ] 0
|
||||
NO_B_W UnblockM [0 ] 0
|
||||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [1159 ] 1159
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
O_B_W PUT [0 ] 0
|
||||
O_B_W UnblockS [0 ] 0
|
||||
O_B_W Pf_Replacement [0 ] 0
|
||||
O_B_W DMA_READ [0 ] 0
|
||||
O_B_W DMA_WRITE [0 ] 0
|
||||
O_B_W Memory_Data [0 ] 0
|
||||
O_B_W GETF [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W PUT [0 ] 0
|
||||
NO_W Pf_Replacement [0 ] 0
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W Memory_Data [0 ] 0
|
||||
NO_W GETF [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W PUT [0 ] 0
|
||||
O_W Pf_Replacement [0 ] 0
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W GETF [0 ] 0
|
||||
|
||||
NO_DW_B_W GETX [0 ] 0
|
||||
NO_DW_B_W GETS [0 ] 0
|
||||
NO_DW_B_W PUT [0 ] 0
|
||||
NO_DW_B_W Pf_Replacement [0 ] 0
|
||||
NO_DW_B_W DMA_READ [0 ] 0
|
||||
NO_DW_B_W DMA_WRITE [0 ] 0
|
||||
NO_DW_B_W Ack [0 ] 0
|
||||
NO_DW_B_W Data [0 ] 0
|
||||
NO_DW_B_W Exclusive_Data [0 ] 0
|
||||
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DW_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_W GETX [0 ] 0
|
||||
NO_DR_B_W GETS [0 ] 0
|
||||
NO_DR_B_W PUT [0 ] 0
|
||||
NO_DR_B_W Pf_Replacement [0 ] 0
|
||||
NO_DR_B_W DMA_READ [0 ] 0
|
||||
NO_DR_B_W DMA_WRITE [0 ] 0
|
||||
NO_DR_B_W Memory_Data [0 ] 0
|
||||
NO_DR_B_W Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Data [0 ] 0
|
||||
NO_DR_B_W Data [0 ] 0
|
||||
NO_DR_B_W Exclusive_Data [0 ] 0
|
||||
NO_DR_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_D GETX [0 ] 0
|
||||
NO_DR_B_D GETS [0 ] 0
|
||||
NO_DR_B_D PUT [0 ] 0
|
||||
NO_DR_B_D Pf_Replacement [0 ] 0
|
||||
NO_DR_B_D DMA_READ [0 ] 0
|
||||
NO_DR_B_D DMA_WRITE [0 ] 0
|
||||
NO_DR_B_D Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Data [0 ] 0
|
||||
NO_DR_B_D Data [0 ] 0
|
||||
NO_DR_B_D Exclusive_Data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B_D GETF [0 ] 0
|
||||
|
||||
NO_DR_B GETX [0 ] 0
|
||||
NO_DR_B GETS [0 ] 0
|
||||
NO_DR_B PUT [0 ] 0
|
||||
NO_DR_B Pf_Replacement [0 ] 0
|
||||
NO_DR_B DMA_READ [0 ] 0
|
||||
NO_DR_B DMA_WRITE [0 ] 0
|
||||
NO_DR_B Ack [0 ] 0
|
||||
NO_DR_B Shared_Ack [0 ] 0
|
||||
NO_DR_B Shared_Data [0 ] 0
|
||||
NO_DR_B Data [0 ] 0
|
||||
NO_DR_B Exclusive_Data [0 ] 0
|
||||
NO_DR_B All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B GETF [0 ] 0
|
||||
|
||||
NO_DW_W GETX [0 ] 0
|
||||
NO_DW_W GETS [0 ] 0
|
||||
NO_DW_W PUT [0 ] 0
|
||||
NO_DW_W Pf_Replacement [0 ] 0
|
||||
NO_DW_W DMA_READ [0 ] 0
|
||||
NO_DW_W DMA_WRITE [0 ] 0
|
||||
NO_DW_W Memory_Ack [0 ] 0
|
||||
NO_DW_W GETF [0 ] 0
|
||||
|
||||
O_DR_B_W GETX [0 ] 0
|
||||
O_DR_B_W GETS [0 ] 0
|
||||
O_DR_B_W PUT [0 ] 0
|
||||
O_DR_B_W Pf_Replacement [0 ] 0
|
||||
O_DR_B_W DMA_READ [0 ] 0
|
||||
O_DR_B_W DMA_WRITE [0 ] 0
|
||||
O_DR_B_W Memory_Data [0 ] 0
|
||||
O_DR_B_W Ack [0 ] 0
|
||||
O_DR_B_W Shared_Ack [0 ] 0
|
||||
O_DR_B_W GETF [0 ] 0
|
||||
|
||||
O_DR_B GETX [0 ] 0
|
||||
O_DR_B GETS [0 ] 0
|
||||
O_DR_B PUT [0 ] 0
|
||||
O_DR_B Pf_Replacement [0 ] 0
|
||||
O_DR_B DMA_READ [0 ] 0
|
||||
O_DR_B DMA_WRITE [0 ] 0
|
||||
O_DR_B Ack [0 ] 0
|
||||
O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [27 ] 27
|
||||
WB GETS [19 ] 19
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [923 ] 923
|
||||
WB Writeback_Exclusive_Dirty [220 ] 220
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
WB GETF [0 ] 0
|
||||
|
||||
WB_O_W GETX [0 ] 0
|
||||
WB_O_W GETS [0 ] 0
|
||||
WB_O_W PUT [0 ] 0
|
||||
WB_O_W Pf_Replacement [0 ] 0
|
||||
WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [1 ] 1
|
||||
WB_E_W GETS [2 ] 2
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [220 ] 220
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
NO_F GETS [0 ] 0
|
||||
NO_F PUT [0 ] 0
|
||||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [0 ] 0
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
NO_F_W PUT [0 ] 0
|
||||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu
|
|||
sim_ticks 93341 # Number of ticks simulated
|
||||
final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22966 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22964 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 335419 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 152500 # Number of bytes of host memory used
|
||||
host_seconds 0.28 # Real time elapsed on the host
|
||||
host_inst_rate 15100 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 15100 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 220554 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 146612 # Number of bytes of host memory used
|
||||
host_seconds 0.42 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits
|
||||
|
|
@ -20,6 +20,21 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1379 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1159 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 220 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 649 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 166 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 1 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 167 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.121102 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 114 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 33 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 8 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 11 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 75 5.44% 5.44% | 17 1.23% 6.67% | 45 3.26% 9.93% | 40 2.90% 12.84% | 54 3.92% 16.75% | 101 7.32% 24.08% | 33 2.39% 26.47% | 16 1.16% 27.63% | 20 1.45% 29.08% | 22 1.60% 30.67% | 32 2.32% 32.99% | 34 2.47% 35.46% | 53 3.84% 39.30% | 50 3.63% 42.93% | 39 2.83% 45.76% | 31 2.25% 48.01% | 39 2.83% 50.83% | 22 1.60% 52.43% | 21 1.52% 53.95% | 27 1.96% 55.91% | 28 2.03% 57.94% | 38 2.76% 60.70% | 81 5.87% 66.57% | 22 1.60% 68.17% | 31 2.25% 70.41% | 23 1.67% 72.08% | 32 2.32% 74.40% | 72 5.22% 79.62% | 89 6.45% 86.08% | 126 9.14% 95.21% | 14 1.02% 96.23% | 52 3.77% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1379 # Number of accesses per bank
|
||||
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
|
|
@ -78,5 +93,66 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 93341 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 1191 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 6411 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 892 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L2_Replacement 1143 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_to_L2 1354 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1D 138 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1I 65 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Complete_L2_to_L1 203 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data 1159 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 1143 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.All_acks_no_sharers 1159 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 420 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 581 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 158 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 304 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 5754 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 60 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L2_Replacement 923 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_to_L2 1061 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 68 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1I 65 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 354 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 614 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L2_Replacement 220 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_to_L2 293 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 70 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Load 62 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Ifetch 65 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Store 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Load 43 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Store 27 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data 158 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 1001 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 158 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data 1001 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Load 8 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Ifetch 11 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Store 27 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 1143 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 133 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 70 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 186 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 1022 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUT 1143 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.UnblockM 1159 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1159 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.PUT 1143 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETX 158 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETS 1001 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.UnblockM 1159 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_W.Memory_Data 1159 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETX 27 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETS 19 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.GETX 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 220 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Mar/06/2013 20:31:07
|
||||
Real time: Jun/08/2013 13:51:49
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.63
|
||||
Virtual_time_in_minutes: 0.0105
|
||||
Virtual_time_in_hours: 0.000175
|
||||
Virtual_time_in_days: 7.29167e-06
|
||||
Virtual_time_in_seconds: 0.5
|
||||
Virtual_time_in_minutes: 0.00833333
|
||||
Virtual_time_in_hours: 0.000138889
|
||||
Virtual_time_in_days: 5.78704e-06
|
||||
|
||||
Ruby_current_time: 143853
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 143853
|
||||
|
||||
mbytes_resident: 55.1172
|
||||
mbytes_total: 146.695
|
||||
resident_ratio: 0.375806
|
||||
|
||||
ruby_cycles_executed: [ 143854 ]
|
||||
mbytes_resident: 55.0938
|
||||
mbytes_total: 142.211
|
||||
resident_ratio: 0.387464
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -64,7 +62,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -85,10 +82,10 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10897
|
||||
page_reclaims: 11329
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 336
|
||||
block_inputs: 0
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
|
|
@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 6.00613
|
|||
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1183 ] 1183
|
||||
Ifetch [6400 ] 6400
|
||||
Store [865 ] 865
|
||||
Data [1730 ] 1730
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [1726 ] 1726
|
||||
Writeback_Ack [1726 ] 1726
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [727 ] 727
|
||||
I Ifetch [730 ] 730
|
||||
I Store [273 ] 273
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [456 ] 456
|
||||
M Ifetch [5670 ] 5670
|
||||
M Store [592 ] 592
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1726 ] 1726
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [1726 ] 1726
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [1457 ] 1457
|
||||
|
||||
IM Data [273 ] 273
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 3456
|
||||
memory_reads: 1730
|
||||
memory_writes: 1726
|
||||
memory_refreshes: 999
|
||||
memory_total_request_delays: 3048
|
||||
memory_delays_per_request: 0.881944
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 11
|
||||
memory_delays_stalled_at_head_of_bank_queue: 3037
|
||||
memory_stalls_for_bank_busy: 1500
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 107
|
||||
memory_stalls_for_bus: 1375
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 55
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [1730 ] 1730
|
||||
GETS [0 ] 0
|
||||
PUTX [1726 ] 1726
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1730 ] 1730
|
||||
Memory_Ack [1726 ] 1726
|
||||
|
||||
- Transitions -
|
||||
I GETX [1730 ] 1730
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [1726 ] 1726
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [1730 ] 1730
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [1726 ] 1726
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,16 +4,31 @@ sim_seconds 0.000144 # Nu
|
|||
sim_ticks 143853 # Number of ticks simulated
|
||||
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31570 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31567 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 710572 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 153096 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_inst_rate 39172 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39167 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 881633 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 145628 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 3456 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1730 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1726 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 999 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 3037 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 11 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 3048 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.881944 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 1500 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1375 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 55 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 107 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 162 4.69% 4.69% | 36 1.04% 5.73% | 92 2.66% 8.39% | 110 3.18% 11.57% | 106 3.07% 14.64% | 362 10.47% 25.12% | 98 2.84% 27.95% | 36 1.04% 28.99% | 32 0.93% 29.92% | 34 0.98% 30.90% | 83 2.40% 33.30% | 92 2.66% 35.97% | 110 3.18% 39.15% | 104 3.01% 42.16% | 84 2.43% 44.59% | 86 2.49% 47.08% | 83 2.40% 49.48% | 53 1.53% 51.01% | 50 1.45% 52.46% | 58 1.68% 54.14% | 64 1.85% 55.99% | 124 3.59% 59.58% | 212 6.13% 65.71% | 72 2.08% 67.80% | 66 1.91% 69.70% | 50 1.45% 71.15% | 122 3.53% 74.68% | 190 5.50% 80.18% | 220 6.37% 86.55% | 325 9.40% 95.95% | 42 1.22% 97.16% | 98 2.84% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 3456 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -69,5 +84,29 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 143853 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 1183 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 865 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data 1730 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Replacement 1726 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 1726 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 727 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 730 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 273 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 456 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 5670 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 592 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement 1726 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 1726 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data 1457 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data 273 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 1730 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 1726 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1730 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 1726 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 1730 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 1726 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 1730 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 1726 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Mar/06/2013 20:38:34
|
||||
Real time: Jun/08/2013 14:12:43
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.54
|
||||
Virtual_time_in_minutes: 0.009
|
||||
Virtual_time_in_hours: 0.00015
|
||||
Virtual_time_in_days: 6.25e-06
|
||||
Virtual_time_in_seconds: 0.48
|
||||
Virtual_time_in_minutes: 0.008
|
||||
Virtual_time_in_hours: 0.000133333
|
||||
Virtual_time_in_days: 5.55556e-06
|
||||
|
||||
Ruby_current_time: 52575
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 52575
|
||||
|
||||
mbytes_resident: 53.8125
|
||||
mbytes_total: 145.805
|
||||
resident_ratio: 0.369126
|
||||
|
||||
ruby_cycles_executed: [ 52576 ]
|
||||
mbytes_resident: 54.0742
|
||||
mbytes_total: 141.93
|
||||
resident_ratio: 0.381048
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -61,7 +59,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -82,7 +79,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11068
|
||||
page_reclaims: 11040
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 4.8648
|
|||
outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [415 ] 415
|
||||
Ifetch [2585 ] 2585
|
||||
Store [294 ] 294
|
||||
Inv [431 ] 431
|
||||
L1_Replacement [502 ] 502
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [204 ] 204
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [368 ] 368
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [124 ] 124
|
||||
PF_Load [0 ] 0
|
||||
PF_Ifetch [0 ] 0
|
||||
PF_Store [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [182 ] 182
|
||||
NP Ifetch [270 ] 270
|
||||
NP Store [58 ] 58
|
||||
NP Inv [162 ] 162
|
||||
NP L1_Replacement [0 ] 0
|
||||
NP PF_Load [0 ] 0
|
||||
NP PF_Ifetch [0 ] 0
|
||||
NP PF_Store [0 ] 0
|
||||
|
||||
I Load [22 ] 22
|
||||
I Ifetch [30 ] 30
|
||||
I Store [10 ] 10
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [206 ] 206
|
||||
I PF_Load [0 ] 0
|
||||
I PF_Ifetch [0 ] 0
|
||||
I PF_Store [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [2285 ] 2285
|
||||
S Store [0 ] 0
|
||||
S Inv [124 ] 124
|
||||
S L1_Replacement [172 ] 172
|
||||
S PF_Load [0 ] 0
|
||||
S PF_Store [0 ] 0
|
||||
|
||||
E Load [140 ] 140
|
||||
E Ifetch [0 ] 0
|
||||
E Store [41 ] 41
|
||||
E Inv [83 ] 83
|
||||
E L1_Replacement [79 ] 79
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
E PF_Load [0 ] 0
|
||||
E PF_Store [0 ] 0
|
||||
|
||||
M Load [71 ] 71
|
||||
M Ifetch [0 ] 0
|
||||
M Store [185 ] 185
|
||||
M Inv [62 ] 62
|
||||
M L1_Replacement [45 ] 45
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
M PF_Load [0 ] 0
|
||||
M PF_Store [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Exclusive [204 ] 204
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [300 ] 300
|
||||
IS PF_Load [0 ] 0
|
||||
IS PF_Store [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [68 ] 68
|
||||
IM Ack [0 ] 0
|
||||
IM PF_Load [0 ] 0
|
||||
IM PF_Store [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [0 ] 0
|
||||
SM PF_Load [0 ] 0
|
||||
SM PF_Store [0 ] 0
|
||||
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
IS_I Store [0 ] 0
|
||||
IS_I Inv [0 ] 0
|
||||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [0 ] 0
|
||||
IS_I PF_Load [0 ] 0
|
||||
IS_I PF_Store [0 ] 0
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [0 ] 0
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [0 ] 0
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [124 ] 124
|
||||
M_I PF_Load [0 ] 0
|
||||
M_I PF_Store [0 ] 0
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 ] 0
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 ] 0
|
||||
SINK_WB_ACK PF_Load [0 ] 0
|
||||
SINK_WB_ACK PF_Store [0 ] 0
|
||||
|
||||
PF_IS Load [0 ] 0
|
||||
PF_IS Ifetch [0 ] 0
|
||||
PF_IS Store [0 ] 0
|
||||
PF_IS Inv [0 ] 0
|
||||
PF_IS L1_Replacement [0 ] 0
|
||||
PF_IS Data_Exclusive [0 ] 0
|
||||
PF_IS DataS_fromL1 [0 ] 0
|
||||
PF_IS Data_all_Acks [0 ] 0
|
||||
PF_IS PF_Load [0 ] 0
|
||||
PF_IS PF_Store [0 ] 0
|
||||
|
||||
PF_IM Load [0 ] 0
|
||||
PF_IM Ifetch [0 ] 0
|
||||
PF_IM Store [0 ] 0
|
||||
PF_IM Inv [0 ] 0
|
||||
PF_IM L1_Replacement [0 ] 0
|
||||
PF_IM Data [0 ] 0
|
||||
PF_IM Data_all_Acks [0 ] 0
|
||||
PF_IM Ack [0 ] 0
|
||||
PF_IM PF_Load [0 ] 0
|
||||
PF_IM PF_Store [0 ] 0
|
||||
|
||||
PF_SM Load [0 ] 0
|
||||
PF_SM Ifetch [0 ] 0
|
||||
PF_SM Store [0 ] 0
|
||||
PF_SM Inv [0 ] 0
|
||||
PF_SM L1_Replacement [0 ] 0
|
||||
PF_SM Ack [0 ] 0
|
||||
PF_SM Ack_all [0 ] 0
|
||||
|
||||
PF_IS_I Load [0 ] 0
|
||||
PF_IS_I Store [0 ] 0
|
||||
PF_IS_I Inv [0 ] 0
|
||||
PF_IS_I L1_Replacement [0 ] 0
|
||||
PF_IS_I Data_Exclusive [0 ] 0
|
||||
PF_IS_I DataS_fromL1 [0 ] 0
|
||||
PF_IS_I Data_all_Acks [0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [300 ] 300
|
||||
L1_GETS [204 ] 204
|
||||
L1_GETX [68 ] 68
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [124 ] 124
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [43 ] 43
|
||||
L2_Replacement_clean [496 ] 496
|
||||
Mem_Data [547 ] 547
|
||||
Mem_Ack [539 ] 539
|
||||
WB_Data [62 ] 62
|
||||
WB_Data_clean [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_all [369 ] 369
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [272 ] 272
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [291 ] 291
|
||||
NP L1_GETS [192 ] 192
|
||||
NP L1_GETX [64 ] 64
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [9 ] 9
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [0 ] 0
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [286 ] 286
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [12 ] 12
|
||||
M L1_GETX [4 ] 4
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [39 ] 39
|
||||
M L2_Replacement_clean [69 ] 69
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [124 ] 124
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [4 ] 4
|
||||
MT L2_Replacement_clean [141 ] 141
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [539 ] 539
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [2 ] 2
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [2 ] 2
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [60 ] 60
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [81 ] 81
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [286 ] 286
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [192 ] 192
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [291 ] 291
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [64 ] 64
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [0 ] 0
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [272 ] 272
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [0 ] 0
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [0 ] 0
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [0 ] 0
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 650
|
||||
memory_reads: 547
|
||||
memory_writes: 103
|
||||
memory_refreshes: 365
|
||||
memory_total_request_delays: 117
|
||||
memory_delays_per_request: 0.18
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 117
|
||||
memory_stalls_for_bank_busy: 63
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 8
|
||||
memory_stalls_for_bus: 46
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 0
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [547 ] 547
|
||||
Data [103 ] 103
|
||||
Memory_Data [547 ] 547
|
||||
Memory_Ack [103 ] 103
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [436 ] 436
|
||||
|
||||
- Transitions -
|
||||
I Fetch [547 ] 547
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [103 ] 103
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [436 ] 436
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [547 ] 547
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [103 ] 103
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu
|
|||
sim_ticks 52575 # Number of ticks simulated
|
||||
final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 12497 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12496 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 254920 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 152164 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_inst_rate 18867 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 18864 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 384805 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 145340 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
|
||||
|
|
@ -29,6 +29,19 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 117 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 117 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.180000 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 63 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 46 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -84,5 +97,79 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 52575 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 124 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement_clean 496 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Data 547 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Ack 539 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data 62 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack_all 369 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 272 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GET_INSTR 291 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 192 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 64 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GET_INSTR 9 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement_clean 286 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 12 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 39 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement_clean 69 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_PUTX 124 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement_clean 141 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.Mem_Ack 539 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.WB_Data 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data 60 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.Ack_all 81 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack_all 286 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.Mem_Data 192 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.Mem_Data 291 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.Mem_Data 64 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 272 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Inv 431 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 502 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Exclusive 204 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_all_Acks 368 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.WB_Ack 124 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Inv 162 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 22 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 30 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 10 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement 206 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch 2285 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Inv 124 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement 172 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Load 140 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Store 41 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Inv 83 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement 79 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 71 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 185 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Inv 62 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 45 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Fetch 547 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data 103 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 547 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 103 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.CleanReplacement 436 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Fetch 547 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.Data 103 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.CleanReplacement 436 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 547 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 103 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu
|
|||
sim_ticks 44968 # Number of ticks simulated
|
||||
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 13243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 13241 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 231036 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 152316 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_inst_rate 16391 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 16389 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 285944 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 146540 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 87 # Number of cache demand hits
|
||||
|
|
@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 499 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 423 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 76 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 313 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 77 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 77 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.154309 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 41 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 25 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 9 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.61% 3.61% | 10 2.00% 5.61% | 0 0.00% 5.61% | 34 6.81% 12.42% | 20 4.01% 16.43% | 19 3.81% 20.24% | 28 5.61% 25.85% | 21 4.21% 30.06% | 5 1.00% 31.06% | 3 0.60% 31.66% | 6 1.20% 32.87% | 4 0.80% 33.67% | 21 4.21% 37.88% | 40 8.02% 45.89% | 20 4.01% 49.90% | 3 0.60% 50.50% | 4 0.80% 51.30% | 5 1.00% 52.30% | 7 1.40% 53.71% | 13 2.61% 56.31% | 10 2.00% 58.32% | 16 3.21% 61.52% | 14 2.81% 64.33% | 41 8.22% 72.55% | 15 3.01% 75.55% | 5 1.00% 76.55% | 5 1.00% 77.56% | 12 2.40% 79.96% | 12 2.40% 82.36% | 18 3.61% 85.97% | 14 2.81% 88.78% | 56 11.22% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 499 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -75,5 +89,82 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 44968 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l2_cntrl0.L1_GETS 454 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 58 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 502 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.All_Acks 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data_Exclusive 380 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBCLEANDATA 396 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBDIRTYDATA 106 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Ack 407 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 510 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 407 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 380 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_PUTX 502 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 72 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 15 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 407 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 396 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 106 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Data_Exclusive 380 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 380 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGM.Data 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.All_Acks 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 43 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.Exclusive_Unblock 15 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.Exclusive_Unblock 72 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.L1_GETS 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.Writeback_Ack 407 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 506 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data 510 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack_Data 502 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.All_acks 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Use_Timeout 509 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 182 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 270 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 82 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 1220 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 33 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 406 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Load 49 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Ifetch 1095 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Store 7 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement 4 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_Timeout 444 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 99 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 114 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement 96 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Load 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 82 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_Timeout 65 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.All_acks 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data 452 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 502 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 43 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 380 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 407 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Exclusive_Unblock 422 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Clean_Writeback 331 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Dirty_Writeback 76 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 423 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 76 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 43 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETS 380 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Memory_Ack 74 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 407 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Exclusive_Unblock 379 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Data 380 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Ack 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Exclusive_Unblock 43 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Memory_Data 43 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Clean_Writeback 331 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Dirty_Writeback 76 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Mar/06/2013 20:46:06
|
||||
Real time: Jun/08/2013 14:14:46
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.55
|
||||
Virtual_time_in_minutes: 0.00916667
|
||||
Virtual_time_in_hours: 0.000152778
|
||||
Virtual_time_in_days: 6.36574e-06
|
||||
Virtual_time_in_seconds: 0.47
|
||||
Virtual_time_in_minutes: 0.00783333
|
||||
Virtual_time_in_hours: 0.000130556
|
||||
Virtual_time_in_days: 5.43981e-06
|
||||
|
||||
Ruby_current_time: 43073
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 43073
|
||||
|
||||
mbytes_resident: 53.1133
|
||||
mbytes_total: 144.906
|
||||
resident_ratio: 0.366562
|
||||
|
||||
ruby_cycles_executed: [ 43074 ]
|
||||
mbytes_resident: 53.543
|
||||
mbytes_total: 140.984
|
||||
resident_ratio: 0.379835
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -69,7 +67,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -90,7 +87,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11916
|
||||
page_reclaims: 10919
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -160,805 +157,3 @@ links_utilized_percent_switch_3: 4.36236
|
|||
outgoing_messages_switch_3_link_2_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 365 2920 [ 0 0 0 0 365 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [415 ] 415
|
||||
Ifetch [2585 ] 2585
|
||||
Store [294 ] 294
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [504 ] 504
|
||||
Data_Shared [56 ] 56
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [462 ] 462
|
||||
Ack [1 ] 1
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_Local_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
Transient_Local_GETS_Last_Token [0 ] 0
|
||||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Request_Timeout [0 ] 0
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [461 ] 461
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [182 ] 182
|
||||
NP Ifetch [270 ] 270
|
||||
NP Store [58 ] 58
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [0 ] 0
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Transient_Local_GETS [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Atomic [0 ] 0
|
||||
I L1_Replacement [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_Local_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_Local_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I Transient_Local_GETS_Last_Token [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [29 ] 29
|
||||
S Ifetch [158 ] 158
|
||||
S Store [8 ] 8
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [48 ] 48
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_Local_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_Local_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S Transient_Local_GETS_Last_Token [0 ] 0
|
||||
S Persistent_GETX [0 ] 0
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O Atomic [0 ] 0
|
||||
O L1_Replacement [0 ] 0
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_Local_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_Local_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O Transient_Local_GETS_Last_Token [0 ] 0
|
||||
O Persistent_GETX [0 ] 0
|
||||
O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M Load [66 ] 66
|
||||
M Ifetch [1161 ] 1161
|
||||
M Store [29 ] 29
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [358 ] 358
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
MM Load [96 ] 96
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [104 ] 104
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [96 ] 96
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M_W Load [36 ] 36
|
||||
M_W Ifetch [996 ] 996
|
||||
M_W Store [3 ] 3
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [1 ] 1
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
M_W Transient_Local_GETS [0 ] 0
|
||||
M_W Persistent_GETX [0 ] 0
|
||||
M_W Persistent_GETS [0 ] 0
|
||||
M_W Own_Lock_or_Unlock [0 ] 0
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [392 ] 392
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [6 ] 6
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [92 ] 92
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [1 ] 1
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [0 ] 0
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [69 ] 69
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [58 ] 58
|
||||
IM Ack [1 ] 1
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
IM Transient_Local_GETS [0 ] 0
|
||||
IM Transient_GETS_Last_Token [0 ] 0
|
||||
IM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [0 ] 0
|
||||
IM Request_Timeout [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Atomic [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [8 ] 8
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
SM Transient_GETS [0 ] 0
|
||||
SM Transient_Local_GETS [0 ] 0
|
||||
SM Transient_GETS_Last_Token [0 ] 0
|
||||
SM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
SM Persistent_GETX [0 ] 0
|
||||
SM Persistent_GETS [0 ] 0
|
||||
SM Persistent_GETS_Last_Token [0 ] 0
|
||||
SM Own_Lock_or_Unlock [0 ] 0
|
||||
SM Request_Timeout [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM Atomic [0 ] 0
|
||||
OM L1_Replacement [0 ] 0
|
||||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [0 ] 0
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
OM Transient_Local_GETS [0 ] 0
|
||||
OM Transient_GETS_Last_Token [0 ] 0
|
||||
OM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [0 ] 0
|
||||
OM Request_Timeout [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Shared [56 ] 56
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [396 ] 396
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
IS Transient_GETS [0 ] 0
|
||||
IS Transient_Local_GETS [0 ] 0
|
||||
IS Transient_GETS_Last_Token [0 ] 0
|
||||
IS Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [0 ] 0
|
||||
IS Request_Timeout [0 ] 0
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
I_L Store [0 ] 0
|
||||
I_L Atomic [0 ] 0
|
||||
I_L L1_Replacement [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_Local_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_Local_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
I_L Persistent_GETX [0 ] 0
|
||||
I_L Persistent_GETS [0 ] 0
|
||||
I_L Persistent_GETS_Last_Token [0 ] 0
|
||||
I_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S_L Load [0 ] 0
|
||||
S_L Ifetch [0 ] 0
|
||||
S_L Store [0 ] 0
|
||||
S_L Atomic [0 ] 0
|
||||
S_L L1_Replacement [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_Local_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_Local_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
IM_L Load [0 ] 0
|
||||
IM_L Ifetch [0 ] 0
|
||||
IM_L Store [0 ] 0
|
||||
IM_L Atomic [0 ] 0
|
||||
IM_L L1_Replacement [0 ] 0
|
||||
IM_L Data_Shared [0 ] 0
|
||||
IM_L Data_Owner [0 ] 0
|
||||
IM_L Data_All_Tokens [0 ] 0
|
||||
IM_L Ack [0 ] 0
|
||||
IM_L Transient_GETX [0 ] 0
|
||||
IM_L Transient_Local_GETX [0 ] 0
|
||||
IM_L Transient_GETS [0 ] 0
|
||||
IM_L Transient_Local_GETS [0 ] 0
|
||||
IM_L Transient_GETS_Last_Token [0 ] 0
|
||||
IM_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM_L Persistent_GETX [0 ] 0
|
||||
IM_L Persistent_GETS [0 ] 0
|
||||
IM_L Own_Lock_or_Unlock [0 ] 0
|
||||
IM_L Request_Timeout [0 ] 0
|
||||
|
||||
SM_L Load [0 ] 0
|
||||
SM_L Ifetch [0 ] 0
|
||||
SM_L Store [0 ] 0
|
||||
SM_L Atomic [0 ] 0
|
||||
SM_L L1_Replacement [0 ] 0
|
||||
SM_L Data_Shared [0 ] 0
|
||||
SM_L Data_Owner [0 ] 0
|
||||
SM_L Data_All_Tokens [0 ] 0
|
||||
SM_L Ack [0 ] 0
|
||||
SM_L Transient_GETX [0 ] 0
|
||||
SM_L Transient_Local_GETX [0 ] 0
|
||||
SM_L Transient_GETS [0 ] 0
|
||||
SM_L Transient_Local_GETS [0 ] 0
|
||||
SM_L Transient_GETS_Last_Token [0 ] 0
|
||||
SM_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
SM_L Persistent_GETX [0 ] 0
|
||||
SM_L Persistent_GETS [0 ] 0
|
||||
SM_L Persistent_GETS_Last_Token [0 ] 0
|
||||
SM_L Own_Lock_or_Unlock [0 ] 0
|
||||
SM_L Request_Timeout [0 ] 0
|
||||
|
||||
IS_L Load [0 ] 0
|
||||
IS_L Ifetch [0 ] 0
|
||||
IS_L Store [0 ] 0
|
||||
IS_L Atomic [0 ] 0
|
||||
IS_L L1_Replacement [0 ] 0
|
||||
IS_L Data_Shared [0 ] 0
|
||||
IS_L Data_Owner [0 ] 0
|
||||
IS_L Data_All_Tokens [0 ] 0
|
||||
IS_L Ack [0 ] 0
|
||||
IS_L Transient_GETX [0 ] 0
|
||||
IS_L Transient_Local_GETX [0 ] 0
|
||||
IS_L Transient_GETS [0 ] 0
|
||||
IS_L Transient_Local_GETS [0 ] 0
|
||||
IS_L Transient_GETS_Last_Token [0 ] 0
|
||||
IS_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS_L Persistent_GETX [0 ] 0
|
||||
IS_L Persistent_GETS [0 ] 0
|
||||
IS_L Own_Lock_or_Unlock [0 ] 0
|
||||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [448 ] 448
|
||||
L1_GETS_Last_Token [4 ] 4
|
||||
L1_GETX [66 ] 66
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [458 ] 458
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [21 ] 21
|
||||
Writeback_All_Tokens [481 ] 481
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [396 ] 396
|
||||
NP L1_GETX [50 ] 50
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [18 ] 18
|
||||
NP Writeback_All_Tokens [448 ] 448
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [0 ] 0
|
||||
NP Ack [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [1 ] 1
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [9 ] 9
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [3 ] 3
|
||||
I Writeback_All_Tokens [6 ] 6
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [4 ] 4
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [15 ] 15
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
S Writeback_Owned [0 ] 0
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Persistent_GETX [0 ] 0
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [6 ] 6
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [19 ] 19
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [27 ] 27
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Persistent_GETX [0 ] 0
|
||||
O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [52 ] 52
|
||||
M L1_GETX [8 ] 8
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [415 ] 415
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
I_L L1_GETX [0 ] 0
|
||||
I_L L1_INV [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [0 ] 0
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [0 ] 0
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [0 ] 0
|
||||
I_L Persistent_GETS [0 ] 0
|
||||
I_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
S_L L1_GETX [0 ] 0
|
||||
S_L L1_INV [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L L2_Replacement [0 ] 0
|
||||
S_L Writeback_Tokens [0 ] 0
|
||||
S_L Writeback_Shared_Data [0 ] 0
|
||||
S_L Writeback_All_Tokens [0 ] 0
|
||||
S_L Writeback_Owned [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 532
|
||||
memory_reads: 448
|
||||
memory_writes: 84
|
||||
memory_refreshes: 299
|
||||
memory_total_request_delays: 150
|
||||
memory_delays_per_request: 0.281955
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 150
|
||||
memory_stalls_for_bank_busy: 38
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 16
|
||||
memory_stalls_for_bus: 90
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 6
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 19 10 0 39 20 19 31 22 5 3 6 4 22 41 22 3 4 6 7 13 10 18 14 42 16 5 5 12 13 18 14 69
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [70 ] 70
|
||||
GETS [405 ] 405
|
||||
Lockdown [0 ] 0
|
||||
Unlockdown [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [3 ] 3
|
||||
Data_All_Tokens [81 ] 81
|
||||
Ack_Owner [16 ] 16
|
||||
Ack_Owner_All_Tokens [334 ] 334
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [15 ] 15
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [448 ] 448
|
||||
Memory_Ack [84 ] 84
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [52 ] 52
|
||||
O GETS [396 ] 396
|
||||
O Lockdown [0 ] 0
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [15 ] 15
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [6 ] 6
|
||||
NO GETS [0 ] 0
|
||||
NO Lockdown [0 ] 0
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [3 ] 3
|
||||
NO Data_All_Tokens [81 ] 81
|
||||
NO Ack_Owner [16 ] 16
|
||||
NO Ack_Owner_All_Tokens [334 ] 334
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [0 ] 0
|
||||
L GETS [0 ] 0
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [0 ] 0
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [0 ] 0
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [0 ] 0
|
||||
L Tokens [0 ] 0
|
||||
L DMA_READ [0 ] 0
|
||||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [12 ] 12
|
||||
O_W GETS [9 ] 9
|
||||
O_W Lockdown [0 ] 0
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_W Data_Owner [0 ] 0
|
||||
O_W Data_All_Tokens [0 ] 0
|
||||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [84 ] 84
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [0 ] 0
|
||||
L_O_W GETS [0 ] 0
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
L_O_W Data_All_Tokens [0 ] 0
|
||||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [0 ] 0
|
||||
L_O_W Memory_Ack [0 ] 0
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_NO_W GETX [0 ] 0
|
||||
L_NO_W GETS [0 ] 0
|
||||
L_NO_W Lockdown [0 ] 0
|
||||
L_NO_W Unlockdown [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_NO_W Data_Owner [0 ] 0
|
||||
L_NO_W Data_All_Tokens [0 ] 0
|
||||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [0 ] 0
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L_W GETX [0 ] 0
|
||||
DR_L_W GETS [0 ] 0
|
||||
DR_L_W Lockdown [0 ] 0
|
||||
DR_L_W Unlockdown [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L_W Data_Owner [0 ] 0
|
||||
DR_L_W Data_All_Tokens [0 ] 0
|
||||
DR_L_W Ack_Owner [0 ] 0
|
||||
DR_L_W Tokens [0 ] 0
|
||||
DR_L_W Ack_All_Tokens [0 ] 0
|
||||
DR_L_W Request_Timeout [0 ] 0
|
||||
DR_L_W Memory_Data [0 ] 0
|
||||
DR_L_W DMA_READ [0 ] 0
|
||||
DR_L_W DMA_WRITE [0 ] 0
|
||||
DR_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L_W GETX [0 ] 0
|
||||
DW_L_W GETS [0 ] 0
|
||||
DW_L_W Lockdown [0 ] 0
|
||||
DW_L_W Unlockdown [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L_W Data_Owner [0 ] 0
|
||||
DW_L_W Data_All_Tokens [0 ] 0
|
||||
DW_L_W Ack_Owner [0 ] 0
|
||||
DW_L_W Tokens [0 ] 0
|
||||
DW_L_W Ack_All_Tokens [0 ] 0
|
||||
DW_L_W Request_Timeout [0 ] 0
|
||||
DW_L_W Memory_Ack [0 ] 0
|
||||
DW_L_W DMA_READ [0 ] 0
|
||||
DW_L_W DMA_WRITE [0 ] 0
|
||||
DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [0 ] 0
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_W Data_Owner [0 ] 0
|
||||
NO_W Data_All_Tokens [0 ] 0
|
||||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [448 ] 448
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW_W GETX [0 ] 0
|
||||
O_DW_W GETS [0 ] 0
|
||||
O_DW_W Lockdown [0 ] 0
|
||||
O_DW_W Unlockdown [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW_W Data_Owner [0 ] 0
|
||||
O_DW_W Data_All_Tokens [0 ] 0
|
||||
O_DW_W Ack_Owner [0 ] 0
|
||||
O_DW_W Tokens [0 ] 0
|
||||
O_DW_W Ack_All_Tokens [0 ] 0
|
||||
O_DW_W Request_Timeout [0 ] 0
|
||||
O_DW_W Memory_Ack [0 ] 0
|
||||
O_DW_W DMA_READ [0 ] 0
|
||||
O_DW_W DMA_WRITE [0 ] 0
|
||||
O_DW_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DR_W GETX [0 ] 0
|
||||
O_DR_W GETS [0 ] 0
|
||||
O_DR_W Lockdown [0 ] 0
|
||||
O_DR_W Unlockdown [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DR_W Data_Owner [0 ] 0
|
||||
O_DR_W Data_All_Tokens [0 ] 0
|
||||
O_DR_W Ack_Owner [0 ] 0
|
||||
O_DR_W Tokens [0 ] 0
|
||||
O_DR_W Ack_All_Tokens [0 ] 0
|
||||
O_DR_W Request_Timeout [0 ] 0
|
||||
O_DR_W Memory_Data [0 ] 0
|
||||
O_DR_W DMA_READ [0 ] 0
|
||||
O_DR_W DMA_WRITE [0 ] 0
|
||||
O_DR_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW GETX [0 ] 0
|
||||
O_DW GETS [0 ] 0
|
||||
O_DW Lockdown [0 ] 0
|
||||
O_DW Unlockdown [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW Data_Owner [0 ] 0
|
||||
O_DW Data_All_Tokens [0 ] 0
|
||||
O_DW Ack_Owner [0 ] 0
|
||||
O_DW Ack_Owner_All_Tokens [0 ] 0
|
||||
O_DW Tokens [0 ] 0
|
||||
O_DW Ack_All_Tokens [0 ] 0
|
||||
O_DW Request_Timeout [0 ] 0
|
||||
O_DW DMA_READ [0 ] 0
|
||||
O_DW DMA_WRITE [0 ] 0
|
||||
O_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DW GETX [0 ] 0
|
||||
NO_DW GETS [0 ] 0
|
||||
NO_DW Lockdown [0 ] 0
|
||||
NO_DW Unlockdown [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DW Data_Owner [0 ] 0
|
||||
NO_DW Data_All_Tokens [0 ] 0
|
||||
NO_DW Tokens [0 ] 0
|
||||
NO_DW Request_Timeout [0 ] 0
|
||||
NO_DW DMA_READ [0 ] 0
|
||||
NO_DW DMA_WRITE [0 ] 0
|
||||
NO_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DR GETX [0 ] 0
|
||||
NO_DR GETS [0 ] 0
|
||||
NO_DR Lockdown [0 ] 0
|
||||
NO_DR Unlockdown [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DR Data_Owner [0 ] 0
|
||||
NO_DR Data_All_Tokens [0 ] 0
|
||||
NO_DR Tokens [0 ] 0
|
||||
NO_DR Request_Timeout [0 ] 0
|
||||
NO_DR DMA_READ [0 ] 0
|
||||
NO_DR DMA_WRITE [0 ] 0
|
||||
NO_DR DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L GETX [0 ] 0
|
||||
DW_L GETS [0 ] 0
|
||||
DW_L Lockdown [0 ] 0
|
||||
DW_L Unlockdown [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L Data_Owner [0 ] 0
|
||||
DW_L Data_All_Tokens [0 ] 0
|
||||
DW_L Ack_Owner [0 ] 0
|
||||
DW_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DW_L Tokens [0 ] 0
|
||||
DW_L Request_Timeout [0 ] 0
|
||||
DW_L DMA_READ [0 ] 0
|
||||
DW_L DMA_WRITE [0 ] 0
|
||||
DW_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L GETX [0 ] 0
|
||||
DR_L GETS [0 ] 0
|
||||
DR_L Lockdown [0 ] 0
|
||||
DR_L Unlockdown [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L Data_Owner [0 ] 0
|
||||
DR_L Data_All_Tokens [0 ] 0
|
||||
DR_L Ack_Owner [0 ] 0
|
||||
DR_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DR_L Tokens [0 ] 0
|
||||
DR_L Request_Timeout [0 ] 0
|
||||
DR_L DMA_READ [0 ] 0
|
||||
DR_L DMA_WRITE [0 ] 0
|
||||
DR_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu
|
|||
sim_ticks 43073 # Number of ticks simulated
|
||||
final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 14561 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 14560 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 243330 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 151252 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_inst_rate 29444 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29437 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 491916 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 144372 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits
|
||||
|
|
@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 532 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 448 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 84 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 299 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 150 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 150 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.281955 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 38 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 90 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 6 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 16 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 19 3.57% 3.57% | 10 1.88% 5.45% | 0 0.00% 5.45% | 39 7.33% 12.78% | 20 3.76% 16.54% | 19 3.57% 20.11% | 31 5.83% 25.94% | 22 4.14% 30.08% | 5 0.94% 31.02% | 3 0.56% 31.58% | 6 1.13% 32.71% | 4 0.75% 33.46% | 22 4.14% 37.59% | 41 7.71% 45.30% | 22 4.14% 49.44% | 3 0.56% 50.00% | 4 0.75% 50.75% | 6 1.13% 51.88% | 7 1.32% 53.20% | 13 2.44% 55.64% | 10 1.88% 57.52% | 18 3.38% 60.90% | 14 2.63% 63.53% | 42 7.89% 71.43% | 16 3.01% 74.44% | 5 0.94% 75.38% | 5 0.94% 76.32% | 12 2.26% 78.57% | 13 2.44% 81.02% | 18 3.38% 84.40% | 14 2.63% 87.03% | 69 12.97% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 532 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -75,5 +89,85 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 43073 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l2_cntrl0.L1_GETS 448 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS_Last_Token 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 66 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 458 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Shared_Data 21 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_All_Tokens 481 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 396 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 50 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_Shared_Data 18 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 448 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L2_Replacement 9 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_Shared_Data 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_All_Tokens 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETS_Last_Token 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L2_Replacement 15 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L1_GETX 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L2_Replacement 19 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Writeback_All_Tokens 27 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 52 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 8 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 415 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 504 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Shared 56 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_All_Tokens 462 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ack 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Use_TimeoutNoStarvers 461 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Load 29 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch 158 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Store 8 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement 48 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 66 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 1161 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 29 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 358 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 96 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 104 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement 96 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Load 36 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Ifetch 996 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Store 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Load 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 92 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers 69 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_All_Tokens 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Ack 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.SM.Data_All_Tokens 8 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Shared 56 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_All_Tokens 396 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 70 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 405 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_Owner 3 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_All_Tokens 81 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner 16 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 334 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_All_Tokens 15 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 448 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 84 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETX 52 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETS 396 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Ack_All_Tokens 15 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETX 6 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_Owner 3 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_All_Tokens 81 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner 16 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 334 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.GETX 12 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.GETS 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Memory_Ack 84 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Memory_Data 448 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Mar/06/2013 20:34:50
|
||||
Real time: Jun/08/2013 13:28:07
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.51
|
||||
Virtual_time_in_minutes: 0.0085
|
||||
Virtual_time_in_hours: 0.000141667
|
||||
Virtual_time_in_days: 5.90278e-06
|
||||
Virtual_time_in_seconds: 0.5
|
||||
Virtual_time_in_minutes: 0.00833333
|
||||
Virtual_time_in_hours: 0.000138889
|
||||
Virtual_time_in_days: 5.78704e-06
|
||||
|
||||
Ruby_current_time: 35432
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 35432
|
||||
|
||||
mbytes_resident: 52.5391
|
||||
mbytes_total: 144.84
|
||||
resident_ratio: 0.362793
|
||||
|
||||
ruby_cycles_executed: [ 35433 ]
|
||||
mbytes_resident: 53.8984
|
||||
mbytes_total: 141.902
|
||||
resident_ratio: 0.379883
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -68,7 +66,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -89,11 +86,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10230
|
||||
page_faults: 0
|
||||
page_reclaims: 15042
|
||||
page_faults: 6
|
||||
swaps: 0
|
||||
block_inputs: 8
|
||||
block_outputs: 88
|
||||
block_inputs: 936
|
||||
block_outputs: 16712
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -144,749 +141,3 @@ links_utilized_percent_switch_2: 4.77887
|
|||
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [422 ] 422
|
||||
Ifetch [2591 ] 2591
|
||||
Store [298 ] 298
|
||||
L2_Replacement [425 ] 425
|
||||
L1_to_L2 [502 ] 502
|
||||
Trigger_L2_to_L1D [47 ] 47
|
||||
Trigger_L2_to_L1I [22 ] 22
|
||||
Complete_L2_to_L1 [69 ] 69
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [441 ] 441
|
||||
Writeback_Ack [425 ] 425
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [441 ] 441
|
||||
Flush_line [0 ] 0
|
||||
Block_Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [146 ] 146
|
||||
I Ifetch [248 ] 248
|
||||
I Store [47 ] 47
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
I Trigger_L2_to_L1I [0 ] 0
|
||||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S L2_Replacement [0 ] 0
|
||||
S L1_to_L2 [0 ] 0
|
||||
S Trigger_L2_to_L1D [0 ] 0
|
||||
S Trigger_L2_to_L1I [0 ] 0
|
||||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
S Flush_line [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O L2_Replacement [0 ] 0
|
||||
O L1_to_L2 [0 ] 0
|
||||
O Trigger_L2_to_L1D [0 ] 0
|
||||
O Trigger_L2_to_L1I [0 ] 0
|
||||
O Other_GETX [0 ] 0
|
||||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [109 ] 109
|
||||
M Ifetch [2315 ] 2315
|
||||
M Store [35 ] 35
|
||||
M L2_Replacement [344 ] 344
|
||||
M L1_to_L2 [397 ] 397
|
||||
M Trigger_L2_to_L1D [23 ] 23
|
||||
M Trigger_L2_to_L1I [22 ] 22
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [124 ] 124
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [201 ] 201
|
||||
MM L2_Replacement [81 ] 81
|
||||
MM L1_to_L2 [105 ] 105
|
||||
MM Trigger_L2_to_L1D [24 ] 24
|
||||
MM Trigger_L2_to_L1I [0 ] 0
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
MM Flush_line [0 ] 0
|
||||
|
||||
IR Load [0 ] 0
|
||||
IR Ifetch [0 ] 0
|
||||
IR Store [0 ] 0
|
||||
IR L1_to_L2 [0 ] 0
|
||||
IR Flush_line [0 ] 0
|
||||
|
||||
SR Load [0 ] 0
|
||||
SR Ifetch [0 ] 0
|
||||
SR Store [0 ] 0
|
||||
SR L1_to_L2 [0 ] 0
|
||||
SR Flush_line [0 ] 0
|
||||
|
||||
OR Load [0 ] 0
|
||||
OR Ifetch [0 ] 0
|
||||
OR Store [0 ] 0
|
||||
OR L1_to_L2 [0 ] 0
|
||||
OR Flush_line [0 ] 0
|
||||
|
||||
MR Load [22 ] 22
|
||||
MR Ifetch [22 ] 22
|
||||
MR Store [1 ] 1
|
||||
MR L1_to_L2 [0 ] 0
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [14 ] 14
|
||||
MMR Ifetch [0 ] 0
|
||||
MMR Store [10 ] 10
|
||||
MMR L1_to_L2 [0 ] 0
|
||||
MMR Flush_line [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [0 ] 0
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [47 ] 47
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM L2_Replacement [0 ] 0
|
||||
SM L1_to_L2 [0 ] 0
|
||||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
SM Flush_line [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM L2_Replacement [0 ] 0
|
||||
OM L1_to_L2 [0 ] 0
|
||||
OM Other_GETX [0 ] 0
|
||||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
OM All_acks_no_sharers [0 ] 0
|
||||
OM Flush_line [0 ] 0
|
||||
|
||||
ISM Load [0 ] 0
|
||||
ISM Ifetch [0 ] 0
|
||||
ISM Store [0 ] 0
|
||||
ISM L2_Replacement [0 ] 0
|
||||
ISM L1_to_L2 [0 ] 0
|
||||
ISM Ack [0 ] 0
|
||||
ISM All_acks_no_sharers [0 ] 0
|
||||
ISM Flush_line [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [0 ] 0
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [394 ] 394
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [0 ] 0
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [0 ] 0
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [47 ] 47
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [0 ] 0
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [394 ] 394
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
SS Store [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L1_to_L2 [0 ] 0
|
||||
SS Ack [0 ] 0
|
||||
SS Shared_Ack [0 ] 0
|
||||
SS All_acks [0 ] 0
|
||||
SS All_acks_no_sharers [0 ] 0
|
||||
SS Flush_line [0 ] 0
|
||||
|
||||
OI Load [0 ] 0
|
||||
OI Ifetch [0 ] 0
|
||||
OI Store [0 ] 0
|
||||
OI L2_Replacement [0 ] 0
|
||||
OI L1_to_L2 [0 ] 0
|
||||
OI Other_GETX [0 ] 0
|
||||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [7 ] 7
|
||||
MI Ifetch [6 ] 6
|
||||
MI Store [4 ] 4
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [425 ] 425
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
II Store [0 ] 0
|
||||
II L2_Replacement [0 ] 0
|
||||
II L1_to_L2 [0 ] 0
|
||||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
II Flush_line [0 ] 0
|
||||
|
||||
IT Load [0 ] 0
|
||||
IT Ifetch [0 ] 0
|
||||
IT Store [0 ] 0
|
||||
IT L2_Replacement [0 ] 0
|
||||
IT L1_to_L2 [0 ] 0
|
||||
IT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
ST Ifetch [0 ] 0
|
||||
ST Store [0 ] 0
|
||||
ST L2_Replacement [0 ] 0
|
||||
ST L1_to_L2 [0 ] 0
|
||||
ST Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
OT Ifetch [0 ] 0
|
||||
OT Store [0 ] 0
|
||||
OT L2_Replacement [0 ] 0
|
||||
OT L1_to_L2 [0 ] 0
|
||||
OT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [0 ] 0
|
||||
MT Complete_L2_to_L1 [45 ] 45
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [0 ] 0
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [0 ] 0
|
||||
MMT Complete_L2_to_L1 [24 ] 24
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [0 ] 0
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
MM_F Ifetch [0 ] 0
|
||||
MM_F Store [0 ] 0
|
||||
MM_F L1_to_L2 [0 ] 0
|
||||
MM_F Other_GETX [0 ] 0
|
||||
MM_F Other_GETS [0 ] 0
|
||||
MM_F Merged_GETS [0 ] 0
|
||||
MM_F Other_GETS_No_Mig [0 ] 0
|
||||
MM_F NC_DMA_GETS [0 ] 0
|
||||
MM_F Invalidate [0 ] 0
|
||||
MM_F Ack [0 ] 0
|
||||
MM_F All_acks [0 ] 0
|
||||
MM_F All_acks_no_sharers [0 ] 0
|
||||
MM_F Flush_line [0 ] 0
|
||||
MM_F Block_Ack [0 ] 0
|
||||
|
||||
IM_F Load [0 ] 0
|
||||
IM_F Ifetch [0 ] 0
|
||||
IM_F Store [0 ] 0
|
||||
IM_F L2_Replacement [0 ] 0
|
||||
IM_F L1_to_L2 [0 ] 0
|
||||
IM_F Other_GETX [0 ] 0
|
||||
IM_F Other_GETS [0 ] 0
|
||||
IM_F Other_GETS_No_Mig [0 ] 0
|
||||
IM_F NC_DMA_GETS [0 ] 0
|
||||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [0 ] 0
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
ISM_F Ifetch [0 ] 0
|
||||
ISM_F Store [0 ] 0
|
||||
ISM_F L2_Replacement [0 ] 0
|
||||
ISM_F L1_to_L2 [0 ] 0
|
||||
ISM_F Ack [0 ] 0
|
||||
ISM_F All_acks_no_sharers [0 ] 0
|
||||
ISM_F Flush_line [0 ] 0
|
||||
|
||||
SM_F Load [0 ] 0
|
||||
SM_F Ifetch [0 ] 0
|
||||
SM_F Store [0 ] 0
|
||||
SM_F L2_Replacement [0 ] 0
|
||||
SM_F L1_to_L2 [0 ] 0
|
||||
SM_F Other_GETX [0 ] 0
|
||||
SM_F Other_GETS [0 ] 0
|
||||
SM_F Other_GETS_No_Mig [0 ] 0
|
||||
SM_F NC_DMA_GETS [0 ] 0
|
||||
SM_F Invalidate [0 ] 0
|
||||
SM_F Ack [0 ] 0
|
||||
SM_F Data [0 ] 0
|
||||
SM_F Exclusive_Data [0 ] 0
|
||||
SM_F Flush_line [0 ] 0
|
||||
|
||||
OM_F Load [0 ] 0
|
||||
OM_F Ifetch [0 ] 0
|
||||
OM_F Store [0 ] 0
|
||||
OM_F L2_Replacement [0 ] 0
|
||||
OM_F L1_to_L2 [0 ] 0
|
||||
OM_F Other_GETX [0 ] 0
|
||||
OM_F Other_GETS [0 ] 0
|
||||
OM_F Merged_GETS [0 ] 0
|
||||
OM_F Other_GETS_No_Mig [0 ] 0
|
||||
OM_F NC_DMA_GETS [0 ] 0
|
||||
OM_F Invalidate [0 ] 0
|
||||
OM_F Ack [0 ] 0
|
||||
OM_F All_acks [0 ] 0
|
||||
OM_F All_acks_no_sharers [0 ] 0
|
||||
OM_F Flush_line [0 ] 0
|
||||
|
||||
MM_WF Load [0 ] 0
|
||||
MM_WF Ifetch [0 ] 0
|
||||
MM_WF Store [0 ] 0
|
||||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [0 ] 0
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 522
|
||||
memory_reads: 441
|
||||
memory_writes: 81
|
||||
memory_refreshes: 246
|
||||
memory_total_request_delays: 39
|
||||
memory_delays_per_request: 0.0747126
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 39
|
||||
memory_stalls_for_bank_busy: 15
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 5
|
||||
memory_stalls_for_bus: 15
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [51 ] 51
|
||||
GETS [410 ] 410
|
||||
PUT [425 ] 425
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [440 ] 440
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [344 ] 344
|
||||
Writeback_Exclusive_Dirty [81 ] 81
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [441 ] 441
|
||||
Memory_Ack [81 ] 81
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [0 ] 0
|
||||
All_acks_and_shared_data [0 ] 0
|
||||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [0 ] 0
|
||||
PUTF [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
NX GETS [0 ] 0
|
||||
NX PUT [0 ] 0
|
||||
NX Pf_Replacement [0 ] 0
|
||||
NX DMA_READ [0 ] 0
|
||||
NX DMA_WRITE [0 ] 0
|
||||
NX GETF [0 ] 0
|
||||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [425 ] 425
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [0 ] 0
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
S PUT [0 ] 0
|
||||
S Pf_Replacement [0 ] 0
|
||||
S DMA_READ [0 ] 0
|
||||
S DMA_WRITE [0 ] 0
|
||||
S GETF [0 ] 0
|
||||
|
||||
O GETX [0 ] 0
|
||||
O GETS [0 ] 0
|
||||
O PUT [0 ] 0
|
||||
O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [47 ] 47
|
||||
E GETS [394 ] 394
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [0 ] 0
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
O_R PUT [0 ] 0
|
||||
O_R Pf_Replacement [0 ] 0
|
||||
O_R DMA_READ [0 ] 0
|
||||
O_R DMA_WRITE [0 ] 0
|
||||
O_R Ack [0 ] 0
|
||||
O_R All_acks_and_data_no_sharers [0 ] 0
|
||||
O_R GETF [0 ] 0
|
||||
|
||||
S_R GETX [0 ] 0
|
||||
S_R GETS [0 ] 0
|
||||
S_R PUT [0 ] 0
|
||||
S_R Pf_Replacement [0 ] 0
|
||||
S_R DMA_READ [0 ] 0
|
||||
S_R DMA_WRITE [0 ] 0
|
||||
S_R Ack [0 ] 0
|
||||
S_R Data [0 ] 0
|
||||
S_R All_acks_and_data_no_sharers [0 ] 0
|
||||
S_R GETF [0 ] 0
|
||||
|
||||
NO_R GETX [0 ] 0
|
||||
NO_R GETS [0 ] 0
|
||||
NO_R PUT [0 ] 0
|
||||
NO_R Pf_Replacement [0 ] 0
|
||||
NO_R DMA_READ [0 ] 0
|
||||
NO_R DMA_WRITE [0 ] 0
|
||||
NO_R Ack [0 ] 0
|
||||
NO_R Data [0 ] 0
|
||||
NO_R Exclusive_Data [0 ] 0
|
||||
NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_R GETF [0 ] 0
|
||||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [0 ] 0
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [440 ] 440
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
NO_B GETF [0 ] 0
|
||||
|
||||
NO_B_X GETX [0 ] 0
|
||||
NO_B_X GETS [0 ] 0
|
||||
NO_B_X PUT [0 ] 0
|
||||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
NO_B_X GETF [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
NO_B_S PUT [0 ] 0
|
||||
NO_B_S UnblockS [0 ] 0
|
||||
NO_B_S UnblockM [0 ] 0
|
||||
NO_B_S Pf_Replacement [0 ] 0
|
||||
NO_B_S DMA_READ [0 ] 0
|
||||
NO_B_S DMA_WRITE [0 ] 0
|
||||
NO_B_S GETF [0 ] 0
|
||||
|
||||
NO_B_S_W GETX [0 ] 0
|
||||
NO_B_S_W GETS [0 ] 0
|
||||
NO_B_S_W PUT [0 ] 0
|
||||
NO_B_S_W UnblockS [0 ] 0
|
||||
NO_B_S_W Pf_Replacement [0 ] 0
|
||||
NO_B_S_W DMA_READ [0 ] 0
|
||||
NO_B_S_W DMA_WRITE [0 ] 0
|
||||
NO_B_S_W All_Unblocks [0 ] 0
|
||||
NO_B_S_W GETF [0 ] 0
|
||||
|
||||
O_B GETX [0 ] 0
|
||||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
O_B GETF [0 ] 0
|
||||
|
||||
NO_B_W GETX [0 ] 0
|
||||
NO_B_W GETS [0 ] 0
|
||||
NO_B_W PUT [0 ] 0
|
||||
NO_B_W UnblockS [0 ] 0
|
||||
NO_B_W UnblockM [0 ] 0
|
||||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [441 ] 441
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
O_B_W PUT [0 ] 0
|
||||
O_B_W UnblockS [0 ] 0
|
||||
O_B_W Pf_Replacement [0 ] 0
|
||||
O_B_W DMA_READ [0 ] 0
|
||||
O_B_W DMA_WRITE [0 ] 0
|
||||
O_B_W Memory_Data [0 ] 0
|
||||
O_B_W GETF [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W PUT [0 ] 0
|
||||
NO_W Pf_Replacement [0 ] 0
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W Memory_Data [0 ] 0
|
||||
NO_W GETF [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W PUT [0 ] 0
|
||||
O_W Pf_Replacement [0 ] 0
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W GETF [0 ] 0
|
||||
|
||||
NO_DW_B_W GETX [0 ] 0
|
||||
NO_DW_B_W GETS [0 ] 0
|
||||
NO_DW_B_W PUT [0 ] 0
|
||||
NO_DW_B_W Pf_Replacement [0 ] 0
|
||||
NO_DW_B_W DMA_READ [0 ] 0
|
||||
NO_DW_B_W DMA_WRITE [0 ] 0
|
||||
NO_DW_B_W Ack [0 ] 0
|
||||
NO_DW_B_W Data [0 ] 0
|
||||
NO_DW_B_W Exclusive_Data [0 ] 0
|
||||
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DW_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_W GETX [0 ] 0
|
||||
NO_DR_B_W GETS [0 ] 0
|
||||
NO_DR_B_W PUT [0 ] 0
|
||||
NO_DR_B_W Pf_Replacement [0 ] 0
|
||||
NO_DR_B_W DMA_READ [0 ] 0
|
||||
NO_DR_B_W DMA_WRITE [0 ] 0
|
||||
NO_DR_B_W Memory_Data [0 ] 0
|
||||
NO_DR_B_W Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Data [0 ] 0
|
||||
NO_DR_B_W Data [0 ] 0
|
||||
NO_DR_B_W Exclusive_Data [0 ] 0
|
||||
NO_DR_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_D GETX [0 ] 0
|
||||
NO_DR_B_D GETS [0 ] 0
|
||||
NO_DR_B_D PUT [0 ] 0
|
||||
NO_DR_B_D Pf_Replacement [0 ] 0
|
||||
NO_DR_B_D DMA_READ [0 ] 0
|
||||
NO_DR_B_D DMA_WRITE [0 ] 0
|
||||
NO_DR_B_D Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Data [0 ] 0
|
||||
NO_DR_B_D Data [0 ] 0
|
||||
NO_DR_B_D Exclusive_Data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B_D GETF [0 ] 0
|
||||
|
||||
NO_DR_B GETX [0 ] 0
|
||||
NO_DR_B GETS [0 ] 0
|
||||
NO_DR_B PUT [0 ] 0
|
||||
NO_DR_B Pf_Replacement [0 ] 0
|
||||
NO_DR_B DMA_READ [0 ] 0
|
||||
NO_DR_B DMA_WRITE [0 ] 0
|
||||
NO_DR_B Ack [0 ] 0
|
||||
NO_DR_B Shared_Ack [0 ] 0
|
||||
NO_DR_B Shared_Data [0 ] 0
|
||||
NO_DR_B Data [0 ] 0
|
||||
NO_DR_B Exclusive_Data [0 ] 0
|
||||
NO_DR_B All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B GETF [0 ] 0
|
||||
|
||||
NO_DW_W GETX [0 ] 0
|
||||
NO_DW_W GETS [0 ] 0
|
||||
NO_DW_W PUT [0 ] 0
|
||||
NO_DW_W Pf_Replacement [0 ] 0
|
||||
NO_DW_W DMA_READ [0 ] 0
|
||||
NO_DW_W DMA_WRITE [0 ] 0
|
||||
NO_DW_W Memory_Ack [0 ] 0
|
||||
NO_DW_W GETF [0 ] 0
|
||||
|
||||
O_DR_B_W GETX [0 ] 0
|
||||
O_DR_B_W GETS [0 ] 0
|
||||
O_DR_B_W PUT [0 ] 0
|
||||
O_DR_B_W Pf_Replacement [0 ] 0
|
||||
O_DR_B_W DMA_READ [0 ] 0
|
||||
O_DR_B_W DMA_WRITE [0 ] 0
|
||||
O_DR_B_W Memory_Data [0 ] 0
|
||||
O_DR_B_W Ack [0 ] 0
|
||||
O_DR_B_W Shared_Ack [0 ] 0
|
||||
O_DR_B_W GETF [0 ] 0
|
||||
|
||||
O_DR_B GETX [0 ] 0
|
||||
O_DR_B GETS [0 ] 0
|
||||
O_DR_B PUT [0 ] 0
|
||||
O_DR_B Pf_Replacement [0 ] 0
|
||||
O_DR_B DMA_READ [0 ] 0
|
||||
O_DR_B DMA_WRITE [0 ] 0
|
||||
O_DR_B Ack [0 ] 0
|
||||
O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [4 ] 4
|
||||
WB GETS [14 ] 14
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [344 ] 344
|
||||
WB Writeback_Exclusive_Dirty [81 ] 81
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
WB GETF [0 ] 0
|
||||
|
||||
WB_O_W GETX [0 ] 0
|
||||
WB_O_W GETS [0 ] 0
|
||||
WB_O_W PUT [0 ] 0
|
||||
WB_O_W Pf_Replacement [0 ] 0
|
||||
WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [2 ] 2
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [81 ] 81
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
NO_F GETS [0 ] 0
|
||||
NO_F PUT [0 ] 0
|
||||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [0 ] 0
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
NO_F_W PUT [0 ] 0
|
||||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu
|
|||
sim_ticks 35432 # Number of ticks simulated
|
||||
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17259 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17257 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 237238 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 151196 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 14099 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 14097 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 193809 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 145312 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
|
||||
|
|
@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 522 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 441 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 81 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 246 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 39 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 39 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.074713 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 15 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 15 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 5 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.45% 3.45% | 10 1.92% 5.36% | 0 0.00% 5.36% | 36 6.90% 12.26% | 20 3.83% 16.09% | 19 3.64% 19.73% | 31 5.94% 25.67% | 22 4.21% 29.89% | 5 0.96% 30.84% | 4 0.77% 31.61% | 7 1.34% 32.95% | 4 0.77% 33.72% | 22 4.21% 37.93% | 41 7.85% 45.79% | 22 4.21% 50.00% | 3 0.57% 50.57% | 4 0.77% 51.34% | 6 1.15% 52.49% | 7 1.34% 53.83% | 13 2.49% 56.32% | 10 1.92% 58.24% | 18 3.45% 61.69% | 14 2.68% 64.37% | 41 7.85% 72.22% | 16 3.07% 75.29% | 5 0.96% 76.25% | 5 0.96% 77.20% | 12 2.30% 79.50% | 13 2.49% 81.99% | 18 3.45% 85.44% | 14 2.68% 88.12% | 62 11.88% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 522 # Number of accesses per bank
|
||||
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
|
|
@ -78,5 +92,65 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 35432 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 422 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 2591 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 298 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L2_Replacement 425 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_to_L2 502 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1D 47 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1I 22 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Complete_L2_to_L1 69 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data 441 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 425 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.All_acks_no_sharers 441 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 146 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 248 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 47 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 109 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 2315 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 35 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L2_Replacement 344 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_to_L2 397 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 23 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1I 22 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 124 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 201 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L2_Replacement 81 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_to_L2 105 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 24 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Load 22 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Ifetch 22 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Store 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Load 14 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Store 10 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data 47 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 394 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 47 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data 394 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Load 7 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Ifetch 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Store 4 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 425 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 45 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 24 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 51 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 410 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUT 425 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.UnblockM 440 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 344 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 81 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 441 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 81 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.PUT 425 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETX 47 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETS 394 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.UnblockM 440 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_W.Memory_Data 441 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETX 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETS 14 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 344 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 81 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Mar/06/2013 20:31:07
|
||||
Real time: Jun/08/2013 13:43:10
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.51
|
||||
Virtual_time_in_minutes: 0.0085
|
||||
Virtual_time_in_hours: 0.000141667
|
||||
Virtual_time_in_days: 5.90278e-06
|
||||
Virtual_time_in_seconds: 0.44
|
||||
Virtual_time_in_minutes: 0.00733333
|
||||
Virtual_time_in_hours: 0.000122222
|
||||
Virtual_time_in_days: 5.09259e-06
|
||||
|
||||
Ruby_current_time: 52498
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 52498
|
||||
|
||||
mbytes_resident: 53.0938
|
||||
mbytes_total: 145.422
|
||||
resident_ratio: 0.365182
|
||||
|
||||
ruby_cycles_executed: [ 52499 ]
|
||||
mbytes_resident: 53.0039
|
||||
mbytes_total: 140.805
|
||||
resident_ratio: 0.376491
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -64,7 +62,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -85,10 +82,10 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10892
|
||||
page_reclaims: 11286
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 1328
|
||||
block_inputs: 0
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
|
|
@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 5.94308
|
|||
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [415 ] 415
|
||||
Ifetch [2585 ] 2585
|
||||
Store [294 ] 294
|
||||
Data [626 ] 626
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [622 ] 622
|
||||
Writeback_Ack [622 ] 622
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [245 ] 245
|
||||
I Ifetch [297 ] 297
|
||||
I Store [84 ] 84
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [170 ] 170
|
||||
M Ifetch [2288 ] 2288
|
||||
M Store [210 ] 210
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [622 ] 622
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [622 ] 622
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [542 ] 542
|
||||
|
||||
IM Data [84 ] 84
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1248
|
||||
memory_reads: 626
|
||||
memory_writes: 622
|
||||
memory_refreshes: 365
|
||||
memory_total_request_delays: 915
|
||||
memory_delays_per_request: 0.733173
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 915
|
||||
memory_stalls_for_bank_busy: 352
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 40
|
||||
memory_stalls_for_bus: 497
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 26
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [626 ] 626
|
||||
GETS [0 ] 0
|
||||
PUTX [622 ] 622
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [626 ] 626
|
||||
Memory_Ack [622 ] 622
|
||||
|
||||
- Transitions -
|
||||
I GETX [626 ] 626
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [622 ] 622
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [626 ] 626
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [622 ] 622
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,16 +4,30 @@ sim_seconds 0.000052 # Nu
|
|||
sim_ticks 52498 # Number of ticks simulated
|
||||
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 9649 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 9649 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 196549 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 151788 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
host_inst_rate 30872 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30864 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 628609 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 144188 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1248 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 626 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 622 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 915 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 915 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.733173 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 352 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 497 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 26 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 55 4.41% 4.41% | 40 3.21% 7.61% | 0 0.00% 7.61% | 100 8.01% 15.62% | 42 3.37% 18.99% | 42 3.37% 22.36% | 88 7.05% 29.41% | 45 3.61% 33.01% | 14 1.12% 34.13% | 10 0.80% 34.94% | 14 1.12% 36.06% | 10 0.80% 36.86% | 46 3.69% 40.54% | 82 6.57% 47.12% | 38 3.04% 50.16% | 6 0.48% 50.64% | 22 1.76% 52.40% | 14 1.12% 53.53% | 14 1.12% 54.65% | 48 3.85% 58.49% | 20 1.60% 60.10% | 52 4.17% 64.26% | 26 2.08% 66.35% | 92 7.37% 73.72% | 34 2.72% 76.44% | 10 0.80% 77.24% | 12 0.96% 78.21% | 24 1.92% 80.13% | 28 2.24% 82.37% | 44 3.53% 85.90% | 38 3.04% 88.94% | 138 11.06% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1248 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -69,5 +83,29 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 52498 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data 626 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Replacement 622 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 622 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 245 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 297 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 84 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 170 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 2288 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 210 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement 622 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 622 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data 542 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data 84 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 626 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 622 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 626 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 622 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 626 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 622 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 626 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 622 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,16 +4,31 @@ sim_seconds 0.000125 # Nu
|
|||
sim_ticks 125334 # Number of ticks simulated
|
||||
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24800 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24798 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 534538 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 154892 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
host_inst_rate 43626 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 43619 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 940162 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 147408 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1493 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7903 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 2982 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1493 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1489 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 871 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2125 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 5 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 2130 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.714286 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 839 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1172 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 34 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 80 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 236 7.91% 7.91% | 108 3.62% 11.54% | 74 2.48% 14.02% | 51 1.71% 15.73% | 26 0.87% 16.60% | 104 3.49% 20.09% | 18 0.60% 20.69% | 38 1.27% 21.97% | 16 0.54% 22.50% | 52 1.74% 24.25% | 154 5.16% 29.41% | 50 1.68% 31.09% | 22 0.74% 31.82% | 70 2.35% 34.17% | 30 1.01% 35.18% | 220 7.38% 42.56% | 80 2.68% 45.24% | 58 1.95% 47.18% | 80 2.68% 49.87% | 118 3.96% 53.82% | 42 1.41% 55.23% | 52 1.74% 56.98% | 82 2.75% 59.73% | 168 5.63% 65.36% | 116 3.89% 69.25% | 80 2.68% 71.93% | 138 4.63% 76.56% | 110 3.69% 80.25% | 208 6.98% 87.22% | 273 9.15% 96.38% | 40 1.34% 97.72% | 68 2.28% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2982 # Number of accesses per bank
|
||||
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
|
|
@ -55,5 +70,29 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 125334 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 1163 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 5815 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 925 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data 1493 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Replacement 1489 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 1489 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 677 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 596 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 220 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 486 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 5219 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 705 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement 1489 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 1489 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data 1273 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 1493 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 1489 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1493 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 1489 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 1493 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 1489 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 1493 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 1489 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Mar/06/2013 20:57:13
|
||||
Real time: Jun/08/2013 14:17:53
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.57
|
||||
Virtual_time_in_minutes: 0.0095
|
||||
Virtual_time_in_hours: 0.000158333
|
||||
Virtual_time_in_days: 6.59722e-06
|
||||
Virtual_time_in_seconds: 0.49
|
||||
Virtual_time_in_minutes: 0.00816667
|
||||
Virtual_time_in_hours: 0.000136111
|
||||
Virtual_time_in_days: 5.6713e-06
|
||||
|
||||
Ruby_current_time: 107952
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 107952
|
||||
|
||||
mbytes_resident: 55.75
|
||||
mbytes_total: 154.406
|
||||
resident_ratio: 0.361111
|
||||
|
||||
ruby_cycles_executed: [ 107953 ]
|
||||
mbytes_resident: 55.6289
|
||||
mbytes_total: 144.984
|
||||
resident_ratio: 0.383743
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -64,7 +62,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -85,10 +82,10 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12080
|
||||
page_faults: 2
|
||||
page_reclaims: 11996
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 32
|
||||
block_inputs: 0
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
|
|
@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 5.96098
|
|||
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [715 ] 715
|
||||
Ifetch [5370 ] 5370
|
||||
Store [673 ] 673
|
||||
Data [1289 ] 1289
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [1285 ] 1285
|
||||
Writeback_Ack [1285 ] 1285
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [395 ] 395
|
||||
I Ifetch [715 ] 715
|
||||
I Store [179 ] 179
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [320 ] 320
|
||||
M Ifetch [4655 ] 4655
|
||||
M Store [494 ] 494
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1285 ] 1285
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [1285 ] 1285
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [1110 ] 1110
|
||||
|
||||
IM Data [179 ] 179
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 2574
|
||||
memory_reads: 1289
|
||||
memory_writes: 1285
|
||||
memory_refreshes: 750
|
||||
memory_total_request_delays: 1873
|
||||
memory_delays_per_request: 0.727661
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1871
|
||||
memory_stalls_for_bank_busy: 758
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 69
|
||||
memory_stalls_for_bus: 992
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 52
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [1289 ] 1289
|
||||
GETS [0 ] 0
|
||||
PUTX [1285 ] 1285
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1289 ] 1289
|
||||
Memory_Ack [1285 ] 1285
|
||||
|
||||
- Transitions -
|
||||
I GETX [1289 ] 1289
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [1285 ] 1285
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [1289 ] 1289
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [1285 ] 1285
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,16 +4,31 @@ sim_seconds 0.000108 # Nu
|
|||
sim_ticks 107952 # Number of ticks simulated
|
||||
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 36056 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36051 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 730482 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 160860 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 37306 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 37301 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 755806 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 148468 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank
|
||||
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 107952 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -37,5 +52,29 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 107952 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 715 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 5370 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 673 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data 1289 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Replacement 1285 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 1285 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 395 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 715 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 179 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 320 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 4655 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 494 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement 1285 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 1285 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data 1110 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data 179 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 1289 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 1285 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1289 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 1285 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 1289 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 1285 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 1289 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 1285 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Mar/11/2013 13:21:59
|
||||
Real time: Jun/08/2013 14:40:51
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.6
|
||||
Virtual_time_in_minutes: 0.01
|
||||
Virtual_time_in_hours: 0.000166667
|
||||
Virtual_time_in_days: 6.94444e-06
|
||||
Virtual_time_in_seconds: 0.54
|
||||
Virtual_time_in_minutes: 0.009
|
||||
Virtual_time_in_hours: 0.00015
|
||||
Virtual_time_in_days: 6.25e-06
|
||||
|
||||
Ruby_current_time: 121759
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 121759
|
||||
|
||||
mbytes_resident: 66.582
|
||||
mbytes_total: 163.426
|
||||
resident_ratio: 0.407486
|
||||
|
||||
ruby_cycles_executed: [ 121760 ]
|
||||
mbytes_resident: 66.5
|
||||
mbytes_total: 158.215
|
||||
resident_ratio: 0.420364
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -67,7 +65,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -88,11 +85,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 14769
|
||||
page_reclaims: 13753
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 88
|
||||
block_outputs: 96
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -136,129 +133,3 @@ links_utilized_percent_switch_2: 5.6464
|
|||
outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1045 ] 1045
|
||||
Ifetch [6864 ] 6864
|
||||
Store [943 ] 943
|
||||
Data [1377 ] 1377
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [1373 ] 1373
|
||||
Writeback_Ack [1373 ] 1373
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [499 ] 499
|
||||
I Ifetch [623 ] 623
|
||||
I Store [255 ] 255
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [546 ] 546
|
||||
M Ifetch [6241 ] 6241
|
||||
M Store [688 ] 688
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1373 ] 1373
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [1373 ] 1373
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [1122 ] 1122
|
||||
|
||||
IM Data [255 ] 255
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 2750
|
||||
memory_reads: 1377
|
||||
memory_writes: 1373
|
||||
memory_refreshes: 846
|
||||
memory_total_request_delays: 1968
|
||||
memory_delays_per_request: 0.715636
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1965
|
||||
memory_stalls_for_bank_busy: 823
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 65
|
||||
memory_stalls_for_bus: 1044
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 33
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [1377 ] 1377
|
||||
GETS [0 ] 0
|
||||
PUTX [1373 ] 1373
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1377 ] 1377
|
||||
Memory_Ack [1373 ] 1373
|
||||
|
||||
- Transitions -
|
||||
I GETX [1377 ] 1377
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [1373 ] 1373
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [1377 ] 1377
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [1373 ] 1373
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,16 +4,31 @@ sim_seconds 0.000122 # Nu
|
|||
sim_ticks 121759 # Number of ticks simulated
|
||||
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 32232 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58383 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 729156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 170120 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_inst_rate 37945 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 68729 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 858310 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 162016 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 2750 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1377 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1373 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 846 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1965 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1968 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.715636 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 823 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1044 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 33 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 65 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 160 5.82% 5.82% | 144 5.24% 11.05% | 210 7.64% 18.69% | 146 5.31% 24.00% | 196 7.13% 31.13% | 96 3.49% 34.62% | 66 2.40% 37.02% | 38 1.38% 38.40% | 22 0.80% 39.20% | 20 0.73% 39.93% | 184 6.69% 46.62% | 297 10.80% 57.42% | 71 2.58% 60.00% | 124 4.51% 64.51% | 60 2.18% 66.69% | 18 0.65% 67.35% | 84 3.05% 70.40% | 6 0.22% 70.62% | 8 0.29% 70.91% | 14 0.51% 71.42% | 92 3.35% 74.76% | 56 2.04% 76.80% | 14 0.51% 77.31% | 60 2.18% 79.49% | 34 1.24% 80.73% | 58 2.11% 82.84% | 84 3.05% 85.89% | 66 2.40% 88.29% | 42 1.53% 89.82% | 122 4.44% 94.25% | 104 3.78% 98.04% | 54 1.96% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2750 # Number of accesses per bank
|
||||
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 121759 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -37,5 +52,29 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 121759 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.ruby.l1_cntrl0.Load 1045 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 6864 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 943 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data 1377 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Replacement 1373 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 1373 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 499 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 623 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 255 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 546 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 6241 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 688 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement 1373 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 1373 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data 1122 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data 255 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 1377 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 1373 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 1377 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 1373 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 1377 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 1373 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 1377 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 1373 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Apr/09/2013 02:05:31
|
||||
Real time: Jun/08/2013 14:13:51
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 139
|
||||
Elapsed_time_in_minutes: 2.31667
|
||||
Elapsed_time_in_hours: 0.0386111
|
||||
Elapsed_time_in_days: 0.0016088
|
||||
Elapsed_time_in_seconds: 78
|
||||
Elapsed_time_in_minutes: 1.3
|
||||
Elapsed_time_in_hours: 0.0216667
|
||||
Elapsed_time_in_days: 0.000902778
|
||||
|
||||
Virtual_time_in_seconds: 139.38
|
||||
Virtual_time_in_minutes: 2.323
|
||||
Virtual_time_in_hours: 0.0387167
|
||||
Virtual_time_in_days: 0.00161319
|
||||
Virtual_time_in_seconds: 78.87
|
||||
Virtual_time_in_minutes: 1.3145
|
||||
Virtual_time_in_hours: 0.0219083
|
||||
Virtual_time_in_days: 0.000912847
|
||||
|
||||
Ruby_current_time: 7257449
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 7257449
|
||||
|
||||
mbytes_resident: 65.4102
|
||||
mbytes_total: 245.32
|
||||
resident_ratio: 0.266632
|
||||
|
||||
ruby_cycles_executed: [ 7257450 7257450 7257450 7257450 7257450 7257450 7257450 7257450 ]
|
||||
mbytes_resident: 71.2383
|
||||
mbytes_total: 285.629
|
||||
resident_ratio: 0.249436
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -60,7 +58,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -79,13 +76,13 @@ Total_delay_cycles: [binsize: 32 max: 952 count: 4856797 average: 43.4082 | stan
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 139
|
||||
user_time: 78
|
||||
system_time: 0
|
||||
page_reclaims: 17300
|
||||
page_faults: 7
|
||||
page_reclaims: 11392
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 1648
|
||||
block_outputs: 296
|
||||
block_inputs: 0
|
||||
block_outputs: 272
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -293,458 +290,3 @@ links_utilized_percent_switch_10: 14.8743
|
|||
outgoing_messages_switch_10_link_9_Response_Data: 212955 15332760 [ 0 212955 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Response_Control: 392034 3136272 [ 0 392034 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [49778 49377 49516 49381 49747 49368 50044 49642 ] 396853
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [26786 26679 26651 26574 26897 26600 26631 26746 ] 213564
|
||||
Inv [73735 73350 73434 73266 73836 73403 73975 73550 ] 588549
|
||||
L1_Replacement [533617 530929 531837 527767 533499 530493 533236 532831 ] 4254209
|
||||
Fwd_GETX [198 220 198 200 215 204 212 216 ] 1663
|
||||
Fwd_GETS [159 151 153 155 149 129 133 142 ] 1171
|
||||
Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
Data [1 2 1 0 3 2 1 1 ] 11
|
||||
Data_Exclusive [48989 48607 48775 48593 48923 48630 49230 48877 ] 390624
|
||||
DataS_fromL1 [147 148 149 152 133 124 182 136 ] 1171
|
||||
Data_all_Acks [27420 27295 27237 27204 27578 27207 27259 27370 ] 218570
|
||||
Ack [1 2 1 0 3 2 1 1 ] 11
|
||||
Ack_all [1 2 1 0 3 2 1 1 ] 11
|
||||
WB_Ack [40110 39623 40034 39662 40309 39563 40425 40081 ] 319807
|
||||
PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [49768 49368 49506 49370 49736 49359 50040 49632 ] 396779
|
||||
NP Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Store [26783 26673 26639 26570 26890 26593 26629 26744 ] 213521
|
||||
NP Inv [436 404 386 385 420 399 405 385 ] 3220
|
||||
NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
NP PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
NP PF_Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
NP PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
I Load [8 9 9 9 9 8 4 8 ] 64
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [2 6 11 4 6 6 2 2 ] 39
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I L1_Replacement [36061 36066 35776 35948 35950 36049 35879 35962 ] 287691
|
||||
I PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
I PF_Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
S Load [0 0 0 0 0 0 0 0 ] 0
|
||||
S Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
S Store [0 0 0 0 0 0 0 0 ] 0
|
||||
S Inv [475 488 482 528 526 446 511 500 ] 3956
|
||||
S L1_Replacement [375 347 329 325 361 336 360 328 ] 2761
|
||||
S PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
S PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
E Load [2 0 0 0 1 0 0 2 ] 5
|
||||
E Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
E Store [0 0 0 0 0 0 0 0 ] 0
|
||||
E Inv [22855 23068 22724 22855 22694 23009 22944 22917 ] 183066
|
||||
E L1_Replacement [26080 25475 25987 25671 26159 25558 26202 25901 ] 207033
|
||||
E Fwd_GETX [47 55 52 62 56 56 77 52 ] 457
|
||||
E Fwd_GETS [7 9 12 5 14 7 7 7 ] 68
|
||||
E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
E PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
E PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M Load [0 0 0 1 1 1 0 0 ] 3
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [1 0 1 0 0 1 0 0 ] 3
|
||||
M Inv [12660 12445 12509 12484 12663 12517 12326 12472 ] 100076
|
||||
M L1_Replacement [14031 14149 14049 13992 14152 14005 14224 14181 ] 112783
|
||||
M Fwd_GETX [34 25 30 32 26 36 27 32 ] 242
|
||||
M Fwd_GETS [59 60 61 63 54 40 53 61 ] 451
|
||||
M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
M PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Inv [0 0 0 0 0 0 1 1 ] 2
|
||||
IS L1_Replacement [297388 295578 296859 294148 297188 294582 298840 297864 ] 2372447
|
||||
IS Data_Exclusive [48989 48607 48775 48593 48923 48630 49230 48877 ] 390624
|
||||
IS DataS_fromL1 [147 148 149 152 133 124 182 136 ] 1171
|
||||
IS Data_all_Acks [637 618 589 633 686 611 629 624 ] 5027
|
||||
IS PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IM L1_Replacement [159682 159314 158837 157683 159689 159963 157731 158595 ] 1271494
|
||||
IM Data [1 2 1 0 3 2 1 1 ] 11
|
||||
IM Data_all_Acks [26783 26677 26648 26571 26892 26596 26629 26745 ] 213541
|
||||
IM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
IM PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ack [1 2 1 0 3 2 1 1 ] 11
|
||||
SM Ack_all [1 2 1 0 3 2 1 1 ] 11
|
||||
SM PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Data_all_Acks [0 0 0 0 0 0 1 1 ] 2
|
||||
IS_I PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Inv [37277 36920 37310 36987 37511 37013 37760 37258 ] 298036
|
||||
M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Fwd_GETX [117 140 116 106 133 112 108 132 ] 964
|
||||
M_I Fwd_GETS [93 82 80 87 81 82 73 74 ] 652
|
||||
M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I WB_Ack [2624 2482 2530 2483 2584 2356 2484 2618 ] 20161
|
||||
M_I PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SINK_WB_ACK Load [0 0 1 1 0 0 0 0 ] 2
|
||||
SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK Store [0 0 0 0 1 0 0 0 ] 1
|
||||
SINK_WB_ACK Inv [32 25 23 27 22 19 28 17 ] 193
|
||||
SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [37486 37141 37504 37179 37725 37207 37941 37463 ] 299646
|
||||
SINK_WB_ACK PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
PF_IS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS Data_all_Acks [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
PF_IM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM Data [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM Data_all_Acks [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM PF_Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IM PF_Store [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
PF_SM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_SM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_SM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_SM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_SM Ack_all [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
PF_IS_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS_I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0
|
||||
PF_IS_I Data_all_Acks [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [0 ] 0
|
||||
L1_GETS [398575 ] 398575
|
||||
L1_GETX [215875 ] 215875
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [21987 ] 21987
|
||||
L1_PUTX_old [305455 ] 305455
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [8554 ] 8554
|
||||
L2_Replacement_clean [4607156 ] 4607156
|
||||
Mem_Data [604993 ] 604993
|
||||
Mem_Ack [604984 ] 604984
|
||||
WB_Data [205698 ] 205698
|
||||
WB_Data_clean [193585 ] 193585
|
||||
Ack [3680 ] 3680
|
||||
Ack_all [186735 ] 186735
|
||||
Unblock [1171 ] 1171
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [604175 ] 604175
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [0 ] 0
|
||||
NP L1_GETS [393127 ] 393127
|
||||
NP L1_GETX [211871 ] 211871
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [283962 ] 283962
|
||||
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [4 ] 4
|
||||
SS L1_GETX [11 ] 11
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [456 ] 456
|
||||
SS L1_PUTX_old [1 ] 1
|
||||
SS L2_Replacement [1087 ] 1087
|
||||
SS L2_Replacement_clean [2582 ] 2582
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [9 ] 9
|
||||
M L1_GETX [9 ] 9
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [7258 ] 7258
|
||||
M L2_Replacement_clean [12885 ] 12885
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [1171 ] 1171
|
||||
MT L1_GETX [1663 ] 1663
|
||||
MT L1_PUTX [20161 ] 20161
|
||||
MT L1_PUTX_old [694 ] 694
|
||||
MT L2_Replacement [5 ] 5
|
||||
MT L2_Replacement_clean [581173 ] 581173
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [226 ] 226
|
||||
M_I L1_GETX [136 ] 136
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [13952 ] 13952
|
||||
M_I Mem_Ack [604984 ] 604984
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [3 ] 3
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [2 ] 2
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [67 ] 67
|
||||
MCT_I L1_GETX [78 ] 78
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [6266 ] 6266
|
||||
MCT_I WB_Data [204606 ] 204606
|
||||
MCT_I WB_Data_clean [193503 ] 193503
|
||||
MCT_I Ack_all [183064 ] 183064
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [1 ] 1
|
||||
I_I Ack [2590 ] 2590
|
||||
I_I Ack_all [2582 ] 2582
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [1090 ] 1090
|
||||
S_I Ack_all [1087 ] 1087
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [2509 ] 2509
|
||||
ISS L1_GETX [1307 ] 1307
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [266 ] 266
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [2167226 ] 2167226
|
||||
ISS Mem_Data [390615 ] 390615
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [7 ] 7
|
||||
IS L1_GETX [3 ] 3
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [1 ] 1
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [14533 ] 14533
|
||||
IS Mem_Data [2509 ] 2509
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [1302 ] 1302
|
||||
IM L1_GETX [709 ] 709
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [310 ] 310
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [1170224 ] 1170224
|
||||
IM Mem_Data [211869 ] 211869
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [5 ] 5
|
||||
SS_MB L2_Replacement_clean [10 ] 10
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [11 ] 11
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [151 ] 151
|
||||
MT_MB L1_GETX [87 ] 87
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [840 ] 840
|
||||
MT_MB L1_PUTX_old [1 ] 1
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [655321 ] 655321
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [604164 ] 604164
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [2 ] 2
|
||||
MT_IIB L1_GETX [1 ] 1
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [527 ] 527
|
||||
MT_IIB L1_PUTX_old [1 ] 1
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [3164 ] 3164
|
||||
MT_IIB WB_Data [727 ] 727
|
||||
MT_IIB WB_Data_clean [53 ] 53
|
||||
MT_IIB Unblock [391 ] 391
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [1 ] 1
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [38 ] 38
|
||||
MT_IB WB_Data [362 ] 362
|
||||
MT_IB WB_Data_clean [29 ] 29
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [2 ] 2
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [199 ] 199
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [780 ] 780
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 817953
|
||||
memory_reads: 604997
|
||||
memory_writes: 212953
|
||||
memory_refreshes: 50399
|
||||
memory_total_request_delays: 5673617
|
||||
memory_delays_per_request: 6.93636
|
||||
memory_delays_in_input_queue: 172403
|
||||
memory_delays_behind_head_of_bank_queue: 411771
|
||||
memory_delays_stalled_at_head_of_bank_queue: 5089443
|
||||
memory_stalls_for_bank_busy: 991356
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 192369
|
||||
memory_stalls_for_arbitration: 976938
|
||||
memory_stalls_for_bus: 1587349
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 927948
|
||||
memory_stalls_for_read_read_turnaround: 413483
|
||||
accesses_per_bank: 25693 25309 25639 25493 25446 25240 25202 25657 25510 25612 25713 25863 25420 25756 25574 25666 25584 25558 25869 25665 25398 25614 25401 25740 25400 25542 25601 25502 25584 25779 25408 25515
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [604998 ] 604998
|
||||
Data [212955 ] 212955
|
||||
Memory_Data [604995 ] 604995
|
||||
Memory_Ack [212951 ] 212951
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [392034 ] 392034
|
||||
|
||||
- Transitions -
|
||||
I Fetch [604998 ] 604998
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [212955 ] 212955
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [392034 ] 392034
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [604995 ] 604995
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [212951 ] 212951
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.007257 # Nu
|
|||
sim_ticks 7257449 # Number of ticks simulated
|
||||
final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 119266 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252632 # Number of bytes of host memory used
|
||||
host_seconds 60.85 # Real time elapsed on the host
|
||||
host_tick_rate 92293 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292488 # Number of bytes of host memory used
|
||||
host_seconds 78.63 # Real time elapsed on the host
|
||||
system.funcbus.throughput 0 # Throughput (bytes/s)
|
||||
system.funcbus.data_through_bus 0 # Total data (bytes)
|
||||
system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits
|
||||
|
|
@ -132,6 +132,24 @@ system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0
|
|||
system.ruby.l2_cntrl0.L2cache.demand_hits 33 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 610348 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 610381 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 817953 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 604997 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 212953 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 50399 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 5089443 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 172403 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 411771 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 5673617 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 6.936361 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 991356 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1587349 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 927948 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 413483 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 976938 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 192369 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 25693 3.14% 3.14% | 25309 3.09% 6.24% | 25639 3.13% 9.37% | 25493 3.12% 12.49% | 25446 3.11% 15.60% | 25240 3.09% 18.68% | 25202 3.08% 21.76% | 25657 3.14% 24.90% | 25510 3.12% 28.02% | 25612 3.13% 31.15% | 25713 3.14% 34.29% | 25863 3.16% 37.46% | 25420 3.11% 40.56% | 25756 3.15% 43.71% | 25574 3.13% 46.84% | 25666 3.14% 49.98% | 25584 3.13% 53.11% | 25558 3.12% 56.23% | 25869 3.16% 59.39% | 25665 3.14% 62.53% | 25398 3.11% 65.64% | 25614 3.13% 68.77% | 25401 3.11% 71.87% | 25740 3.15% 75.02% | 25400 3.11% 78.12% | 25542 3.12% 81.25% | 25601 3.13% 84.38% | 25502 3.12% 87.49% | 25584 3.13% 90.62% | 25779 3.15% 93.77% | 25408 3.11% 96.88% | 25515 3.12% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 817953 # Number of accesses per bank
|
||||
|
||||
system.cpu0.num_reads 99060 # number of read accesses completed
|
||||
system.cpu0.num_writes 53442 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
|
|
@ -156,5 +174,257 @@ system.cpu6.num_copies 0 # nu
|
|||
system.cpu7.num_reads 99052 # number of read accesses completed
|
||||
system.cpu7.num_writes 53517 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.ruby.l1_cntrl0.Load | 49778 12.54% 12.54% | 49377 12.44% 24.99% | 49516 12.48% 37.46% | 49381 12.44% 49.91% | 49747 12.54% 62.44% | 49368 12.44% 74.88% | 50044 12.61% 87.49% | 49642 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 396853
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 26786 12.54% 12.54% | 26679 12.49% 25.03% | 26651 12.48% 37.51% | 26574 12.44% 49.96% | 26897 12.59% 62.55% | 26600 12.46% 75.01% | 26631 12.47% 87.48% | 26746 12.52% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 213564
|
||||
|
||||
system.ruby.l1_cntrl0.Inv | 73735 12.53% 12.53% | 73350 12.46% 24.99% | 73434 12.48% 37.47% | 73266 12.45% 49.92% | 73836 12.55% 62.46% | 73403 12.47% 74.93% | 73975 12.57% 87.50% | 73550 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Inv::total 588549
|
||||
|
||||
system.ruby.l1_cntrl0.L1_Replacement | 533617 12.54% 12.54% | 530929 12.48% 25.02% | 531837 12.50% 37.52% | 527767 12.41% 49.93% | 533499 12.54% 62.47% | 530493 12.47% 74.94% | 533236 12.53% 87.48% | 532831 12.52% 100.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement::total 4254209
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETX | 198 11.91% 11.91% | 220 13.23% 25.14% | 198 11.91% 37.04% | 200 12.03% 49.07% | 215 12.93% 62.00% | 204 12.27% 74.26% | 212 12.75% 87.01% | 216 12.99% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETX::total 1663
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETS | 159 13.58% 13.58% | 151 12.89% 26.47% | 153 13.07% 39.54% | 155 13.24% 52.78% | 149 12.72% 65.50% | 129 11.02% 76.52% | 133 11.36% 87.87% | 142 12.13% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETS::total 1171
|
||||
|
||||
system.ruby.l1_cntrl0.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
|
||||
system.ruby.l1_cntrl0.Data::total 11
|
||||
|
||||
system.ruby.l1_cntrl0.Data_Exclusive | 48989 12.54% 12.54% | 48607 12.44% 24.98% | 48775 12.49% 37.47% | 48593 12.44% 49.91% | 48923 12.52% 62.44% | 48630 12.45% 74.88% | 49230 12.60% 87.49% | 48877 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_Exclusive::total 390624
|
||||
|
||||
system.ruby.l1_cntrl0.DataS_fromL1 | 147 12.55% 12.55% | 148 12.64% 25.19% | 149 12.72% 37.92% | 152 12.98% 50.90% | 133 11.36% 62.25% | 124 10.59% 72.84% | 182 15.54% 88.39% | 136 11.61% 100.00%
|
||||
system.ruby.l1_cntrl0.DataS_fromL1::total 1171
|
||||
|
||||
system.ruby.l1_cntrl0.Data_all_Acks | 27420 12.55% 12.55% | 27295 12.49% 25.03% | 27237 12.46% 37.49% | 27204 12.45% 49.94% | 27578 12.62% 62.56% | 27207 12.45% 75.01% | 27259 12.47% 87.48% | 27370 12.52% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_all_Acks::total 218570
|
||||
|
||||
system.ruby.l1_cntrl0.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack::total 11
|
||||
|
||||
system.ruby.l1_cntrl0.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack_all::total 11
|
||||
|
||||
system.ruby.l1_cntrl0.WB_Ack | 40110 12.54% 12.54% | 39623 12.39% 24.93% | 40034 12.52% 37.45% | 39662 12.40% 49.85% | 40309 12.60% 62.46% | 39563 12.37% 74.83% | 40425 12.64% 87.47% | 40081 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.WB_Ack::total 319807
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Load | 49768 12.54% 12.54% | 49368 12.44% 24.99% | 49506 12.48% 37.46% | 49370 12.44% 49.90% | 49736 12.53% 62.44% | 49359 12.44% 74.88% | 50040 12.61% 87.49% | 49632 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Load::total 396779
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Store | 26783 12.54% 12.54% | 26673 12.49% 25.04% | 26639 12.48% 37.51% | 26570 12.44% 49.96% | 26890 12.59% 62.55% | 26593 12.45% 75.00% | 26629 12.47% 87.47% | 26744 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Store::total 213521
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Inv | 436 13.54% 13.54% | 404 12.55% 26.09% | 386 11.99% 38.07% | 385 11.96% 50.03% | 420 13.04% 63.07% | 399 12.39% 75.47% | 405 12.58% 88.04% | 385 11.96% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Inv::total 3220
|
||||
|
||||
system.ruby.l1_cntrl0.I.Load | 8 12.50% 12.50% | 9 14.06% 26.56% | 9 14.06% 40.62% | 9 14.06% 54.69% | 9 14.06% 68.75% | 8 12.50% 81.25% | 4 6.25% 87.50% | 8 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Load::total 64
|
||||
|
||||
system.ruby.l1_cntrl0.I.Store | 2 5.13% 5.13% | 6 15.38% 20.51% | 11 28.21% 48.72% | 4 10.26% 58.97% | 6 15.38% 74.36% | 6 15.38% 89.74% | 2 5.13% 94.87% | 2 5.13% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Store::total 39
|
||||
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement | 36061 12.53% 12.53% | 36066 12.54% 25.07% | 35776 12.44% 37.51% | 35948 12.50% 50.00% | 35950 12.50% 62.50% | 36049 12.53% 75.03% | 35879 12.47% 87.50% | 35962 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement::total 287691
|
||||
|
||||
system.ruby.l1_cntrl0.S.Inv | 475 12.01% 12.01% | 488 12.34% 24.34% | 482 12.18% 36.53% | 528 13.35% 49.87% | 526 13.30% 63.17% | 446 11.27% 74.44% | 511 12.92% 87.36% | 500 12.64% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Inv::total 3956
|
||||
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement | 375 13.58% 13.58% | 347 12.57% 26.15% | 329 11.92% 38.07% | 325 11.77% 49.84% | 361 13.07% 62.91% | 336 12.17% 75.08% | 360 13.04% 88.12% | 328 11.88% 100.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement::total 2761
|
||||
|
||||
system.ruby.l1_cntrl0.E.Load | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Load::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.E.Inv | 22855 12.48% 12.48% | 23068 12.60% 25.09% | 22724 12.41% 37.50% | 22855 12.48% 49.98% | 22694 12.40% 62.38% | 23009 12.57% 74.95% | 22944 12.53% 87.48% | 22917 12.52% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Inv::total 183066
|
||||
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement | 26080 12.60% 12.60% | 25475 12.30% 24.90% | 25987 12.55% 37.45% | 25671 12.40% 49.85% | 26159 12.64% 62.49% | 25558 12.34% 74.83% | 26202 12.66% 87.49% | 25901 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement::total 207033
|
||||
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETX | 47 10.28% 10.28% | 55 12.04% 22.32% | 52 11.38% 33.70% | 62 13.57% 47.26% | 56 12.25% 59.52% | 56 12.25% 71.77% | 77 16.85% 88.62% | 52 11.38% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETX::total 457
|
||||
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETS | 7 10.29% 10.29% | 9 13.24% 23.53% | 12 17.65% 41.18% | 5 7.35% 48.53% | 14 20.59% 69.12% | 7 10.29% 79.41% | 7 10.29% 89.71% | 7 10.29% 100.00%
|
||||
system.ruby.l1_cntrl0.E.Fwd_GETS::total 68
|
||||
|
||||
system.ruby.l1_cntrl0.M.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Load::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.M.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.M.Inv | 12660 12.65% 12.65% | 12445 12.44% 25.09% | 12509 12.50% 37.59% | 12484 12.47% 50.06% | 12663 12.65% 62.71% | 12517 12.51% 75.22% | 12326 12.32% 87.54% | 12472 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Inv::total 100076
|
||||
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement | 14031 12.44% 12.44% | 14149 12.55% 24.99% | 14049 12.46% 37.44% | 13992 12.41% 49.85% | 14152 12.55% 62.40% | 14005 12.42% 74.81% | 14224 12.61% 87.43% | 14181 12.57% 100.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement::total 112783
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX | 34 14.05% 14.05% | 25 10.33% 24.38% | 30 12.40% 36.78% | 32 13.22% 50.00% | 26 10.74% 60.74% | 36 14.88% 75.62% | 27 11.16% 86.78% | 32 13.22% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX::total 242
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETS | 59 13.08% 13.08% | 60 13.30% 26.39% | 61 13.53% 39.91% | 63 13.97% 53.88% | 54 11.97% 65.85% | 40 8.87% 74.72% | 53 11.75% 86.47% | 61 13.53% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETS::total 451
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Inv | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Inv::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement | 297388 12.54% 12.54% | 295578 12.46% 24.99% | 296859 12.51% 37.51% | 294148 12.40% 49.91% | 297188 12.53% 62.43% | 294582 12.42% 74.85% | 298840 12.60% 87.44% | 297864 12.56% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement::total 2372447
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive | 48989 12.54% 12.54% | 48607 12.44% 24.98% | 48775 12.49% 37.47% | 48593 12.44% 49.91% | 48923 12.52% 62.44% | 48630 12.45% 74.88% | 49230 12.60% 87.49% | 48877 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive::total 390624
|
||||
|
||||
system.ruby.l1_cntrl0.IS.DataS_fromL1 | 147 12.55% 12.55% | 148 12.64% 25.19% | 149 12.72% 37.92% | 152 12.98% 50.90% | 133 11.36% 62.25% | 124 10.59% 72.84% | 182 15.54% 88.39% | 136 11.61% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.DataS_fromL1::total 1171
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks | 637 12.67% 12.67% | 618 12.29% 24.97% | 589 11.72% 36.68% | 633 12.59% 49.27% | 686 13.65% 62.92% | 611 12.15% 75.07% | 629 12.51% 87.59% | 624 12.41% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks::total 5027
|
||||
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement | 159682 12.56% 12.56% | 159314 12.53% 25.09% | 158837 12.49% 37.58% | 157683 12.40% 49.98% | 159689 12.56% 62.54% | 159963 12.58% 75.12% | 157731 12.41% 87.53% | 158595 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement::total 1271494
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data::total 11
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks | 26783 12.54% 12.54% | 26677 12.49% 25.04% | 26648 12.48% 37.51% | 26571 12.44% 49.96% | 26892 12.59% 62.55% | 26596 12.45% 75.01% | 26629 12.47% 87.48% | 26745 12.52% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks::total 213541
|
||||
|
||||
system.ruby.l1_cntrl0.SM.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.Ack::total 11
|
||||
|
||||
system.ruby.l1_cntrl0.SM.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.Ack_all::total 11
|
||||
|
||||
system.ruby.l1_cntrl0.IS_I.Data_all_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_I.Data_all_Acks::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.M_I.Inv | 37277 12.51% 12.51% | 36920 12.39% 24.90% | 37310 12.52% 37.41% | 36987 12.41% 49.82% | 37511 12.59% 62.41% | 37013 12.42% 74.83% | 37760 12.67% 87.50% | 37258 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.M_I.Inv::total 298036
|
||||
|
||||
system.ruby.l1_cntrl0.M_I.Fwd_GETX | 117 12.14% 12.14% | 140 14.52% 26.66% | 116 12.03% 38.69% | 106 11.00% 49.69% | 133 13.80% 63.49% | 112 11.62% 75.10% | 108 11.20% 86.31% | 132 13.69% 100.00%
|
||||
system.ruby.l1_cntrl0.M_I.Fwd_GETX::total 964
|
||||
|
||||
system.ruby.l1_cntrl0.M_I.Fwd_GETS | 93 14.26% 14.26% | 82 12.58% 26.84% | 80 12.27% 39.11% | 87 13.34% 52.45% | 81 12.42% 64.88% | 82 12.58% 77.45% | 73 11.20% 88.65% | 74 11.35% 100.00%
|
||||
system.ruby.l1_cntrl0.M_I.Fwd_GETS::total 652
|
||||
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack | 2624 13.02% 13.02% | 2482 12.31% 25.33% | 2530 12.55% 37.88% | 2483 12.32% 50.19% | 2584 12.82% 63.01% | 2356 11.69% 74.69% | 2484 12.32% 87.01% | 2618 12.99% 100.00%
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack::total 20161
|
||||
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Load::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Store::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Inv | 32 16.58% 16.58% | 25 12.95% 29.53% | 23 11.92% 41.45% | 27 13.99% 55.44% | 22 11.40% 66.84% | 19 9.84% 76.68% | 28 14.51% 91.19% | 17 8.81% 100.00%
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Inv::total 193
|
||||
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack | 37486 12.51% 12.51% | 37141 12.39% 24.91% | 37504 12.52% 37.42% | 37179 12.41% 49.83% | 37725 12.59% 62.42% | 37207 12.42% 74.84% | 37941 12.66% 87.50% | 37463 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack::total 299646
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GETS 398575 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 215875 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 21987 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX_old 305455 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 8554 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement_clean 4607156 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Data 604993 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Ack 604984 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data 205698 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data_clean 193585 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack 3680 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack_all 186735 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Unblock 1171 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 604175 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 393127 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 211871 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_PUTX_old 283962 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GETS 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GETX 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_PUTX 456 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_PUTX_old 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement 1087 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement_clean 2582 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 9 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 9 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 7258 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement_clean 12885 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_GETS 1171 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_GETX 1663 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_PUTX 20161 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_PUTX_old 694 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement_clean 581173 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.L1_GETS 226 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.L1_GETX 136 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.L1_PUTX_old 13952 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.Mem_Ack 604984 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.WB_Data 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.L1_GETS 67 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.L1_GETX 78 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 6266 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data 204606 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 193503 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.Ack_all 183064 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.L1_PUTX_old 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack 2590 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack_all 2582 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S_I.Ack 1090 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S_I.Ack_all 1087 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.L1_GETS 2509 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.L1_GETX 1307 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.L1_PUTX_old 266 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 2167226 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.Mem_Data 390615 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.L1_GETS 7 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.L1_GETX 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.L1_PUTX_old 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.L2_Replacement_clean 14533 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.Mem_Data 2509 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.L1_GETS 1302 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.L1_GETX 709 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.L1_PUTX_old 310 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.L2_Replacement_clean 1170224 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.Mem_Data 211869 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.L2_Replacement 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.L2_Replacement_clean 10 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_GETS 151 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_GETX 87 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_PUTX 840 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 655321 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 604164 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.L1_GETS 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.L1_PUTX 527 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.L1_PUTX_old 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.L2_Replacement_clean 3164 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.WB_Data 727 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 53 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IIB.Unblock 391 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IB.L1_PUTX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IB.L2_Replacement_clean 38 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IB.WB_Data 362 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 29 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_SB.L1_PUTX 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_SB.L2_Replacement 199 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_SB.Unblock 780 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Fetch 604998 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data 212955 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 604995 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 212951 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.CleanReplacement 392034 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Fetch 604998 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.Data 212955 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.CleanReplacement 392034 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 604995 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 212951 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.007481 # Nu
|
|||
sim_ticks 7481441 # Number of ticks simulated
|
||||
final_tick 7481441 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 59106 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252804 # Number of bytes of host memory used
|
||||
host_seconds 126.58 # Real time elapsed on the host
|
||||
host_tick_rate 53557 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293688 # Number of bytes of host memory used
|
||||
host_seconds 139.69 # Real time elapsed on the host
|
||||
system.funcbus.throughput 0 # Throughput (bytes/s)
|
||||
system.funcbus.data_through_bus 0 # Total data (bytes)
|
||||
system.ruby.l1_cntrl4.L1Dcache.demand_hits 21 # Number of cache demand hits
|
||||
|
|
@ -60,6 +60,24 @@ system.ruby.l1_cntrl3.L1Icache.demand_accesses 0
|
|||
system.ruby.l2_cntrl0.L2cache.demand_hits 5922 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 613572 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 619494 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 820394 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 605143 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 215243 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 51955 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 11786270 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 6968030 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 3665383 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 22419683 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 27.327946 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 2079686 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 3902603 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 208436 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1319186 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 2932982 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 1343377 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 25992 3.17% 3.17% | 25482 3.11% 6.27% | 25735 3.14% 9.41% | 25728 3.14% 12.55% | 25931 3.16% 15.71% | 25829 3.15% 18.86% | 25430 3.10% 21.96% | 25686 3.13% 25.09% | 25772 3.14% 28.23% | 25394 3.10% 31.32% | 25765 3.14% 34.46% | 25528 3.11% 37.58% | 25775 3.14% 40.72% | 25820 3.15% 43.87% | 25548 3.11% 46.98% | 25750 3.14% 50.12% | 25378 3.09% 53.21% | 25625 3.12% 56.33% | 25783 3.14% 59.48% | 25254 3.08% 62.56% | 25786 3.14% 65.70% | 25466 3.10% 68.80% | 25638 3.13% 71.93% | 25430 3.10% 75.03% | 25799 3.14% 78.17% | 25685 3.13% 81.30% | 25362 3.09% 84.39% | 25641 3.13% 87.52% | 25676 3.13% 90.65% | 25658 3.13% 93.78% | 25720 3.14% 96.91% | 25328 3.09% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 820394 # Number of accesses per bank
|
||||
|
||||
system.cpu0.num_reads 99553 # number of read accesses completed
|
||||
system.cpu0.num_writes 54274 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
|
|
@ -84,5 +102,395 @@ system.cpu6.num_copies 0 # nu
|
|||
system.cpu7.num_reads 99277 # number of read accesses completed
|
||||
system.cpu7.num_writes 53851 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.ruby.l1_cntrl0.Load | 50249 12.48% 12.48% | 50370 12.51% 24.99% | 49923 12.40% 37.38% | 50235 12.47% 49.86% | 50375 12.51% 62.37% | 50577 12.56% 74.93% | 50611 12.57% 87.49% | 50361 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 402701
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 27052 12.46% 12.46% | 27339 12.59% 25.05% | 27175 12.52% 37.57% | 27153 12.51% 50.08% | 27079 12.47% 62.55% | 26983 12.43% 74.98% | 27113 12.49% 87.47% | 27205 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 217099
|
||||
|
||||
system.ruby.l1_cntrl0.L1_Replacement | 9611009 12.51% 12.51% | 9602265 12.49% 25.00% | 9618315 12.51% 37.51% | 9608777 12.50% 50.02% | 9608029 12.50% 62.52% | 9605100 12.50% 75.02% | 9598595 12.49% 87.50% | 9603783 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement::total 76855873
|
||||
|
||||
system.ruby.l1_cntrl0.Own_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.Own_GETX::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETX | 395 12.44% 12.44% | 352 11.09% 23.53% | 364 11.47% 35.00% | 433 13.64% 48.65% | 393 12.38% 61.03% | 374 11.78% 72.81% | 406 12.79% 85.60% | 457 14.40% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETX::total 3174
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETS | 764 13.27% 13.27% | 770 13.37% 26.64% | 739 12.83% 39.48% | 739 12.83% 52.31% | 692 12.02% 64.33% | 715 12.42% 76.75% | 690 11.98% 88.73% | 649 11.27% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETS::total 5758
|
||||
|
||||
system.ruby.l1_cntrl0.Inv | 6 31.58% 31.58% | 3 15.79% 47.37% | 0 0.00% 47.37% | 3 15.79% 63.16% | 2 10.53% 73.68% | 1 5.26% 78.95% | 3 15.79% 94.74% | 1 5.26% 100.00%
|
||||
system.ruby.l1_cntrl0.Inv::total 19
|
||||
|
||||
system.ruby.l1_cntrl0.Ack | 376 12.52% 12.52% | 376 12.52% 25.03% | 382 12.72% 37.75% | 351 11.68% 49.43% | 372 12.38% 61.82% | 350 11.65% 73.47% | 417 13.88% 87.35% | 380 12.65% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack::total 3004
|
||||
|
||||
system.ruby.l1_cntrl0.Data | 720 12.65% 12.65% | 712 12.51% 25.17% | 716 12.58% 37.75% | 661 11.62% 49.37% | 738 12.97% 62.34% | 721 12.67% 75.01% | 703 12.36% 87.36% | 719 12.64% 100.00%
|
||||
system.ruby.l1_cntrl0.Data::total 5690
|
||||
|
||||
system.ruby.l1_cntrl0.Exclusive_Data | 76548 12.47% 12.47% | 76964 12.54% 25.01% | 76362 12.44% 37.45% | 76663 12.49% 49.94% | 76686 12.49% 62.44% | 76787 12.51% 74.95% | 76960 12.54% 87.49% | 76807 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data::total 613777
|
||||
|
||||
system.ruby.l1_cntrl0.Writeback_Ack | 637 12.77% 12.77% | 632 12.67% 25.44% | 612 12.27% 37.70% | 579 11.61% 49.31% | 639 12.81% 62.12% | 632 12.67% 74.78% | 619 12.41% 87.19% | 639 12.81% 100.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack::total 4989
|
||||
|
||||
system.ruby.l1_cntrl0.Writeback_Ack_Data | 76553 12.47% 12.47% | 76972 12.54% 25.01% | 76401 12.44% 37.45% | 76678 12.49% 49.94% | 76717 12.50% 62.44% | 76818 12.51% 74.95% | 76980 12.54% 87.49% | 76828 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack_Data::total 613947
|
||||
|
||||
system.ruby.l1_cntrl0.Writeback_Nack | 52 14.36% 14.36% | 53 14.64% 29.01% | 49 13.54% 42.54% | 52 14.36% 56.91% | 37 10.22% 67.13% | 44 12.15% 79.28% | 37 10.22% 89.50% | 38 10.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Nack::total 362
|
||||
|
||||
system.ruby.l1_cntrl0.All_acks | 27041 12.46% 12.46% | 27326 12.59% 25.05% | 27165 12.52% 37.57% | 27136 12.51% 50.08% | 27069 12.47% 62.55% | 26960 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.All_acks::total 217000
|
||||
|
||||
system.ruby.l1_cntrl0.Use_Timeout | 76548 12.47% 12.47% | 76964 12.54% 25.01% | 76362 12.44% 37.45% | 76664 12.49% 49.94% | 76686 12.49% 62.44% | 76787 12.51% 74.95% | 76959 12.54% 87.49% | 76807 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Use_Timeout::total 613777
|
||||
|
||||
system.ruby.l1_cntrl0.I.Load | 50230 12.48% 12.48% | 50351 12.51% 24.99% | 49916 12.40% 37.39% | 50192 12.47% 49.86% | 50358 12.51% 62.37% | 50550 12.56% 74.93% | 50559 12.56% 87.49% | 50332 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Load::total 402488
|
||||
|
||||
system.ruby.l1_cntrl0.I.Store | 27042 12.46% 12.46% | 27328 12.59% 25.05% | 27166 12.52% 37.57% | 27136 12.50% 50.08% | 27070 12.47% 62.55% | 26961 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Store::total 217006
|
||||
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement | 70 13.78% 13.78% | 67 13.19% 26.97% | 65 12.80% 39.76% | 64 12.60% 52.36% | 67 13.19% 65.55% | 57 11.22% 76.77% | 62 12.20% 88.98% | 56 11.02% 100.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement::total 508
|
||||
|
||||
system.ruby.l1_cntrl0.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Load::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement | 719 12.65% 12.65% | 712 12.53% 25.18% | 716 12.60% 37.78% | 660 11.61% 49.39% | 736 12.95% 62.34% | 720 12.67% 75.01% | 701 12.34% 87.35% | 719 12.65% 100.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement::total 5683
|
||||
|
||||
system.ruby.l1_cntrl0.S.Inv | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Inv::total 7
|
||||
|
||||
system.ruby.l1_cntrl0.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Store::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.O.L1_Replacement | 50 14.75% 14.75% | 43 12.68% 27.43% | 42 12.39% 39.82% | 40 11.80% 51.62% | 37 10.91% 62.54% | 50 14.75% 77.29% | 34 10.03% 87.32% | 43 12.68% 100.00%
|
||||
system.ruby.l1_cntrl0.O.L1_Replacement::total 339
|
||||
|
||||
system.ruby.l1_cntrl0.O.Fwd_GETS | 0 0.00% 0.00% | 2 33.33% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Fwd_GETS::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.M.Load | 2 8.70% 8.70% | 3 13.04% 21.74% | 2 8.70% 30.43% | 5 21.74% 52.17% | 2 8.70% 60.87% | 5 21.74% 82.61% | 2 8.70% 91.30% | 2 8.70% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Load::total 23
|
||||
|
||||
system.ruby.l1_cntrl0.M.Store | 3 20.00% 20.00% | 0 0.00% 20.00% | 2 13.33% 33.33% | 2 13.33% 46.67% | 3 20.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 5 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 15
|
||||
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement | 49426 12.48% 12.48% | 49555 12.51% 24.98% | 49122 12.40% 37.38% | 49457 12.48% 49.87% | 49545 12.51% 62.37% | 49751 12.56% 74.93% | 49794 12.57% 87.50% | 49535 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement::total 396185
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX | 24 11.88% 11.88% | 29 14.36% 26.24% | 29 14.36% 40.59% | 27 13.37% 53.96% | 27 13.37% 67.33% | 19 9.41% 76.73% | 22 10.89% 87.62% | 25 12.38% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX::total 202
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETS | 50 14.71% 14.71% | 43 12.65% 27.35% | 42 12.35% 39.71% | 41 12.06% 51.76% | 37 10.88% 62.65% | 50 14.71% 77.35% | 34 10.00% 87.35% | 43 12.65% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETS::total 340
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Load | 9 15.79% 15.79% | 8 14.04% 29.82% | 3 5.26% 35.09% | 9 15.79% 50.88% | 7 12.28% 63.16% | 7 12.28% 75.44% | 6 10.53% 85.96% | 8 14.04% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Load::total 57
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Store | 4 12.12% 12.12% | 10 30.30% 42.42% | 2 6.06% 48.48% | 1 3.03% 51.52% | 5 15.15% 66.67% | 7 21.21% 87.88% | 2 6.06% 93.94% | 2 6.06% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Store::total 33
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement | 888542 12.47% 12.47% | 887409 12.46% 24.93% | 886648 12.45% 37.38% | 890208 12.50% 49.88% | 893182 12.54% 62.42% | 893219 12.54% 74.96% | 892511 12.53% 87.49% | 891162 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement::total 7122881
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Fwd_GETX | 14 12.17% 12.17% | 10 8.70% 20.87% | 15 13.04% 33.91% | 16 13.91% 47.83% | 15 13.04% 60.87% | 9 7.83% 68.70% | 19 16.52% 85.22% | 17 14.78% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Fwd_GETX::total 115
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Fwd_GETS | 35 16.83% 16.83% | 22 10.58% 27.40% | 26 12.50% 39.90% | 25 12.02% 51.92% | 14 6.73% 58.65% | 29 13.94% 72.60% | 32 15.38% 87.98% | 25 12.02% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Fwd_GETS::total 208
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Use_Timeout | 49503 12.48% 12.48% | 49628 12.51% 24.99% | 49195 12.40% 37.39% | 49527 12.48% 49.87% | 49612 12.50% 62.37% | 49820 12.56% 74.93% | 49850 12.56% 87.50% | 49609 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_Timeout::total 396744
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Load | 3 17.65% 17.65% | 3 17.65% 35.29% | 0 0.00% 35.29% | 4 23.53% 58.82% | 3 17.65% 76.47% | 0 0.00% 76.47% | 3 17.65% 94.12% | 1 5.88% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Load::total 17
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 3 42.86% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Store::total 7
|
||||
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement | 27003 12.46% 12.46% | 27298 12.59% 25.05% | 27133 12.52% 37.57% | 27103 12.50% 50.08% | 27039 12.47% 62.55% | 26929 12.42% 74.97% | 27071 12.49% 87.46% | 27171 12.54% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement::total 216747
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Fwd_GETX | 9 10.11% 10.11% | 7 7.87% 17.98% | 14 15.73% 33.71% | 11 12.36% 46.07% | 11 12.36% 58.43% | 13 14.61% 73.03% | 10 11.24% 84.27% | 14 15.73% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Fwd_GETX::total 89
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Fwd_GETS | 36 17.14% 17.14% | 31 14.76% 31.90% | 22 10.48% 42.38% | 25 11.90% 54.29% | 27 12.86% 67.14% | 24 11.43% 78.57% | 28 13.33% 91.90% | 17 8.10% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Fwd_GETS::total 210
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Load | 4 14.81% 14.81% | 5 18.52% 33.33% | 2 7.41% 40.74% | 5 18.52% 59.26% | 1 3.70% 62.96% | 3 11.11% 74.07% | 4 14.81% 88.89% | 3 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Load::total 27
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Store | 2 16.67% 16.67% | 1 8.33% 25.00% | 2 16.67% 41.67% | 1 8.33% 50.00% | 0 0.00% 50.00% | 2 16.67% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store::total 12
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement | 503603 12.54% 12.54% | 505001 12.58% 25.12% | 504191 12.56% 37.68% | 503264 12.54% 50.22% | 498638 12.42% 62.64% | 499252 12.44% 75.08% | 498871 12.43% 87.50% | 501742 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement::total 4014562
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Fwd_GETX | 8 10.67% 10.67% | 6 8.00% 18.67% | 8 10.67% 29.33% | 14 18.67% 48.00% | 9 12.00% 60.00% | 11 14.67% 74.67% | 5 6.67% 81.33% | 14 18.67% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Fwd_GETX::total 75
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Fwd_GETS | 20 17.54% 17.54% | 15 13.16% 30.70% | 9 7.89% 38.60% | 19 16.67% 55.26% | 19 16.67% 71.93% | 12 10.53% 82.46% | 18 15.79% 98.25% | 2 1.75% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Fwd_GETS::total 114
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Use_Timeout | 27045 12.46% 12.46% | 27336 12.60% 25.06% | 27167 12.52% 37.57% | 27137 12.50% 50.08% | 27074 12.47% 62.55% | 26967 12.43% 74.98% | 27109 12.49% 87.47% | 27198 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_Timeout::total 217033
|
||||
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement | 2854379 12.51% 12.51% | 2860141 12.54% 25.05% | 2888247 12.66% 37.71% | 2844877 12.47% 50.18% | 2844320 12.47% 62.65% | 2831082 12.41% 75.06% | 2837633 12.44% 87.49% | 2852830 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement::total 22813509
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Ack | 374 12.57% 12.57% | 373 12.54% 25.11% | 380 12.77% 37.88% | 346 11.63% 49.51% | 370 12.44% 61.95% | 346 11.63% 73.58% | 410 13.78% 87.36% | 376 12.64% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Ack::total 2975
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data | 27041 12.46% 12.46% | 27326 12.59% 25.05% | 27165 12.52% 37.57% | 27135 12.50% 50.08% | 27069 12.47% 62.55% | 26960 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data::total 216999
|
||||
|
||||
system.ruby.l1_cntrl0.OM.L1_Replacement | 15977 12.61% 12.61% | 16015 12.64% 25.26% | 16094 12.71% 37.97% | 15787 12.46% 50.43% | 15663 12.37% 62.80% | 15820 12.49% 75.29% | 15975 12.61% 87.90% | 15323 12.10% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.L1_Replacement::total 126654
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Own_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Own_GETX::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Ack | 2 6.90% 6.90% | 3 10.34% 17.24% | 2 6.90% 24.14% | 5 17.24% 41.38% | 2 6.90% 48.28% | 4 13.79% 62.07% | 7 24.14% 86.21% | 4 13.79% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Ack::total 29
|
||||
|
||||
system.ruby.l1_cntrl0.OM.All_acks | 27041 12.46% 12.46% | 27326 12.59% 25.05% | 27165 12.52% 37.57% | 27136 12.51% 50.08% | 27069 12.47% 62.55% | 26960 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.All_acks::total 217000
|
||||
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement | 5271240 12.50% 12.50% | 5256024 12.47% 24.97% | 5246057 12.44% 37.41% | 5277317 12.52% 49.93% | 5278802 12.52% 62.45% | 5288220 12.54% 75.00% | 5275943 12.51% 87.51% | 5265202 12.49% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement::total 42158805
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data | 720 12.65% 12.65% | 712 12.51% 25.17% | 716 12.58% 37.75% | 661 11.62% 49.37% | 738 12.97% 62.34% | 721 12.67% 75.01% | 703 12.36% 87.36% | 719 12.64% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data::total 5690
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data | 49507 12.48% 12.48% | 49638 12.51% 24.99% | 49197 12.40% 37.39% | 49528 12.48% 49.87% | 49617 12.50% 62.37% | 49827 12.56% 74.93% | 49853 12.56% 87.50% | 49611 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data::total 396778
|
||||
|
||||
system.ruby.l1_cntrl0.SI.Fwd_GETS | 2 25.00% 25.00% | 0 0.00% 25.00% | 3 37.50% 62.50% | 1 12.50% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.SI.Fwd_GETS::total 8
|
||||
|
||||
system.ruby.l1_cntrl0.SI.Inv | 5 41.67% 41.67% | 3 25.00% 66.67% | 0 0.00% 66.67% | 2 16.67% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 8.33% 91.67% | 1 8.33% 100.00%
|
||||
system.ruby.l1_cntrl0.SI.Inv::total 12
|
||||
|
||||
system.ruby.l1_cntrl0.SI.Writeback_Ack | 637 12.77% 12.77% | 632 12.67% 25.44% | 612 12.27% 37.70% | 579 11.61% 49.31% | 639 12.81% 62.12% | 632 12.67% 74.78% | 619 12.41% 87.19% | 639 12.81% 100.00%
|
||||
system.ruby.l1_cntrl0.SI.Writeback_Ack::total 4989
|
||||
|
||||
system.ruby.l1_cntrl0.SI.Writeback_Ack_Data | 77 11.29% 11.29% | 77 11.29% 22.58% | 104 15.25% 37.83% | 79 11.58% 49.41% | 97 14.22% 63.64% | 88 12.90% 76.54% | 81 11.88% 88.42% | 79 11.58% 100.00%
|
||||
system.ruby.l1_cntrl0.SI.Writeback_Ack_Data::total 682
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Fwd_GETX | 3 25.00% 25.00% | 1 8.33% 33.33% | 1 8.33% 41.67% | 0 0.00% 41.67% | 2 16.67% 58.33% | 1 8.33% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Fwd_GETX::total 12
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Fwd_GETS | 1 5.00% 5.00% | 5 25.00% 30.00% | 2 10.00% 40.00% | 0 0.00% 40.00% | 4 20.00% 60.00% | 2 10.00% 70.00% | 5 25.00% 95.00% | 1 5.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Fwd_GETS::total 20
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Writeback_Ack_Data | 667 12.88% 12.88% | 694 13.40% 26.28% | 675 13.03% 39.31% | 668 12.90% 52.21% | 624 12.05% 64.26% | 647 12.49% 76.75% | 602 11.62% 88.38% | 602 11.62% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Writeback_Ack_Data::total 5179
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Writeback_Nack | 45 13.04% 13.04% | 49 14.20% 27.25% | 49 14.20% 41.45% | 49 14.20% 55.65% | 36 10.43% 66.09% | 44 12.75% 78.84% | 36 10.43% 89.28% | 37 10.72% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Writeback_Nack::total 345
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Load | 1 1.14% 1.14% | 0 0.00% 1.14% | 0 0.00% 1.14% | 19 21.59% 22.73% | 4 4.55% 27.27% | 12 13.64% 40.91% | 37 42.05% 82.95% | 15 17.05% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Load::total 88
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Store | 1 4.00% 4.00% | 0 0.00% 4.00% | 2 8.00% 12.00% | 9 36.00% 48.00% | 1 4.00% 52.00% | 12 48.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Store::total 25
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Fwd_GETX | 337 12.57% 12.57% | 299 11.15% 23.72% | 297 11.08% 34.80% | 365 13.61% 48.41% | 329 12.27% 60.69% | 321 11.97% 72.66% | 347 12.94% 85.60% | 386 14.40% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Fwd_GETX::total 2681
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Fwd_GETS | 620 12.78% 12.78% | 652 13.44% 26.22% | 634 13.07% 39.28% | 628 12.94% 52.23% | 589 12.14% 64.37% | 598 12.32% 76.69% | 571 11.77% 88.46% | 560 11.54% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Fwd_GETS::total 4852
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack_Data | 75471 12.47% 12.47% | 75902 12.54% 25.00% | 75324 12.44% 37.45% | 75567 12.48% 49.93% | 75666 12.50% 62.43% | 75761 12.51% 74.94% | 75947 12.54% 87.49% | 75760 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack_Data::total 605398
|
||||
|
||||
system.ruby.l1_cntrl0.II.Writeback_Ack_Data | 338 12.57% 12.57% | 299 11.12% 23.70% | 298 11.09% 34.78% | 364 13.54% 48.33% | 330 12.28% 60.60% | 322 11.98% 72.58% | 350 13.02% 85.60% | 387 14.40% 100.00%
|
||||
system.ruby.l1_cntrl0.II.Writeback_Ack_Data::total 2688
|
||||
|
||||
system.ruby.l1_cntrl0.II.Writeback_Nack | 7 41.18% 41.18% | 4 23.53% 64.71% | 0 0.00% 64.71% | 3 17.65% 82.35% | 1 5.88% 88.24% | 0 0.00% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00%
|
||||
system.ruby.l1_cntrl0.II.Writeback_Nack::total 17
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GETS 504389 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 272648 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTO 1593 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 699797 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTS_only 21673 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTS 495 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.All_Acks 211934 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data 212372 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data_Exclusive 392755 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBCLEANDATA 393957 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBDIRTYDATA 217301 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Ack 604645 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Unblock 13367 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 613777 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 690149 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 393211 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 211938 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILS.L1_GETS 8 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILS.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILS.L1_PUTS_only 666 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILS.L1_PUTS 16 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_GETS 5402 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_GETX 2972 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_PUTO 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_PUTX 608084 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_PUTS 12 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOX.L1_GETS 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOX.L1_GETX 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOX.L1_PUTO 498 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOX.L1_PUTX 345 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSX.L1_GETS 22 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSX.L1_GETX 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSX.L1_PUTO 184 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSX.L1_PUTX 4499 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSX.L1_PUTS_only 504 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSX.L1_PUTS 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETS 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L2_Replacement 675 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSX.L1_GETS 20 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSX.L1_GETX 7 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSX.L1_PUTS_only 4435 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSX.L1_PUTS 23 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSX.L2_Replacement 239 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SLS.L1_PUTS_only 16 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SLS.L2_Replacement 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 3814 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 2075 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_PUTX 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 604433 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.L1_GETS 53 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.L1_GETX 42 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.L1_PUTO 826 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.L1_PUTX 4960 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.L1_WBCLEANDATA 389 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.L1_WBDIRTYDATA 109 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOXW.Unblock 504 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_GETS 138 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_GETX 87 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_PUTO 8 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_PUTX 63 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_PUTS_only 14625 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_PUTS 56 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_WBCLEANDATA 3112 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.L1_WBDIRTYDATA 1569 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILOSXW.Unblock 13 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILSW.L1_PUTS 78 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILSW.L1_WBCLEANDATA 16 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IW.L1_GETS 53 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IW.L1_GETX 14 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IW.L1_WBCLEANDATA 666 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SW.Unblock 16 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SW.L2_Replacement 297 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OXW.L1_GETS 163 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OXW.L1_GETX 69 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OXW.Unblock 4435 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OXW.L2_Replacement 33711 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSXW.L1_PUTS 119 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSXW.Unblock 23 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSXW.L2_Replacement 225 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_GETS 23787 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_GETX 12537 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_PUTX 5410 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_PUTS 21 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 389774 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 215623 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.Unblock 2686 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLS.L1_PUTS_only 50 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLS.Unblock 8 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOX.L1_PUTX 15 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOX.L1_PUTS_only 35 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOX.Unblock 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOX.Exclusive_Unblock 7 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.L1_GETS 550 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.L1_GETX 221 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.L1_PUTO 75 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.L1_PUTX 75456 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.L1_PUTS 40 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.Unblock 5192 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOXX.Exclusive_Unblock 3184 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOSX.L1_PUTX 175 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOSX.L1_PUTS_only 115 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLOSX.Unblock 22 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLXO.L1_PUTX 134 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLXO.L1_PUTS_only 81 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IFLXO.Exclusive_Unblock 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.L1_GETS 49660 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.L1_GETX 26581 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.L1_PUTX 426 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.L1_PUTS 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Data 438 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Data_Exclusive 392755 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Unblock 438 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 392753 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGM.L1_GETS 19915 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGM.L1_GETX 11908 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGM.Data 211933 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMLS.L1_PUTS_only 23 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMLS.Data 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.L1_GETS 4990 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.L1_GETX 3032 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.L1_PUTX 215 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.L1_PUTS_only 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.All_Acks 211934 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 211933 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.L1_GETS 41 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.L1_GETX 46 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.L1_PUTX 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.Exclusive_Unblock 2075 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.Unblock 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement 127 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.L1_GETS 101 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.L1_GETX 49 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.L1_PUTX 7 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.Exclusive_Unblock 3814 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.L2_Replacement 50262 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSXS.L1_PUTS_only 107 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSXS.Unblock 20 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSXS.L2_Replacement 174 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.L1_GETS 2451 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.L1_GETX 1055 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.Writeback_Ack 604406 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSI.L1_PUTS_only 1011 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSI.L1_PUTS 108 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OLSI.Writeback_Ack 239 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 211949 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 393220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 604433 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTO_SHARERS 239 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Last_Unblock 438 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Exclusive_Unblock 604686 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Clean_Writeback 389402 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Dirty_Writeback 215243 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 605138 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 215243 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 211704 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETS 392773 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Memory_Ack 213458 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.S.GETX 236 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.S.GETS 438 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.S.Memory_Ack 82 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 604433 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTO_SHARERS 239 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Exclusive_Unblock 392753 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Data 392763 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Ack 1125 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.SS.Last_Unblock 438 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.SS.Memory_Data 438 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Exclusive_Unblock 211933 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Memory_Data 211937 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Memory_Ack 578 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.GETX 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.GETS 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Clean_Writeback 389245 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Dirty_Writeback 215161 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MIS.Clean_Writeback 157 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MIS.Dirty_Writeback 82 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Apr/09/2013 02:12:00
|
||||
Real time: Jun/08/2013 14:16:39
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 161
|
||||
Elapsed_time_in_minutes: 2.68333
|
||||
Elapsed_time_in_hours: 0.0447222
|
||||
Elapsed_time_in_days: 0.00186343
|
||||
Elapsed_time_in_seconds: 102
|
||||
Elapsed_time_in_minutes: 1.7
|
||||
Elapsed_time_in_hours: 0.0283333
|
||||
Elapsed_time_in_days: 0.00118056
|
||||
|
||||
Virtual_time_in_seconds: 160.82
|
||||
Virtual_time_in_minutes: 2.68033
|
||||
Virtual_time_in_hours: 0.0446722
|
||||
Virtual_time_in_days: 0.00186134
|
||||
Virtual_time_in_seconds: 102.3
|
||||
Virtual_time_in_minutes: 1.705
|
||||
Virtual_time_in_hours: 0.0284167
|
||||
Virtual_time_in_days: 0.00118403
|
||||
|
||||
Ruby_current_time: 6151475
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 6151475
|
||||
|
||||
mbytes_resident: 65.0859
|
||||
mbytes_total: 244.512
|
||||
resident_ratio: 0.266187
|
||||
|
||||
ruby_cycles_executed: [ 6151476 6151476 6151476 6151476 6151476 6151476 6151476 6151476 ]
|
||||
mbytes_resident: 73.043
|
||||
mbytes_total: 285.676
|
||||
resident_ratio: 0.255712
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -69,7 +67,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -88,13 +85,13 @@ Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 160
|
||||
user_time: 102
|
||||
system_time: 0
|
||||
page_reclaims: 17197
|
||||
page_faults: 10
|
||||
page_reclaims: 10796
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 1400
|
||||
block_outputs: 312
|
||||
block_inputs: 0
|
||||
block_outputs: 280
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -399,805 +396,3 @@ links_utilized_percent_switch_10: 17.6719
|
|||
outgoing_messages_switch_10_link_9_Writeback_Control: 377581 3020648 [ 0 0 0 0 377581 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Persistent_Control: 259692 2077536 [ 0 0 0 259692 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50331 49967 50254 50183 50017 50259 50136 50016 ] 401163
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [26960 27312 26841 26622 26950 27007 27203 26930 ] 215825
|
||||
Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
L1_Replacement [1368057 1367643 1363908 1358410 1362554 1365525 1369124 1360777 ] 10915998
|
||||
Data_Shared [236 219 237 210 242 233 202 233 ] 1812
|
||||
Data_Owner [73 74 52 50 71 66 41 52 ] 479
|
||||
Data_All_Tokens [80940 80743 80630 80297 80401 80744 80888 80464 ] 645107
|
||||
Ack [1 0 3 0 3 2 4 1 ] 14
|
||||
Ack_All_Tokens [1 1 0 1 1 0 0 1 ] 5
|
||||
Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
Transient_Local_GETX [188823 188465 188937 189155 188828 188776 188573 188847 ] 1510404
|
||||
Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
Transient_Local_GETS [350731 351096 350807 350881 351048 350805 350930 351050 ] 2807348
|
||||
Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
Transient_Local_GETS_Last_Token [2 0 1 4 0 1 0 1 ] 9
|
||||
Persistent_GETX [40243 40235 40237 40452 40236 40319 40323 40294 ] 322339
|
||||
Persistent_GETS [74022 73973 73853 73992 74071 73914 74014 74024 ] 591863
|
||||
Persistent_GETS_Last_Token [0 0 1 1 1 0 0 0 ] 3
|
||||
Own_Lock_or_Unlock [145427 145484 145601 145247 145384 145459 145355 145374 ] 1163331
|
||||
Request_Timeout [60159 59656 60277 60879 60010 60642 60033 58941 ] 480597
|
||||
Use_TimeoutStarverX [5 4 12 11 13 10 18 16 ] 89
|
||||
Use_TimeoutStarverS [6 15 16 13 14 25 24 25 ] 138
|
||||
Use_TimeoutNoStarvers [76982 76971 76777 76512 76634 76926 77048 76616 ] 614466
|
||||
Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [50234 49878 50162 50102 49920 50179 50054 49912 ] 400441
|
||||
NP Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Store [26908 27274 26779 26582 26907 26962 27158 26896 ] 215466
|
||||
NP Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Data_Shared [15 7 5 4 11 6 6 5 ] 59
|
||||
NP Data_Owner [21 15 12 10 18 16 11 12 ] 115
|
||||
NP Data_All_Tokens [3905 3708 3801 3744 3722 3775 3791 3803 ] 30249
|
||||
NP Ack [0 0 1 0 0 0 1 0 ] 2
|
||||
NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Transient_Local_GETX [188213 187862 188356 188542 188229 188157 187989 188206 ] 1505554
|
||||
NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Transient_Local_GETS [349628 349983 349669 349728 349922 349655 349776 349964 ] 2798325
|
||||
NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Own_Lock_or_Unlock [126885 126871 126751 126905 126881 126869 126992 126955 ] 1015109
|
||||
|
||||
I Load [0 0 0 0 0 0 1 0 ] 1
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
I Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
I L1_Replacement [183 170 174 180 173 164 159 191 ] 1394
|
||||
I Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
I Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
||||
I Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
I Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
I Transient_Local_GETX [0 0 0 1 0 0 0 0 ] 1
|
||||
I Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
I Transient_Local_GETS [0 0 0 2 0 1 0 0 ] 3
|
||||
I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
I Persistent_GETX [0 0 0 0 1 0 0 0 ] 1
|
||||
I Persistent_GETS [1 1 0 1 0 0 0 0 ] 3
|
||||
I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
I Own_Lock_or_Unlock [0 1 0 0 1 0 0 0 ] 2
|
||||
|
||||
S Load [0 0 1 0 0 0 0 0 ] 1
|
||||
S Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
S Store [0 0 0 0 0 0 0 0 ] 0
|
||||
S Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
S L1_Replacement [249 252 274 244 272 281 241 271 ] 2084
|
||||
S Data_Shared [1 0 2 0 1 0 0 1 ] 5
|
||||
S Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
S Data_All_Tokens [0 1 0 0 0 0 0 0 ] 1
|
||||
S Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
S Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
S Transient_Local_GETX [1 2 1 1 2 0 0 1 ] 8
|
||||
S Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
S Transient_Local_GETS [0 0 0 0 1 0 0 0 ] 1
|
||||
S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
S Transient_Local_GETS_Last_Token [2 0 1 4 0 1 0 1 ] 9
|
||||
S Persistent_GETX [1 0 0 0 0 0 0 0 ] 1
|
||||
S Persistent_GETS [0 0 0 0 0 1 1 0 ] 2
|
||||
S Persistent_GETS_Last_Token [0 0 1 1 1 0 0 0 ] 3
|
||||
S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
O Load [0 0 0 0 0 0 0 0 ] 0
|
||||
O Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
O Store [0 0 0 0 0 0 0 0 ] 0
|
||||
O Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
O L1_Replacement [133 127 116 134 132 145 111 121 ] 1019
|
||||
O Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
O Data_All_Tokens [1 0 0 0 0 0 0 1 ] 2
|
||||
O Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
O Ack_All_Tokens [0 0 0 0 1 0 0 0 ] 1
|
||||
O Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
O Transient_Local_GETX [0 1 0 0 0 1 0 0 ] 2
|
||||
O Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
O Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
O Persistent_GETS [0 1 0 1 0 0 0 0 ] 2
|
||||
O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
O Own_Lock_or_Unlock [12 15 17 13 12 13 10 6 ] 98
|
||||
|
||||
M Load [5 2 3 5 5 3 8 10 ] 41
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [3 2 5 4 3 4 0 0 ] 21
|
||||
M Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
M L1_Replacement [49847 49500 49774 49713 49519 49733 49702 49527 ] 397315
|
||||
M Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
M Transient_Local_GETX [50 36 52 40 46 55 33 55 ] 367
|
||||
M Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
M Transient_Local_GETS [83 71 76 96 80 96 81 84 ] 667
|
||||
M Persistent_GETX [25 26 14 21 21 13 18 11 ] 149
|
||||
M Persistent_GETS [27 31 33 32 36 38 28 29 ] 254
|
||||
M Own_Lock_or_Unlock [1187 1229 1293 1200 1221 1249 1131 1186 ] 9696
|
||||
|
||||
MM Load [1 5 2 7 3 2 3 1 ] 24
|
||||
MM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Store [5 1 1 1 0 3 1 3 ] 15
|
||||
MM Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
MM L1_Replacement [26851 27209 26736 26508 26847 26914 27102 26811 ] 214978
|
||||
MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Transient_Local_GETX [31 33 27 28 17 21 25 28 ] 210
|
||||
MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Transient_Local_GETS [45 36 37 41 49 33 36 42 ] 319
|
||||
MM Persistent_GETX [11 11 10 17 10 10 8 7 ] 84
|
||||
MM Persistent_GETS [12 17 17 14 9 12 15 22 ] 118
|
||||
MM Own_Lock_or_Unlock [712 667 685 670 668 648 636 641 ] 5327
|
||||
|
||||
M_W Load [2 4 5 3 3 4 3 4 ] 28
|
||||
M_W Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W Store [1 2 0 0 1 2 2 1 ] 9
|
||||
M_W Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W L1_Replacement [291266 289622 289644 290259 288045 288216 288197 287895 ] 2313144
|
||||
M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W Transient_Local_GETX [42 27 30 37 39 45 33 39 ] 292
|
||||
M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W Transient_Local_GETS [66 79 75 88 63 60 78 60 ] 569
|
||||
M_W Persistent_GETX [3 4 4 5 4 6 8 8 ] 42
|
||||
M_W Persistent_GETS [5 11 11 4 7 15 15 17 ] 85
|
||||
M_W Own_Lock_or_Unlock [469 479 514 489 496 466 481 459 ] 3853
|
||||
M_W Use_TimeoutStarverX [4 4 5 6 5 7 11 10 ] 52
|
||||
M_W Use_TimeoutStarverS [5 11 12 6 8 17 17 17 ] 93
|
||||
M_W Use_TimeoutNoStarvers [50035 49666 49954 49907 49705 49940 49862 49706 ] 398775
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MM_W Load [5 1 0 2 3 5 1 1 ] 18
|
||||
MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W Store [2 0 0 0 2 2 1 1 ] 8
|
||||
MM_W Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W L1_Replacement [155942 158074 153918 152634 158304 157087 158031 155857 ] 1249847
|
||||
MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W Transient_Local_GETX [23 18 18 26 23 21 20 27 ] 176
|
||||
MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W Transient_Local_GETS [30 45 31 43 33 40 44 43 ] 309
|
||||
MM_W Persistent_GETX [1 0 6 4 7 2 7 6 ] 33
|
||||
MM_W Persistent_GETS [1 3 3 7 6 7 7 8 ] 42
|
||||
MM_W Own_Lock_or_Unlock [292 270 253 231 270 272 278 235 ] 2101
|
||||
MM_W Use_TimeoutStarverX [1 0 7 5 8 3 7 6 ] 37
|
||||
MM_W Use_TimeoutStarverS [1 4 4 7 6 8 7 8 ] 45
|
||||
MM_W Use_TimeoutNoStarvers [26947 27305 26823 26605 26929 26986 27186 26910 ] 215691
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
IM L1_Replacement [293340 295809 291989 287885 295320 295503 296204 292704 ] 2348754
|
||||
IM Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Data_Owner [1 1 0 1 0 0 0 2 ] 5
|
||||
IM Data_All_Tokens [26946 27305 26829 26615 26941 26992 27198 26921 ] 215747
|
||||
IM Ack [1 0 1 0 2 2 3 1 ] 10
|
||||
IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Transient_Local_GETX [90 84 90 94 93 87 89 96 ] 723
|
||||
IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Transient_Local_GETS [147 144 177 153 146 154 150 165 ] 1236
|
||||
IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Persistent_GETX [29 27 22 27 26 33 22 19 ] 205
|
||||
IM Persistent_GETS [36 39 50 42 48 53 57 63 ] 388
|
||||
IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Own_Lock_or_Unlock [5483 5506 5529 5327 5492 5408 5402 5471 ] 43618
|
||||
IM Request_Timeout [20923 21057 21290 20719 21245 21018 20732 20087 ] 167071
|
||||
|
||||
SM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Request_Timeout [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
OM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
OM L1_Replacement [0 0 0 1 0 0 0 0 ] 1
|
||||
OM Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Data_All_Tokens [0 0 0 0 0 0 0 1 ] 1
|
||||
OM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Ack_All_Tokens [1 1 0 1 0 0 0 1 ] 4
|
||||
OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Own_Lock_or_Unlock [0 0 0 1 0 0 0 0 ] 1
|
||||
OM Request_Timeout [0 0 0 1 0 0 0 0 ] 1
|
||||
|
||||
IS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
IS L1_Replacement [548020 544678 548767 548504 541488 544959 546694 544234 ] 4367344
|
||||
IS Data_Shared [219 212 230 206 230 226 196 226 ] 1745
|
||||
IS Data_Owner [51 58 40 39 53 50 30 38 ] 359
|
||||
IS Data_All_Tokens [50045 49683 49970 49916 49717 49963 49887 49732 ] 398913
|
||||
IS Ack [0 0 1 0 1 0 0 0 ] 2
|
||||
IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Transient_Local_GETX [152 168 140 160 153 161 153 166 ] 1253
|
||||
IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Transient_Local_GETS [287 298 300 291 322 311 302 273 ] 2384
|
||||
IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Persistent_GETX [36 37 47 56 49 57 59 56 ] 397
|
||||
IS Persistent_GETS [86 112 92 95 105 100 104 97 ] 791
|
||||
IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Own_Lock_or_Unlock [9989 10016 10115 9985 9893 10088 9969 9961 ] 80016
|
||||
IS Request_Timeout [38867 38204 38667 39766 38271 39197 38932 38452 ] 310356
|
||||
|
||||
I_L Load [84 77 81 64 83 66 66 88 ] 609
|
||||
I_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Store [41 33 56 35 37 34 41 29 ] 306
|
||||
I_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L L1_Replacement [206 148 234 329 249 203 258 317 ] 1944
|
||||
I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Data_All_Tokens [41 45 23 18 18 8 7 4 ] 164
|
||||
I_L Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Transient_Local_GETX [221 233 222 225 225 228 230 227 ] 1811
|
||||
I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Transient_Local_GETS [445 439 441 435 432 455 463 416 ] 3526
|
||||
I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Persistent_GETX [40137 40125 40121 40304 40099 40175 40167 40156 ] 321284
|
||||
I_L Persistent_GETS [73854 73741 73628 73761 73818 73632 73718 73704 ] 589856
|
||||
I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
I_L Own_Lock_or_Unlock [57 63 57 71 60 54 66 65 ] 493
|
||||
|
||||
S_L Load [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Store [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L L1_Replacement [42 35 64 55 24 80 47 56 ] 403
|
||||
S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Transient_Local_GETX [0 0 0 1 0 0 0 0 ] 1
|
||||
S_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Persistent_GETS [0 4 7 6 5 17 10 14 ] 63
|
||||
S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
S_L Own_Lock_or_Unlock [32 43 46 40 45 56 46 46 ] 354
|
||||
|
||||
IM_L Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L L1_Replacement [616 650 788 576 691 852 843 772 ] 5788
|
||||
IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Data_All_Tokens [1 1 5 1 1 3 0 0 ] 12
|
||||
IM_L Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Transient_Local_GETX [0 0 0 0 1 0 1 1 ] 3
|
||||
IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Transient_Local_GETS [0 1 1 2 0 0 0 1 ] 5
|
||||
IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_L Persistent_GETX [0 3 2 4 10 10 10 6 ] 45
|
||||
IM_L Persistent_GETS [0 2 7 11 13 15 23 29 ] 100
|
||||
IM_L Own_Lock_or_Unlock [105 98 123 103 110 117 120 111 ] 887
|
||||
IM_L Request_Timeout [92 153 130 128 153 194 147 151 ] 1148
|
||||
|
||||
SM_L Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_L Request_Timeout [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS_L Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L L1_Replacement [1362 1369 1430 1388 1490 1388 1535 2021 ] 11983
|
||||
IS_L Data_Shared [1 0 0 0 0 1 0 1 ] 3
|
||||
IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Data_All_Tokens [1 0 2 3 2 3 5 2 ] 18
|
||||
IS_L Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Transient_Local_GETX [0 1 1 0 0 0 0 1 ] 3
|
||||
IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Transient_Local_GETS [0 0 0 2 0 0 0 2 ] 4
|
||||
IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_L Persistent_GETX [0 2 11 14 9 13 24 25 ] 98
|
||||
IS_L Persistent_GETS [0 11 5 18 24 24 36 41 ] 159
|
||||
IS_L Own_Lock_or_Unlock [204 226 218 212 235 219 224 238 ] 1776
|
||||
IS_L Request_Timeout [277 242 190 265 341 233 222 251 ] 2021
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [401048 ] 401048
|
||||
L1_GETS_Last_Token [3 ] 3
|
||||
L1_GETX [215772 ] 215772
|
||||
L1_INV [1395 ] 1395
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [583206 ] 583206
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [1451 ] 1451
|
||||
Writeback_All_Tokens [613102 ] 613102
|
||||
Writeback_Owned [843 ] 843
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [46049 ] 46049
|
||||
Persistent_GETS [84554 ] 84554
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [129089 ] 129089
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [399363 ] 399363
|
||||
NP L1_GETX [214874 ] 214874
|
||||
NP L1_INV [909 ] 909
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [1386 ] 1386
|
||||
NP Writeback_All_Tokens [581094 ] 581094
|
||||
NP Writeback_Owned [734 ] 734
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [0 ] 0
|
||||
NP Ack [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [128754 ] 128754
|
||||
|
||||
I L1_GETS [2 ] 2
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [0 ] 0
|
||||
I L1_INV [2 ] 2
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [559 ] 559
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [0 ] 0
|
||||
I Writeback_All_Tokens [366 ] 366
|
||||
I Writeback_Owned [2 ] 2
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [3 ] 3
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [1209 ] 1209
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [5 ] 5
|
||||
S Writeback_All_Tokens [176 ] 176
|
||||
S Writeback_Owned [0 ] 0
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Persistent_GETX [2 ] 2
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [13 ] 13
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [3 ] 3
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [1168 ] 1168
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [7 ] 7
|
||||
O Writeback_All_Tokens [633 ] 633
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Persistent_GETX [1 ] 1
|
||||
O Persistent_GETS [6 ] 6
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [1075 ] 1075
|
||||
M L1_GETX [590 ] 590
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [579287 ] 579287
|
||||
M Persistent_GETX [460 ] 460
|
||||
M Persistent_GETS [849 ] 849
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [595 ] 595
|
||||
I_L L1_GETX [304 ] 304
|
||||
I_L L1_INV [484 ] 484
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [982 ] 982
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [53 ] 53
|
||||
I_L Writeback_All_Tokens [30833 ] 30833
|
||||
I_L Writeback_Owned [107 ] 107
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [45586 ] 45586
|
||||
I_L Persistent_GETS [83699 ] 83699
|
||||
I_L Own_Lock_or_Unlock [330 ] 330
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
S_L L1_GETX [0 ] 0
|
||||
S_L L1_INV [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L L2_Replacement [1 ] 1
|
||||
S_L Writeback_Tokens [0 ] 0
|
||||
S_L Writeback_Shared_Data [0 ] 0
|
||||
S_L Writeback_All_Tokens [0 ] 0
|
||||
S_L Writeback_Owned [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [5 ] 5
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 844944
|
||||
memory_reads: 610587
|
||||
memory_writes: 234338
|
||||
memory_refreshes: 42719
|
||||
memory_total_request_delays: 42920765
|
||||
memory_delays_per_request: 50.7972
|
||||
memory_delays_in_input_queue: 577720
|
||||
memory_delays_behind_head_of_bank_queue: 15763537
|
||||
memory_delays_stalled_at_head_of_bank_queue: 26579508
|
||||
memory_stalls_for_bank_busy: 4097613
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 6310315
|
||||
memory_stalls_for_arbitration: 5356376
|
||||
memory_stalls_for_bus: 7372232
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 2122830
|
||||
memory_stalls_for_read_read_turnaround: 1320142
|
||||
accesses_per_bank: 26606 25663 25635 25980 25947 25870 25993 25627 26268 26143 25936 26178 26391 26459 26079 26348 26234 26478 26175 26431 26351 26505 26354 26626 26636 26614 27037 26934 26972 27613 27729 27132
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [255487 ] 255487
|
||||
GETS [476933 ] 476933
|
||||
Lockdown [130603 ] 130603
|
||||
Unlockdown [129089 ] 129089
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [344 ] 344
|
||||
Data_All_Tokens [235610 ] 235610
|
||||
Ack_Owner [694 ] 694
|
||||
Ack_Owner_All_Tokens [375677 ] 375677
|
||||
Tokens [456 ] 456
|
||||
Ack_All_Tokens [3709 ] 3709
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [610582 ] 610582
|
||||
Memory_Ack [234338 ] 234338
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [212118 ] 212118
|
||||
O GETS [394360 ] 394360
|
||||
O Lockdown [2461 ] 2461
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [49 ] 49
|
||||
O Tokens [4 ] 4
|
||||
O Ack_All_Tokens [967 ] 967
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [2212 ] 2212
|
||||
NO GETS [3891 ] 3891
|
||||
NO Lockdown [20370 ] 20370
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [344 ] 344
|
||||
NO Data_All_Tokens [233998 ] 233998
|
||||
NO Ack_Owner [694 ] 694
|
||||
NO Ack_Owner_All_Tokens [375526 ] 375526
|
||||
NO Tokens [248 ] 248
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [852 ] 852
|
||||
L GETS [1708 ] 1708
|
||||
L Lockdown [1080 ] 1080
|
||||
L Unlockdown [129089 ] 129089
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [106 ] 106
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [151 ] 151
|
||||
L Tokens [3 ] 3
|
||||
L DMA_READ [0 ] 0
|
||||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [13301 ] 13301
|
||||
O_W GETS [26689 ] 26689
|
||||
O_W Lockdown [1663 ] 1663
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_W Data_Owner [0 ] 0
|
||||
O_W Data_All_Tokens [1388 ] 1388
|
||||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [201 ] 201
|
||||
O_W Ack_All_Tokens [2722 ] 2722
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [232675 ] 232675
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [6131 ] 6131
|
||||
L_O_W GETS [13880 ] 13880
|
||||
L_O_W Lockdown [30 ] 30
|
||||
L_O_W Unlockdown [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
L_O_W Data_All_Tokens [69 ] 69
|
||||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [4123 ] 4123
|
||||
L_O_W Memory_Ack [1663 ] 1663
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_NO_W GETX [5886 ] 5886
|
||||
L_NO_W GETS [10623 ] 10623
|
||||
L_NO_W Lockdown [398 ] 398
|
||||
L_NO_W Unlockdown [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_NO_W Data_Owner [0 ] 0
|
||||
L_NO_W Data_All_Tokens [0 ] 0
|
||||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [104596 ] 104596
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L_W GETX [0 ] 0
|
||||
DR_L_W GETS [0 ] 0
|
||||
DR_L_W Lockdown [0 ] 0
|
||||
DR_L_W Unlockdown [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L_W Data_Owner [0 ] 0
|
||||
DR_L_W Data_All_Tokens [0 ] 0
|
||||
DR_L_W Ack_Owner [0 ] 0
|
||||
DR_L_W Tokens [0 ] 0
|
||||
DR_L_W Ack_All_Tokens [0 ] 0
|
||||
DR_L_W Request_Timeout [0 ] 0
|
||||
DR_L_W Memory_Data [0 ] 0
|
||||
DR_L_W DMA_READ [0 ] 0
|
||||
DR_L_W DMA_WRITE [0 ] 0
|
||||
DR_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L_W GETX [0 ] 0
|
||||
DW_L_W GETS [0 ] 0
|
||||
DW_L_W Lockdown [0 ] 0
|
||||
DW_L_W Unlockdown [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L_W Data_Owner [0 ] 0
|
||||
DW_L_W Data_All_Tokens [0 ] 0
|
||||
DW_L_W Ack_Owner [0 ] 0
|
||||
DW_L_W Tokens [0 ] 0
|
||||
DW_L_W Ack_All_Tokens [0 ] 0
|
||||
DW_L_W Request_Timeout [0 ] 0
|
||||
DW_L_W Memory_Ack [0 ] 0
|
||||
DW_L_W DMA_READ [0 ] 0
|
||||
DW_L_W DMA_WRITE [0 ] 0
|
||||
DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_W GETX [14987 ] 14987
|
||||
NO_W GETS [25782 ] 25782
|
||||
NO_W Lockdown [104601 ] 104601
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_W Data_Owner [0 ] 0
|
||||
NO_W Data_All_Tokens [0 ] 0
|
||||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [20 ] 20
|
||||
NO_W Memory_Data [501863 ] 501863
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW_W GETX [0 ] 0
|
||||
O_DW_W GETS [0 ] 0
|
||||
O_DW_W Lockdown [0 ] 0
|
||||
O_DW_W Unlockdown [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW_W Data_Owner [0 ] 0
|
||||
O_DW_W Data_All_Tokens [0 ] 0
|
||||
O_DW_W Ack_Owner [0 ] 0
|
||||
O_DW_W Tokens [0 ] 0
|
||||
O_DW_W Ack_All_Tokens [0 ] 0
|
||||
O_DW_W Request_Timeout [0 ] 0
|
||||
O_DW_W Memory_Ack [0 ] 0
|
||||
O_DW_W DMA_READ [0 ] 0
|
||||
O_DW_W DMA_WRITE [0 ] 0
|
||||
O_DW_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DR_W GETX [0 ] 0
|
||||
O_DR_W GETS [0 ] 0
|
||||
O_DR_W Lockdown [0 ] 0
|
||||
O_DR_W Unlockdown [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DR_W Data_Owner [0 ] 0
|
||||
O_DR_W Data_All_Tokens [0 ] 0
|
||||
O_DR_W Ack_Owner [0 ] 0
|
||||
O_DR_W Tokens [0 ] 0
|
||||
O_DR_W Ack_All_Tokens [0 ] 0
|
||||
O_DR_W Request_Timeout [0 ] 0
|
||||
O_DR_W Memory_Data [0 ] 0
|
||||
O_DR_W DMA_READ [0 ] 0
|
||||
O_DR_W DMA_WRITE [0 ] 0
|
||||
O_DR_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW GETX [0 ] 0
|
||||
O_DW GETS [0 ] 0
|
||||
O_DW Lockdown [0 ] 0
|
||||
O_DW Unlockdown [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW Data_Owner [0 ] 0
|
||||
O_DW Data_All_Tokens [0 ] 0
|
||||
O_DW Ack_Owner [0 ] 0
|
||||
O_DW Ack_Owner_All_Tokens [0 ] 0
|
||||
O_DW Tokens [0 ] 0
|
||||
O_DW Ack_All_Tokens [0 ] 0
|
||||
O_DW Request_Timeout [0 ] 0
|
||||
O_DW DMA_READ [0 ] 0
|
||||
O_DW DMA_WRITE [0 ] 0
|
||||
O_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DW GETX [0 ] 0
|
||||
NO_DW GETS [0 ] 0
|
||||
NO_DW Lockdown [0 ] 0
|
||||
NO_DW Unlockdown [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DW Data_Owner [0 ] 0
|
||||
NO_DW Data_All_Tokens [0 ] 0
|
||||
NO_DW Tokens [0 ] 0
|
||||
NO_DW Request_Timeout [0 ] 0
|
||||
NO_DW DMA_READ [0 ] 0
|
||||
NO_DW DMA_WRITE [0 ] 0
|
||||
NO_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DR GETX [0 ] 0
|
||||
NO_DR GETS [0 ] 0
|
||||
NO_DR Lockdown [0 ] 0
|
||||
NO_DR Unlockdown [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DR Data_Owner [0 ] 0
|
||||
NO_DR Data_All_Tokens [0 ] 0
|
||||
NO_DR Tokens [0 ] 0
|
||||
NO_DR Request_Timeout [0 ] 0
|
||||
NO_DR DMA_READ [0 ] 0
|
||||
NO_DR DMA_WRITE [0 ] 0
|
||||
NO_DR DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L GETX [0 ] 0
|
||||
DW_L GETS [0 ] 0
|
||||
DW_L Lockdown [0 ] 0
|
||||
DW_L Unlockdown [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L Data_Owner [0 ] 0
|
||||
DW_L Data_All_Tokens [0 ] 0
|
||||
DW_L Ack_Owner [0 ] 0
|
||||
DW_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DW_L Tokens [0 ] 0
|
||||
DW_L Request_Timeout [0 ] 0
|
||||
DW_L DMA_READ [0 ] 0
|
||||
DW_L DMA_WRITE [0 ] 0
|
||||
DW_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L GETX [0 ] 0
|
||||
DR_L GETS [0 ] 0
|
||||
DR_L Lockdown [0 ] 0
|
||||
DR_L Unlockdown [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L Data_Owner [0 ] 0
|
||||
DR_L Data_All_Tokens [0 ] 0
|
||||
DR_L Ack_Owner [0 ] 0
|
||||
DR_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DR_L Tokens [0 ] 0
|
||||
DR_L Request_Timeout [0 ] 0
|
||||
DR_L DMA_READ [0 ] 0
|
||||
DR_L DMA_WRITE [0 ] 0
|
||||
DR_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.006151 # Nu
|
|||
sim_ticks 6151475 # Number of ticks simulated
|
||||
final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 50702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252748 # Number of bytes of host memory used
|
||||
host_seconds 121.33 # Real time elapsed on the host
|
||||
host_tick_rate 60261 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292536 # Number of bytes of host memory used
|
||||
host_seconds 102.08 # Real time elapsed on the host
|
||||
system.funcbus.throughput 0 # Throughput (bytes/s)
|
||||
system.funcbus.data_through_bus 0 # Total data (bytes)
|
||||
system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits
|
||||
|
|
@ -60,6 +60,24 @@ system.ruby.l1_cntrl3.L1Icache.demand_accesses 0
|
|||
system.ruby.l2_cntrl0.L2cache.demand_hits 1681 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 615142 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 616823 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 844944 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 610587 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 234338 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 42719 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 26579508 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 577720 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 15763537 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 42920765 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 50.797171 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 4097613 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 7372232 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2122830 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1320142 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 5356376 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 6310315 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 26606 3.15% 3.15% | 25663 3.04% 6.19% | 25635 3.03% 9.22% | 25980 3.07% 12.29% | 25947 3.07% 15.37% | 25870 3.06% 18.43% | 25993 3.08% 21.50% | 25627 3.03% 24.54% | 26268 3.11% 27.65% | 26143 3.09% 30.74% | 25936 3.07% 33.81% | 26178 3.10% 36.91% | 26391 3.12% 40.03% | 26459 3.13% 43.16% | 26079 3.09% 46.25% | 26348 3.12% 49.37% | 26234 3.10% 52.47% | 26478 3.13% 55.61% | 26175 3.10% 58.70% | 26431 3.13% 61.83% | 26351 3.12% 64.95% | 26505 3.14% 68.09% | 26354 3.12% 71.21% | 26626 3.15% 74.36% | 26636 3.15% 77.51% | 26614 3.15% 80.66% | 27037 3.20% 83.86% | 26934 3.19% 87.05% | 26972 3.19% 90.24% | 27613 3.27% 93.51% | 27729 3.28% 96.79% | 27132 3.21% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 844944 # Number of accesses per bank
|
||||
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 54250 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
|
|
@ -84,5 +102,548 @@ system.cpu6.num_copies 0 # nu
|
|||
system.cpu7.num_reads 99727 # number of read accesses completed
|
||||
system.cpu7.num_writes 53437 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.ruby.l1_cntrl0.Load | 50331 12.55% 12.55% | 49967 12.46% 25.00% | 50254 12.53% 37.53% | 50183 12.51% 50.04% | 50017 12.47% 62.51% | 50259 12.53% 75.03% | 50136 12.50% 87.53% | 50016 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 401163
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 26960 12.49% 12.49% | 27312 12.65% 25.15% | 26841 12.44% 37.58% | 26622 12.33% 49.92% | 26950 12.49% 62.40% | 27007 12.51% 74.92% | 27203 12.60% 87.52% | 26930 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 215825
|
||||
|
||||
system.ruby.l1_cntrl0.L1_Replacement | 1368057 12.53% 12.53% | 1367643 12.53% 25.06% | 1363908 12.49% 37.56% | 1358410 12.44% 50.00% | 1362554 12.48% 62.48% | 1365525 12.51% 74.99% | 1369124 12.54% 87.53% | 1360777 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement::total 10915998
|
||||
|
||||
system.ruby.l1_cntrl0.Data_Shared | 236 13.02% 13.02% | 219 12.09% 25.11% | 237 13.08% 38.19% | 210 11.59% 49.78% | 242 13.36% 63.13% | 233 12.86% 75.99% | 202 11.15% 87.14% | 233 12.86% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_Shared::total 1812
|
||||
|
||||
system.ruby.l1_cntrl0.Data_Owner | 73 15.24% 15.24% | 74 15.45% 30.69% | 52 10.86% 41.54% | 50 10.44% 51.98% | 71 14.82% 66.81% | 66 13.78% 80.58% | 41 8.56% 89.14% | 52 10.86% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_Owner::total 479
|
||||
|
||||
system.ruby.l1_cntrl0.Data_All_Tokens | 80940 12.55% 12.55% | 80743 12.52% 25.06% | 80630 12.50% 37.56% | 80297 12.45% 50.01% | 80401 12.46% 62.47% | 80744 12.52% 74.99% | 80888 12.54% 87.53% | 80464 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.Data_All_Tokens::total 645107
|
||||
|
||||
system.ruby.l1_cntrl0.Ack | 1 7.14% 7.14% | 0 0.00% 7.14% | 3 21.43% 28.57% | 0 0.00% 28.57% | 3 21.43% 50.00% | 2 14.29% 64.29% | 4 28.57% 92.86% | 1 7.14% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack::total 14
|
||||
|
||||
system.ruby.l1_cntrl0.Ack_All_Tokens | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack_All_Tokens::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.Transient_Local_GETX | 188823 12.50% 12.50% | 188465 12.48% 24.98% | 188937 12.51% 37.49% | 189155 12.52% 50.01% | 188828 12.50% 62.51% | 188776 12.50% 75.01% | 188573 12.48% 87.50% | 188847 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Transient_Local_GETX::total 1510404
|
||||
|
||||
system.ruby.l1_cntrl0.Transient_Local_GETS | 350731 12.49% 12.49% | 351096 12.51% 25.00% | 350807 12.50% 37.50% | 350881 12.50% 49.99% | 351048 12.50% 62.50% | 350805 12.50% 74.99% | 350930 12.50% 87.50% | 351050 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Transient_Local_GETS::total 2807348
|
||||
|
||||
system.ruby.l1_cntrl0.Transient_Local_GETS_Last_Token | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 0 0.00% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.Transient_Local_GETS_Last_Token::total 9
|
||||
|
||||
system.ruby.l1_cntrl0.Persistent_GETX | 40243 12.48% 12.48% | 40235 12.48% 24.97% | 40237 12.48% 37.45% | 40452 12.55% 50.00% | 40236 12.48% 62.48% | 40319 12.51% 74.99% | 40323 12.51% 87.50% | 40294 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Persistent_GETX::total 322339
|
||||
|
||||
system.ruby.l1_cntrl0.Persistent_GETS | 74022 12.51% 12.51% | 73973 12.50% 25.00% | 73853 12.48% 37.48% | 73992 12.50% 49.98% | 74071 12.51% 62.50% | 73914 12.49% 74.99% | 74014 12.51% 87.49% | 74024 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Persistent_GETS::total 591863
|
||||
|
||||
system.ruby.l1_cntrl0.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.Persistent_GETS_Last_Token::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.Own_Lock_or_Unlock | 145427 12.50% 12.50% | 145484 12.51% 25.01% | 145601 12.52% 37.52% | 145247 12.49% 50.01% | 145384 12.50% 62.51% | 145459 12.50% 75.01% | 145355 12.49% 87.50% | 145374 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Own_Lock_or_Unlock::total 1163331
|
||||
|
||||
system.ruby.l1_cntrl0.Request_Timeout | 60159 12.52% 12.52% | 59656 12.41% 24.93% | 60277 12.54% 37.47% | 60879 12.67% 50.14% | 60010 12.49% 62.63% | 60642 12.62% 75.24% | 60033 12.49% 87.74% | 58941 12.26% 100.00%
|
||||
system.ruby.l1_cntrl0.Request_Timeout::total 480597
|
||||
|
||||
system.ruby.l1_cntrl0.Use_TimeoutStarverX | 5 5.62% 5.62% | 4 4.49% 10.11% | 12 13.48% 23.60% | 11 12.36% 35.96% | 13 14.61% 50.56% | 10 11.24% 61.80% | 18 20.22% 82.02% | 16 17.98% 100.00%
|
||||
system.ruby.l1_cntrl0.Use_TimeoutStarverX::total 89
|
||||
|
||||
system.ruby.l1_cntrl0.Use_TimeoutStarverS | 6 4.35% 4.35% | 15 10.87% 15.22% | 16 11.59% 26.81% | 13 9.42% 36.23% | 14 10.14% 46.38% | 25 18.12% 64.49% | 24 17.39% 81.88% | 25 18.12% 100.00%
|
||||
system.ruby.l1_cntrl0.Use_TimeoutStarverS::total 138
|
||||
|
||||
system.ruby.l1_cntrl0.Use_TimeoutNoStarvers | 76982 12.53% 12.53% | 76971 12.53% 25.05% | 76777 12.49% 37.55% | 76512 12.45% 50.00% | 76634 12.47% 62.47% | 76926 12.52% 74.99% | 77048 12.54% 87.53% | 76616 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.Use_TimeoutNoStarvers::total 614466
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Load | 50234 12.54% 12.54% | 49878 12.46% 25.00% | 50162 12.53% 37.53% | 50102 12.51% 50.04% | 49920 12.47% 62.51% | 50179 12.53% 75.04% | 50054 12.50% 87.54% | 49912 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Load::total 400441
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Store | 26908 12.49% 12.49% | 27274 12.66% 25.15% | 26779 12.43% 37.57% | 26582 12.34% 49.91% | 26907 12.49% 62.40% | 26962 12.51% 74.91% | 27158 12.60% 87.52% | 26896 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Store::total 215466
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Data_Shared | 15 25.42% 25.42% | 7 11.86% 37.29% | 5 8.47% 45.76% | 4 6.78% 52.54% | 11 18.64% 71.19% | 6 10.17% 81.36% | 6 10.17% 91.53% | 5 8.47% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Data_Shared::total 59
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Data_Owner | 21 18.26% 18.26% | 15 13.04% 31.30% | 12 10.43% 41.74% | 10 8.70% 50.43% | 18 15.65% 66.09% | 16 13.91% 80.00% | 11 9.57% 89.57% | 12 10.43% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Data_Owner::total 115
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Data_All_Tokens | 3905 12.91% 12.91% | 3708 12.26% 25.17% | 3801 12.57% 37.73% | 3744 12.38% 50.11% | 3722 12.30% 62.42% | 3775 12.48% 74.90% | 3791 12.53% 87.43% | 3803 12.57% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Data_All_Tokens::total 30249
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Ack::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Transient_Local_GETX | 188213 12.50% 12.50% | 187862 12.48% 24.98% | 188356 12.51% 37.49% | 188542 12.52% 50.01% | 188229 12.50% 62.52% | 188157 12.50% 75.01% | 187989 12.49% 87.50% | 188206 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Transient_Local_GETX::total 1505554
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Transient_Local_GETS | 349628 12.49% 12.49% | 349983 12.51% 25.00% | 349669 12.50% 37.50% | 349728 12.50% 49.99% | 349922 12.50% 62.50% | 349655 12.50% 74.99% | 349776 12.50% 87.49% | 349964 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Transient_Local_GETS::total 2798325
|
||||
|
||||
system.ruby.l1_cntrl0.NP.Own_Lock_or_Unlock | 126885 12.50% 12.50% | 126871 12.50% 25.00% | 126751 12.49% 37.48% | 126905 12.50% 49.99% | 126881 12.50% 62.49% | 126869 12.50% 74.98% | 126992 12.51% 87.49% | 126955 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.NP.Own_Lock_or_Unlock::total 1015109
|
||||
|
||||
system.ruby.l1_cntrl0.I.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Load::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement | 183 13.13% 13.13% | 170 12.20% 25.32% | 174 12.48% 37.80% | 180 12.91% 50.72% | 173 12.41% 63.13% | 164 11.76% 74.89% | 159 11.41% 86.30% | 191 13.70% 100.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement::total 1394
|
||||
|
||||
system.ruby.l1_cntrl0.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Transient_Local_GETX::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Transient_Local_GETS::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Persistent_GETX::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.I.Persistent_GETS | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Persistent_GETS::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.I.Own_Lock_or_Unlock | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Own_Lock_or_Unlock::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Load::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement | 249 11.95% 11.95% | 252 12.09% 24.04% | 274 13.15% 37.19% | 244 11.71% 48.90% | 272 13.05% 61.95% | 281 13.48% 75.43% | 241 11.56% 87.00% | 271 13.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement::total 2084
|
||||
|
||||
system.ruby.l1_cntrl0.S.Data_Shared | 1 20.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Data_Shared::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.S.Data_All_Tokens | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Data_All_Tokens::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.S.Transient_Local_GETX | 1 12.50% 12.50% | 2 25.00% 37.50% | 1 12.50% 50.00% | 1 12.50% 62.50% | 2 25.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Transient_Local_GETX::total 8
|
||||
|
||||
system.ruby.l1_cntrl0.S.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Transient_Local_GETS::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.S.Transient_Local_GETS_Last_Token | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 0 0.00% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Transient_Local_GETS_Last_Token::total 9
|
||||
|
||||
system.ruby.l1_cntrl0.S.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Persistent_GETX::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.S.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Persistent_GETS::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Persistent_GETS_Last_Token::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.O.L1_Replacement | 133 13.05% 13.05% | 127 12.46% 25.52% | 116 11.38% 36.90% | 134 13.15% 50.05% | 132 12.95% 63.00% | 145 14.23% 77.23% | 111 10.89% 88.13% | 121 11.87% 100.00%
|
||||
system.ruby.l1_cntrl0.O.L1_Replacement::total 1019
|
||||
|
||||
system.ruby.l1_cntrl0.O.Data_All_Tokens | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Data_All_Tokens::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.O.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Ack_All_Tokens::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.O.Transient_Local_GETX | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Transient_Local_GETX::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.O.Persistent_GETS | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Persistent_GETS::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.O.Own_Lock_or_Unlock | 12 12.24% 12.24% | 15 15.31% 27.55% | 17 17.35% 44.90% | 13 13.27% 58.16% | 12 12.24% 70.41% | 13 13.27% 83.67% | 10 10.20% 93.88% | 6 6.12% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Own_Lock_or_Unlock::total 98
|
||||
|
||||
system.ruby.l1_cntrl0.M.Load | 5 12.20% 12.20% | 2 4.88% 17.07% | 3 7.32% 24.39% | 5 12.20% 36.59% | 5 12.20% 48.78% | 3 7.32% 56.10% | 8 19.51% 75.61% | 10 24.39% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Load::total 41
|
||||
|
||||
system.ruby.l1_cntrl0.M.Store | 3 14.29% 14.29% | 2 9.52% 23.81% | 5 23.81% 47.62% | 4 19.05% 66.67% | 3 14.29% 80.95% | 4 19.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 21
|
||||
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement | 49847 12.55% 12.55% | 49500 12.46% 25.00% | 49774 12.53% 37.53% | 49713 12.51% 50.04% | 49519 12.46% 62.51% | 49733 12.52% 75.03% | 49702 12.51% 87.53% | 49527 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement::total 397315
|
||||
|
||||
system.ruby.l1_cntrl0.M.Transient_Local_GETX | 50 13.62% 13.62% | 36 9.81% 23.43% | 52 14.17% 37.60% | 40 10.90% 48.50% | 46 12.53% 61.04% | 55 14.99% 76.02% | 33 8.99% 85.01% | 55 14.99% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Transient_Local_GETX::total 367
|
||||
|
||||
system.ruby.l1_cntrl0.M.Transient_Local_GETS | 83 12.44% 12.44% | 71 10.64% 23.09% | 76 11.39% 34.48% | 96 14.39% 48.88% | 80 11.99% 60.87% | 96 14.39% 75.26% | 81 12.14% 87.41% | 84 12.59% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Transient_Local_GETS::total 667
|
||||
|
||||
system.ruby.l1_cntrl0.M.Persistent_GETX | 25 16.78% 16.78% | 26 17.45% 34.23% | 14 9.40% 43.62% | 21 14.09% 57.72% | 21 14.09% 71.81% | 13 8.72% 80.54% | 18 12.08% 92.62% | 11 7.38% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Persistent_GETX::total 149
|
||||
|
||||
system.ruby.l1_cntrl0.M.Persistent_GETS | 27 10.63% 10.63% | 31 12.20% 22.83% | 33 12.99% 35.83% | 32 12.60% 48.43% | 36 14.17% 62.60% | 38 14.96% 77.56% | 28 11.02% 88.58% | 29 11.42% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Persistent_GETS::total 254
|
||||
|
||||
system.ruby.l1_cntrl0.M.Own_Lock_or_Unlock | 1187 12.24% 12.24% | 1229 12.68% 24.92% | 1293 13.34% 38.25% | 1200 12.38% 50.63% | 1221 12.59% 63.22% | 1249 12.88% 76.10% | 1131 11.66% 87.77% | 1186 12.23% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Own_Lock_or_Unlock::total 9696
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Load | 1 4.17% 4.17% | 5 20.83% 25.00% | 2 8.33% 33.33% | 7 29.17% 62.50% | 3 12.50% 75.00% | 2 8.33% 83.33% | 3 12.50% 95.83% | 1 4.17% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Load::total 24
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Store | 5 33.33% 33.33% | 1 6.67% 40.00% | 1 6.67% 46.67% | 1 6.67% 53.33% | 0 0.00% 53.33% | 3 20.00% 73.33% | 1 6.67% 80.00% | 3 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Store::total 15
|
||||
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement | 26851 12.49% 12.49% | 27209 12.66% 25.15% | 26736 12.44% 37.58% | 26508 12.33% 49.91% | 26847 12.49% 62.40% | 26914 12.52% 74.92% | 27102 12.61% 87.53% | 26811 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement::total 214978
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Transient_Local_GETX | 31 14.76% 14.76% | 33 15.71% 30.48% | 27 12.86% 43.33% | 28 13.33% 56.67% | 17 8.10% 64.76% | 21 10.00% 74.76% | 25 11.90% 86.67% | 28 13.33% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Transient_Local_GETX::total 210
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Transient_Local_GETS | 45 14.11% 14.11% | 36 11.29% 25.39% | 37 11.60% 36.99% | 41 12.85% 49.84% | 49 15.36% 65.20% | 33 10.34% 75.55% | 36 11.29% 86.83% | 42 13.17% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Transient_Local_GETS::total 319
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Persistent_GETX | 11 13.10% 13.10% | 11 13.10% 26.19% | 10 11.90% 38.10% | 17 20.24% 58.33% | 10 11.90% 70.24% | 10 11.90% 82.14% | 8 9.52% 91.67% | 7 8.33% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Persistent_GETX::total 84
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Persistent_GETS | 12 10.17% 10.17% | 17 14.41% 24.58% | 17 14.41% 38.98% | 14 11.86% 50.85% | 9 7.63% 58.47% | 12 10.17% 68.64% | 15 12.71% 81.36% | 22 18.64% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Persistent_GETS::total 118
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Own_Lock_or_Unlock | 712 13.37% 13.37% | 667 12.52% 25.89% | 685 12.86% 38.75% | 670 12.58% 51.32% | 668 12.54% 63.86% | 648 12.16% 76.03% | 636 11.94% 87.97% | 641 12.03% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Own_Lock_or_Unlock::total 5327
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Load | 2 7.14% 7.14% | 4 14.29% 21.43% | 5 17.86% 39.29% | 3 10.71% 50.00% | 3 10.71% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 4 14.29% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Load::total 28
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Store | 1 11.11% 11.11% | 2 22.22% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 11.11% 44.44% | 2 22.22% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Store::total 9
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement | 291266 12.59% 12.59% | 289622 12.52% 25.11% | 289644 12.52% 37.63% | 290259 12.55% 50.18% | 288045 12.45% 62.63% | 288216 12.46% 75.09% | 288197 12.46% 87.55% | 287895 12.45% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement::total 2313144
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Transient_Local_GETX | 42 14.38% 14.38% | 27 9.25% 23.63% | 30 10.27% 33.90% | 37 12.67% 46.58% | 39 13.36% 59.93% | 45 15.41% 75.34% | 33 11.30% 86.64% | 39 13.36% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Transient_Local_GETX::total 292
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Transient_Local_GETS | 66 11.60% 11.60% | 79 13.88% 25.48% | 75 13.18% 38.66% | 88 15.47% 54.13% | 63 11.07% 65.20% | 60 10.54% 75.75% | 78 13.71% 89.46% | 60 10.54% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Transient_Local_GETS::total 569
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Persistent_GETX | 3 7.14% 7.14% | 4 9.52% 16.67% | 4 9.52% 26.19% | 5 11.90% 38.10% | 4 9.52% 47.62% | 6 14.29% 61.90% | 8 19.05% 80.95% | 8 19.05% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Persistent_GETX::total 42
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Persistent_GETS | 5 5.88% 5.88% | 11 12.94% 18.82% | 11 12.94% 31.76% | 4 4.71% 36.47% | 7 8.24% 44.71% | 15 17.65% 62.35% | 15 17.65% 80.00% | 17 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Persistent_GETS::total 85
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Own_Lock_or_Unlock | 469 12.17% 12.17% | 479 12.43% 24.60% | 514 13.34% 37.94% | 489 12.69% 50.64% | 496 12.87% 63.51% | 466 12.09% 75.60% | 481 12.48% 88.09% | 459 11.91% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Own_Lock_or_Unlock::total 3853
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutStarverX | 4 7.69% 7.69% | 4 7.69% 15.38% | 5 9.62% 25.00% | 6 11.54% 36.54% | 5 9.62% 46.15% | 7 13.46% 59.62% | 11 21.15% 80.77% | 10 19.23% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutStarverX::total 52
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutStarverS | 5 5.38% 5.38% | 11 11.83% 17.20% | 12 12.90% 30.11% | 6 6.45% 36.56% | 8 8.60% 45.16% | 17 18.28% 63.44% | 17 18.28% 81.72% | 17 18.28% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutStarverS::total 93
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers | 50035 12.55% 12.55% | 49666 12.45% 25.00% | 49954 12.53% 37.53% | 49907 12.52% 50.04% | 49705 12.46% 62.51% | 49940 12.52% 75.03% | 49862 12.50% 87.54% | 49706 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers::total 398775
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Load | 5 27.78% 27.78% | 1 5.56% 33.33% | 0 0.00% 33.33% | 2 11.11% 44.44% | 3 16.67% 61.11% | 5 27.78% 88.89% | 1 5.56% 94.44% | 1 5.56% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Load::total 18
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Store | 2 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store::total 8
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement | 155942 12.48% 12.48% | 158074 12.65% 25.12% | 153918 12.31% 37.44% | 152634 12.21% 49.65% | 158304 12.67% 62.32% | 157087 12.57% 74.89% | 158031 12.64% 87.53% | 155857 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement::total 1249847
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Transient_Local_GETX | 23 13.07% 13.07% | 18 10.23% 23.30% | 18 10.23% 33.52% | 26 14.77% 48.30% | 23 13.07% 61.36% | 21 11.93% 73.30% | 20 11.36% 84.66% | 27 15.34% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Transient_Local_GETX::total 176
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Transient_Local_GETS | 30 9.71% 9.71% | 45 14.56% 24.27% | 31 10.03% 34.30% | 43 13.92% 48.22% | 33 10.68% 58.90% | 40 12.94% 71.84% | 44 14.24% 86.08% | 43 13.92% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Transient_Local_GETS::total 309
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Persistent_GETX | 1 3.03% 3.03% | 0 0.00% 3.03% | 6 18.18% 21.21% | 4 12.12% 33.33% | 7 21.21% 54.55% | 2 6.06% 60.61% | 7 21.21% 81.82% | 6 18.18% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Persistent_GETX::total 33
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Persistent_GETS | 1 2.38% 2.38% | 3 7.14% 9.52% | 3 7.14% 16.67% | 7 16.67% 33.33% | 6 14.29% 47.62% | 7 16.67% 64.29% | 7 16.67% 80.95% | 8 19.05% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Persistent_GETS::total 42
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Own_Lock_or_Unlock | 292 13.90% 13.90% | 270 12.85% 26.75% | 253 12.04% 38.79% | 231 10.99% 49.79% | 270 12.85% 62.64% | 272 12.95% 75.58% | 278 13.23% 88.81% | 235 11.19% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Own_Lock_or_Unlock::total 2101
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutStarverX | 1 2.70% 2.70% | 0 0.00% 2.70% | 7 18.92% 21.62% | 5 13.51% 35.14% | 8 21.62% 56.76% | 3 8.11% 64.86% | 7 18.92% 83.78% | 6 16.22% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutStarverX::total 37
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutStarverS | 1 2.22% 2.22% | 4 8.89% 11.11% | 4 8.89% 20.00% | 7 15.56% 35.56% | 6 13.33% 48.89% | 8 17.78% 66.67% | 7 15.56% 82.22% | 8 17.78% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutStarverS::total 45
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers | 26947 12.49% 12.49% | 27305 12.66% 25.15% | 26823 12.44% 37.59% | 26605 12.33% 49.92% | 26929 12.48% 62.41% | 26986 12.51% 74.92% | 27186 12.60% 87.52% | 26910 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers::total 215691
|
||||
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement | 293340 12.49% 12.49% | 295809 12.59% 25.08% | 291989 12.43% 37.52% | 287885 12.26% 49.77% | 295320 12.57% 62.35% | 295503 12.58% 74.93% | 296204 12.61% 87.54% | 292704 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement::total 2348754
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data_Owner | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_Owner::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data_All_Tokens | 26946 12.49% 12.49% | 27305 12.66% 25.15% | 26829 12.44% 37.58% | 26615 12.34% 49.92% | 26941 12.49% 62.40% | 26992 12.51% 74.92% | 27198 12.61% 87.52% | 26921 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_All_Tokens::total 215747
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Ack | 1 10.00% 10.00% | 0 0.00% 10.00% | 1 10.00% 20.00% | 0 0.00% 20.00% | 2 20.00% 40.00% | 2 20.00% 60.00% | 3 30.00% 90.00% | 1 10.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Ack::total 10
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Transient_Local_GETX | 90 12.45% 12.45% | 84 11.62% 24.07% | 90 12.45% 36.51% | 94 13.00% 49.52% | 93 12.86% 62.38% | 87 12.03% 74.41% | 89 12.31% 86.72% | 96 13.28% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Transient_Local_GETX::total 723
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Transient_Local_GETS | 147 11.89% 11.89% | 144 11.65% 23.54% | 177 14.32% 37.86% | 153 12.38% 50.24% | 146 11.81% 62.06% | 154 12.46% 74.51% | 150 12.14% 86.65% | 165 13.35% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Transient_Local_GETS::total 1236
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Persistent_GETX | 29 14.15% 14.15% | 27 13.17% 27.32% | 22 10.73% 38.05% | 27 13.17% 51.22% | 26 12.68% 63.90% | 33 16.10% 80.00% | 22 10.73% 90.73% | 19 9.27% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Persistent_GETX::total 205
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Persistent_GETS | 36 9.28% 9.28% | 39 10.05% 19.33% | 50 12.89% 32.22% | 42 10.82% 43.04% | 48 12.37% 55.41% | 53 13.66% 69.07% | 57 14.69% 83.76% | 63 16.24% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Persistent_GETS::total 388
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Own_Lock_or_Unlock | 5483 12.57% 12.57% | 5506 12.62% 25.19% | 5529 12.68% 37.87% | 5327 12.21% 50.08% | 5492 12.59% 62.67% | 5408 12.40% 75.07% | 5402 12.38% 87.46% | 5471 12.54% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Own_Lock_or_Unlock::total 43618
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Request_Timeout | 20923 12.52% 12.52% | 21057 12.60% 25.13% | 21290 12.74% 37.87% | 20719 12.40% 50.27% | 21245 12.72% 62.99% | 21018 12.58% 75.57% | 20732 12.41% 87.98% | 20087 12.02% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Request_Timeout::total 167071
|
||||
|
||||
system.ruby.l1_cntrl0.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.L1_Replacement::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Data_All_Tokens::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Ack_All_Tokens | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Ack_All_Tokens::total 4
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Own_Lock_or_Unlock::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Request_Timeout::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement | 548020 12.55% 12.55% | 544678 12.47% 25.02% | 548767 12.57% 37.58% | 548504 12.56% 50.14% | 541488 12.40% 62.54% | 544959 12.48% 75.02% | 546694 12.52% 87.54% | 544234 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement::total 4367344
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_Shared | 219 12.55% 12.55% | 212 12.15% 24.70% | 230 13.18% 37.88% | 206 11.81% 49.68% | 230 13.18% 62.87% | 226 12.95% 75.82% | 196 11.23% 87.05% | 226 12.95% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Shared::total 1745
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_Owner | 51 14.21% 14.21% | 58 16.16% 30.36% | 40 11.14% 41.50% | 39 10.86% 52.37% | 53 14.76% 67.13% | 50 13.93% 81.06% | 30 8.36% 89.42% | 38 10.58% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Owner::total 359
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data_All_Tokens | 50045 12.55% 12.55% | 49683 12.45% 25.00% | 49970 12.53% 37.53% | 49916 12.51% 50.04% | 49717 12.46% 62.50% | 49963 12.52% 75.03% | 49887 12.51% 87.53% | 49732 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_All_Tokens::total 398913
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Ack::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Transient_Local_GETX | 152 12.13% 12.13% | 168 13.41% 25.54% | 140 11.17% 36.71% | 160 12.77% 49.48% | 153 12.21% 61.69% | 161 12.85% 74.54% | 153 12.21% 86.75% | 166 13.25% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Transient_Local_GETX::total 1253
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Transient_Local_GETS | 287 12.04% 12.04% | 298 12.50% 24.54% | 300 12.58% 37.12% | 291 12.21% 49.33% | 322 13.51% 62.84% | 311 13.05% 75.88% | 302 12.67% 88.55% | 273 11.45% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Transient_Local_GETS::total 2384
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Persistent_GETX | 36 9.07% 9.07% | 37 9.32% 18.39% | 47 11.84% 30.23% | 56 14.11% 44.33% | 49 12.34% 56.68% | 57 14.36% 71.03% | 59 14.86% 85.89% | 56 14.11% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Persistent_GETX::total 397
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Persistent_GETS | 86 10.87% 10.87% | 112 14.16% 25.03% | 92 11.63% 36.66% | 95 12.01% 48.67% | 105 13.27% 61.95% | 100 12.64% 74.59% | 104 13.15% 87.74% | 97 12.26% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Persistent_GETS::total 791
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Own_Lock_or_Unlock | 9989 12.48% 12.48% | 10016 12.52% 25.00% | 10115 12.64% 37.64% | 9985 12.48% 50.12% | 9893 12.36% 62.49% | 10088 12.61% 75.09% | 9969 12.46% 87.55% | 9961 12.45% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Own_Lock_or_Unlock::total 80016
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Request_Timeout | 38867 12.52% 12.52% | 38204 12.31% 24.83% | 38667 12.46% 37.29% | 39766 12.81% 50.11% | 38271 12.33% 62.44% | 39197 12.63% 75.07% | 38932 12.54% 87.61% | 38452 12.39% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Request_Timeout::total 310356
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Load | 84 13.79% 13.79% | 77 12.64% 26.44% | 81 13.30% 39.74% | 64 10.51% 50.25% | 83 13.63% 63.88% | 66 10.84% 74.71% | 66 10.84% 85.55% | 88 14.45% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Load::total 609
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Store | 41 13.40% 13.40% | 33 10.78% 24.18% | 56 18.30% 42.48% | 35 11.44% 53.92% | 37 12.09% 66.01% | 34 11.11% 77.12% | 41 13.40% 90.52% | 29 9.48% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Store::total 306
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.L1_Replacement | 206 10.60% 10.60% | 148 7.61% 18.21% | 234 12.04% 30.25% | 329 16.92% 47.17% | 249 12.81% 59.98% | 203 10.44% 70.42% | 258 13.27% 83.69% | 317 16.31% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.L1_Replacement::total 1944
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Data_All_Tokens | 41 25.00% 25.00% | 45 27.44% 52.44% | 23 14.02% 66.46% | 18 10.98% 77.44% | 18 10.98% 88.41% | 8 4.88% 93.29% | 7 4.27% 97.56% | 4 2.44% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Data_All_Tokens::total 164
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Transient_Local_GETX | 221 12.20% 12.20% | 233 12.87% 25.07% | 222 12.26% 37.33% | 225 12.42% 49.75% | 225 12.42% 62.18% | 228 12.59% 74.77% | 230 12.70% 87.47% | 227 12.53% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Transient_Local_GETX::total 1811
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Transient_Local_GETS | 445 12.62% 12.62% | 439 12.45% 25.07% | 441 12.51% 37.58% | 435 12.34% 49.91% | 432 12.25% 62.17% | 455 12.90% 75.07% | 463 13.13% 88.20% | 416 11.80% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Transient_Local_GETS::total 3526
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Persistent_GETX | 40137 12.49% 12.49% | 40125 12.49% 24.98% | 40121 12.49% 37.47% | 40304 12.54% 50.01% | 40099 12.48% 62.49% | 40175 12.50% 75.00% | 40167 12.50% 87.50% | 40156 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Persistent_GETX::total 321284
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Persistent_GETS | 73854 12.52% 12.52% | 73741 12.50% 25.02% | 73628 12.48% 37.50% | 73761 12.50% 50.01% | 73818 12.51% 62.52% | 73632 12.48% 75.01% | 73718 12.50% 87.50% | 73704 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Persistent_GETS::total 589856
|
||||
|
||||
system.ruby.l1_cntrl0.I_L.Own_Lock_or_Unlock | 57 11.56% 11.56% | 63 12.78% 24.34% | 57 11.56% 35.90% | 71 14.40% 50.30% | 60 12.17% 62.47% | 54 10.95% 73.43% | 66 13.39% 86.82% | 65 13.18% 100.00%
|
||||
system.ruby.l1_cntrl0.I_L.Own_Lock_or_Unlock::total 493
|
||||
|
||||
system.ruby.l1_cntrl0.S_L.L1_Replacement | 42 10.42% 10.42% | 35 8.68% 19.11% | 64 15.88% 34.99% | 55 13.65% 48.64% | 24 5.96% 54.59% | 80 19.85% 74.44% | 47 11.66% 86.10% | 56 13.90% 100.00%
|
||||
system.ruby.l1_cntrl0.S_L.L1_Replacement::total 403
|
||||
|
||||
system.ruby.l1_cntrl0.S_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.S_L.Transient_Local_GETX::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.S_L.Persistent_GETS | 0 0.00% 0.00% | 4 6.35% 6.35% | 7 11.11% 17.46% | 6 9.52% 26.98% | 5 7.94% 34.92% | 17 26.98% 61.90% | 10 15.87% 77.78% | 14 22.22% 100.00%
|
||||
system.ruby.l1_cntrl0.S_L.Persistent_GETS::total 63
|
||||
|
||||
system.ruby.l1_cntrl0.S_L.Own_Lock_or_Unlock | 32 9.04% 9.04% | 43 12.15% 21.19% | 46 12.99% 34.18% | 40 11.30% 45.48% | 45 12.71% 58.19% | 56 15.82% 74.01% | 46 12.99% 87.01% | 46 12.99% 100.00%
|
||||
system.ruby.l1_cntrl0.S_L.Own_Lock_or_Unlock::total 354
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.L1_Replacement | 616 10.64% 10.64% | 650 11.23% 21.87% | 788 13.61% 35.49% | 576 9.95% 45.44% | 691 11.94% 57.38% | 852 14.72% 72.10% | 843 14.56% 86.66% | 772 13.34% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.L1_Replacement::total 5788
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Data_All_Tokens | 1 8.33% 8.33% | 1 8.33% 16.67% | 5 41.67% 58.33% | 1 8.33% 66.67% | 1 8.33% 75.00% | 3 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Data_All_Tokens::total 12
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Transient_Local_GETX::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Transient_Local_GETS::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Persistent_GETX | 0 0.00% 0.00% | 3 6.67% 6.67% | 2 4.44% 11.11% | 4 8.89% 20.00% | 10 22.22% 42.22% | 10 22.22% 64.44% | 10 22.22% 86.67% | 6 13.33% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Persistent_GETX::total 45
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Persistent_GETS | 0 0.00% 0.00% | 2 2.00% 2.00% | 7 7.00% 9.00% | 11 11.00% 20.00% | 13 13.00% 33.00% | 15 15.00% 48.00% | 23 23.00% 71.00% | 29 29.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Persistent_GETS::total 100
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Own_Lock_or_Unlock | 105 11.84% 11.84% | 98 11.05% 22.89% | 123 13.87% 36.75% | 103 11.61% 48.37% | 110 12.40% 60.77% | 117 13.19% 73.96% | 120 13.53% 87.49% | 111 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Own_Lock_or_Unlock::total 887
|
||||
|
||||
system.ruby.l1_cntrl0.IM_L.Request_Timeout | 92 8.01% 8.01% | 153 13.33% 21.34% | 130 11.32% 32.67% | 128 11.15% 43.82% | 153 13.33% 57.14% | 194 16.90% 74.04% | 147 12.80% 86.85% | 151 13.15% 100.00%
|
||||
system.ruby.l1_cntrl0.IM_L.Request_Timeout::total 1148
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.L1_Replacement | 1362 11.37% 11.37% | 1369 11.42% 22.79% | 1430 11.93% 34.72% | 1388 11.58% 46.31% | 1490 12.43% 58.74% | 1388 11.58% 70.32% | 1535 12.81% 83.13% | 2021 16.87% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.L1_Replacement::total 11983
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Data_Shared | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Data_Shared::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Data_All_Tokens | 1 5.56% 5.56% | 0 0.00% 5.56% | 2 11.11% 16.67% | 3 16.67% 33.33% | 2 11.11% 44.44% | 3 16.67% 61.11% | 5 27.78% 88.89% | 2 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Data_All_Tokens::total 18
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Transient_Local_GETX::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Transient_Local_GETS::total 4
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Persistent_GETX | 0 0.00% 0.00% | 2 2.04% 2.04% | 11 11.22% 13.27% | 14 14.29% 27.55% | 9 9.18% 36.73% | 13 13.27% 50.00% | 24 24.49% 74.49% | 25 25.51% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Persistent_GETX::total 98
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Persistent_GETS | 0 0.00% 0.00% | 11 6.92% 6.92% | 5 3.14% 10.06% | 18 11.32% 21.38% | 24 15.09% 36.48% | 24 15.09% 51.57% | 36 22.64% 74.21% | 41 25.79% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Persistent_GETS::total 159
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Own_Lock_or_Unlock | 204 11.49% 11.49% | 226 12.73% 24.21% | 218 12.27% 36.49% | 212 11.94% 48.42% | 235 13.23% 61.66% | 219 12.33% 73.99% | 224 12.61% 86.60% | 238 13.40% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Own_Lock_or_Unlock::total 1776
|
||||
|
||||
system.ruby.l1_cntrl0.IS_L.Request_Timeout | 277 13.71% 13.71% | 242 11.97% 25.68% | 190 9.40% 35.08% | 265 13.11% 48.19% | 341 16.87% 65.07% | 233 11.53% 76.60% | 222 10.98% 87.58% | 251 12.42% 100.00%
|
||||
system.ruby.l1_cntrl0.IS_L.Request_Timeout::total 2021
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GETS 401048 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS_Last_Token 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 215772 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_INV 1395 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 583206 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Shared_Data 1451 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_All_Tokens 613102 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Owned 843 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Persistent_GETX 46049 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Persistent_GETS 84554 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Own_Lock_or_Unlock 129089 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 399363 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 214874 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_INV 909 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_Shared_Data 1386 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 581094 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_Owned 734 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Own_Lock_or_Unlock 128754 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L1_GETS 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L1_INV 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L2_Replacement 559 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_All_Tokens 366 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_Owned 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETS_Last_Token 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.L2_Replacement 1209 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.Writeback_Shared_Data 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.Writeback_All_Tokens 176 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.Persistent_GETX 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L1_GETS 13 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L1_GETX 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L2_Replacement 1168 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Writeback_Shared_Data 7 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Writeback_All_Tokens 633 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Persistent_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Persistent_GETS 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 1075 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 590 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 579287 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.Persistent_GETX 460 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.Persistent_GETS 849 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.L1_GETS 595 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.L1_GETX 304 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.L1_INV 484 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.L2_Replacement 982 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Writeback_Shared_Data 53 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Writeback_All_Tokens 30833 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Writeback_Owned 107 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Persistent_GETX 45586 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Persistent_GETS 83699 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Own_Lock_or_Unlock 330 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S_L.L2_Replacement 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S_L.Own_Lock_or_Unlock 5 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 255487 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 476933 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Lockdown 130603 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Unlockdown 129089 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_Owner 344 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_All_Tokens 235610 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner 694 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 375677 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Tokens 456 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_All_Tokens 3709 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 610582 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 234338 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETX 212118 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETS 394360 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Lockdown 2461 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Data_All_Tokens 49 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Tokens 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Ack_All_Tokens 967 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETX 2212 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETS 3891 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Lockdown 20370 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_Owner 344 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_All_Tokens 233998 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner 694 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 375526 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Tokens 248 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.GETX 852 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.GETS 1708 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Lockdown 1080 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Unlockdown 129089 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Data_All_Tokens 106 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Ack_Owner_All_Tokens 151 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Tokens 3 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.GETX 13301 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.GETS 26689 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Lockdown 1663 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Data_All_Tokens 1388 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Tokens 201 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Ack_All_Tokens 2722 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Memory_Ack 232675 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.GETX 6131 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.GETS 13880 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.Lockdown 30 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.Data_All_Tokens 69 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.Memory_Data 4123 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.Memory_Ack 1663 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_NO_W.GETX 5886 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_NO_W.GETS 10623 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_NO_W.Lockdown 398 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_NO_W.Memory_Data 104596 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.GETX 14987 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.GETS 25782 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Lockdown 104601 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Ack_All_Tokens 20 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Memory_Data 501863 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Apr/09/2013 02:01:53
|
||||
Real time: Jun/08/2013 13:30:00
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 168
|
||||
Elapsed_time_in_minutes: 2.8
|
||||
Elapsed_time_in_hours: 0.0466667
|
||||
Elapsed_time_in_days: 0.00194444
|
||||
Elapsed_time_in_seconds: 99
|
||||
Elapsed_time_in_minutes: 1.65
|
||||
Elapsed_time_in_hours: 0.0275
|
||||
Elapsed_time_in_days: 0.00114583
|
||||
|
||||
Virtual_time_in_seconds: 167.14
|
||||
Virtual_time_in_minutes: 2.78567
|
||||
Virtual_time_in_hours: 0.0464278
|
||||
Virtual_time_in_days: 0.00193449
|
||||
Virtual_time_in_seconds: 96.67
|
||||
Virtual_time_in_minutes: 1.61117
|
||||
Virtual_time_in_hours: 0.0268528
|
||||
Virtual_time_in_days: 0.00111887
|
||||
|
||||
Ruby_current_time: 5795833
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 5795833
|
||||
|
||||
mbytes_resident: 64.7773
|
||||
mbytes_total: 244.449
|
||||
resident_ratio: 0.264993
|
||||
|
||||
ruby_cycles_executed: [ 5795834 5795834 5795834 5795834 5795834 5795834 5795834 5795834 ]
|
||||
mbytes_resident: 69.8828
|
||||
mbytes_total: 285.598
|
||||
resident_ratio: 0.244717
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -68,7 +66,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -87,13 +84,13 @@ Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 166
|
||||
user_time: 96
|
||||
system_time: 0
|
||||
page_reclaims: 17148
|
||||
page_faults: 3
|
||||
page_reclaims: 19166
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 776
|
||||
block_outputs: 312
|
||||
block_inputs: 24
|
||||
block_outputs: 256
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -324,749 +321,3 @@ links_utilized_percent_switch_9: 18.0864
|
|||
outgoing_messages_switch_9_link_8_Writeback_Control: 950339 7602712 [ 0 0 582292 0 0 368047 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Unblock_Control: 617596 4940768 [ 0 0 0 0 0 617596 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50266 50315 50271 50212 50263 50069 50306 49970 ] 401672
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [26762 27215 27106 27272 27014 27080 27361 27054 ] 216864
|
||||
L2_Replacement [76877 77378 77204 77319 77135 76978 77528 76877 ] 617296
|
||||
L1_to_L2 [839684 843217 843158 840771 842565 841910 845488 839694 ] 6736487
|
||||
Trigger_L2_to_L1D [75 72 99 79 66 89 69 72 ] 621
|
||||
Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
|
||||
Complete_L2_to_L1 [75 72 99 79 66 89 69 72 ] 621
|
||||
Other_GETX [189761 189309 189417 189262 189522 189457 189156 189455 ] 1515339
|
||||
Other_GETS [350360 350304 350380 350430 350354 350578 350311 350671 ] 2803388
|
||||
Merged_GETS [67 47 56 60 48 51 52 58 ] 439
|
||||
Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
Ack [535380 538939 537669 538458 537124 535993 539952 535252 ] 4298767
|
||||
Shared_Ack [61 58 61 63 51 74 50 68 ] 486
|
||||
Data [2873 3045 2960 3027 2998 3000 2981 3082 ] 23966
|
||||
Shared_Data [1060 1048 1056 1053 1045 1094 1078 1123 ] 8557
|
||||
Exclusive_Data [72953 73296 73198 73248 73100 72896 73480 72683 ] 584854
|
||||
Writeback_Ack [72619 73022 72821 72965 72792 72564 73169 72340 ] 582292
|
||||
Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
All_acks [1114 1096 1109 1107 1091 1156 1120 1180 ] 8973
|
||||
All_acks_no_sharers [75773 76294 76104 76221 76052 75834 76419 75708 ] 608405
|
||||
Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
Block_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [50174 50224 50155 50116 50191 49971 50219 49868 ] 400918
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [26713 27165 27060 27213 26955 27016 27320 27019 ] 216461
|
||||
I L2_Replacement [1339 1403 1446 1410 1437 1441 1373 1479 ] 11328
|
||||
I L1_to_L2 [263 295 253 281 292 256 261 290 ] 2191
|
||||
I Trigger_L2_to_L1D [3 0 1 2 0 4 2 3 ] 15
|
||||
I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
|
||||
I Other_GETX [188850 188385 188473 188307 188572 188504 188287 188527 ] 1507905
|
||||
I Other_GETS [348728 348598 348711 348779 348712 348887 348575 348998 ] 2789988
|
||||
I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
I Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
I Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
S Load [1 1 2 0 0 0 1 1 ] 6
|
||||
S Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
S Store [0 0 0 0 0 0 0 0 ] 0
|
||||
S L2_Replacement [2919 2953 2937 2944 2906 2973 2984 3058 ] 23674
|
||||
S L1_to_L2 [2947 2984 2973 2971 2929 2993 3006 3086 ] 23889
|
||||
S Trigger_L2_to_L1D [2 5 4 1 0 2 3 6 ] 23
|
||||
S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
|
||||
S Other_GETX [29 31 38 33 32 28 25 31 ] 247
|
||||
S Other_GETS [57 56 59 72 52 62 79 49 ] 486
|
||||
S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
S Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
S Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
O Load [0 0 0 0 0 0 0 0 ] 0
|
||||
O Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
O Store [1 0 0 0 0 0 0 0 ] 1
|
||||
O L2_Replacement [1037 1033 990 999 972 1001 1015 980 ] 8027
|
||||
O L1_to_L2 [204 188 202 199 190 218 217 198 ] 1616
|
||||
O Trigger_L2_to_L1D [0 2 0 1 0 1 0 2 ] 6
|
||||
O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
|
||||
O Other_GETX [7 8 8 5 3 11 9 5 ] 56
|
||||
O Other_GETS [9 14 12 12 13 9 9 13 ] 91
|
||||
O Merged_GETS [4 3 2 6 3 1 1 1 ] 21
|
||||
O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
O Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
O Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M Load [7 3 5 6 2 11 6 2 ] 42
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [5 5 2 5 2 9 1 2 ] 31
|
||||
M L2_Replacement [45647 45669 45641 45593 45746 45407 45688 45251 ] 364642
|
||||
M L1_to_L2 [46941 46960 46927 46865 46980 46700 46933 46507 ] 374813
|
||||
M Trigger_L2_to_L1D [49 40 60 51 41 55 37 40 ] 373
|
||||
M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
|
||||
M Other_GETX [529 518 538 533 520 540 502 539 ] 4219
|
||||
M Other_GETS [983 999 944 950 931 962 974 928 ] 7671
|
||||
M Merged_GETS [39 27 33 31 27 27 29 42 ] 255
|
||||
M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
M Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
M Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MM Load [4 8 2 6 6 4 3 7 ] 40
|
||||
MM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Store [0 5 1 2 4 4 1 2 ] 19
|
||||
MM L2_Replacement [25935 26320 26190 26373 26074 26156 26468 26109 ] 209625
|
||||
MM L1_to_L2 [26603 27029 26955 27088 26817 26905 27186 26874 ] 215457
|
||||
MM Trigger_L2_to_L1D [21 25 34 24 25 27 27 21 ] 204
|
||||
MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Other_GETX [296 298 301 320 334 308 279 308 ] 2444
|
||||
MM Other_GETS [481 549 562 521 548 558 561 599 ] 4379
|
||||
MM Merged_GETS [23 16 21 23 18 23 21 15 ] 160
|
||||
MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
MM Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IR Load [1 0 1 0 0 1 1 2 ] 6
|
||||
IR Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IR Store [2 0 0 2 0 3 1 1 ] 9
|
||||
IR L1_to_L2 [0 0 0 0 0 11 0 2 ] 13
|
||||
IR Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SR Load [2 3 4 1 0 1 2 4 ] 17
|
||||
SR Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SR Store [0 2 0 0 0 1 1 2 ] 6
|
||||
SR L1_to_L2 [0 3 0 0 0 0 0 13 ] 16
|
||||
SR Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
OR Load [0 1 0 1 0 1 0 2 ] 5
|
||||
OR Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
OR Store [0 1 0 0 0 0 0 0 ] 1
|
||||
OR L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
OR Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MR Load [32 27 42 33 20 37 27 31 ] 249
|
||||
MR Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MR Store [17 13 18 18 21 18 10 9 ] 124
|
||||
MR L1_to_L2 [91 56 102 86 95 89 59 56 ] 634
|
||||
MR Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MMR Load [14 17 26 16 16 16 18 14 ] 137
|
||||
MMR Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MMR Store [7 8 8 8 9 11 9 7 ] 67
|
||||
MMR L1_to_L2 [59 75 46 41 49 33 49 34 ] 386
|
||||
MMR Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IM L1_to_L2 [264282 266577 267890 269848 268056 268579 269306 265306 ] 2139844
|
||||
IM Other_GETX [7 12 10 15 9 15 10 13 ] 91
|
||||
IM Other_GETS [21 19 20 24 14 14 22 16 ] 150
|
||||
IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Ack [183448 186647 185973 187270 185299 185768 187652 185613 ] 1487670
|
||||
IM Data [985 1103 1041 1101 1105 1091 1048 1112 ] 8586
|
||||
IM Exclusive_Data [25729 26061 26018 26114 25848 25928 26272 25907 ] 207877
|
||||
IM Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM L1_to_L2 [0 11 0 0 0 1 7 0 ] 19
|
||||
SM Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ack [0 14 0 0 0 7 7 14 ] 42
|
||||
SM Data [0 2 0 0 0 1 1 2 ] 6
|
||||
SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
OM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
OM Ack [7 7 0 0 0 0 0 0 ] 14
|
||||
OM All_acks [0 0 0 0 0 0 0 0 ] 0
|
||||
OM All_acks_no_sharers [1 1 0 0 0 0 0 0 ] 2
|
||||
OM Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
ISM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM L1_to_L2 [2 0 0 0 1 0 14 1 ] 18
|
||||
ISM Ack [104 73 108 117 100 106 115 87 ] 810
|
||||
ISM All_acks_no_sharers [985 1105 1041 1101 1105 1092 1049 1114 ] 8592
|
||||
ISM Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M_W Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
M_W L1_to_L2 [539 550 404 533 478 492 525 425 ] 3946
|
||||
M_W Ack [1618 1714 1578 1607 1665 1631 1583 1553 ] 12949
|
||||
M_W All_acks_no_sharers [47224 47235 47179 47134 47252 46968 47208 46776 ] 376976
|
||||
M_W Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MM_W Load [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W Store [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_W L1_to_L2 [1079 875 817 808 798 840 931 893 ] 7041
|
||||
MM_W Ack [2578 2557 2465 2275 2427 2427 2583 2531 ] 19843
|
||||
MM_W All_acks_no_sharers [25729 26061 26018 26114 25848 25928 26272 25907 ] 207877
|
||||
MM_W Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IS L1_to_L2 [495283 496463 495139 490703 494908 493655 495921 494562 ] 3956634
|
||||
IS Other_GETX [18 25 17 24 21 22 15 15 ] 157
|
||||
IS Other_GETS [33 30 33 29 36 40 28 38 ] 267
|
||||
IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Ack [344673 344866 344538 344199 344619 343059 344891 342300 ] 2753145
|
||||
IS Shared_Ack [57 54 57 59 48 68 45 64 ] 452
|
||||
IS Data [1888 1940 1919 1926 1893 1908 1932 1968 ] 15374
|
||||
IS Shared_Data [1060 1048 1056 1053 1045 1094 1078 1123 ] 8557
|
||||
IS Exclusive_Data [47224 47235 47180 47134 47252 46968 47208 46776 ] 376977
|
||||
IS Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SS L1_to_L2 [1116 874 1194 1064 767 881 901 1161 ] 7958
|
||||
SS Ack [2952 3061 3007 2990 3014 2995 3121 3154 ] 24294
|
||||
SS Shared_Ack [4 4 4 4 3 6 5 4 ] 34
|
||||
SS All_acks [1114 1096 1109 1107 1091 1156 1120 1180 ] 8973
|
||||
SS All_acks_no_sharers [1834 1892 1866 1872 1847 1846 1890 1911 ] 14958
|
||||
SS Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
OI Load [0 1 2 0 0 0 0 0 ] 3
|
||||
OI Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
OI Store [0 0 0 0 0 0 0 0 ] 0
|
||||
OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
OI Other_GETX [0 0 2 0 0 0 0 0 ] 2
|
||||
OI Other_GETS [1 0 0 1 0 0 0 1 ] 3
|
||||
OI Merged_GETS [0 0 0 0 0 0 1 0 ] 1
|
||||
OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OI Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
OI Writeback_Ack [1085 1073 1027 1041 1020 1047 1077 1009 ] 8379
|
||||
OI Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MI Load [10 11 14 12 12 8 7 12 ] 86
|
||||
MI Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Store [7 4 4 12 9 7 8 7 ] 58
|
||||
MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Other_GETX [25 32 30 25 31 29 29 17 ] 218
|
||||
MI Other_GETS [47 39 39 42 48 46 63 29 ] 353
|
||||
MI Merged_GETS [1 1 0 0 0 0 0 0 ] 2
|
||||
MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [71509 71917 71762 71899 71741 71488 72063 71314 ] 573693
|
||||
MI Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
II Load [0 0 0 0 0 0 0 0 ] 0
|
||||
II Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
II Store [0 0 0 0 0 0 0 0 ] 0
|
||||
II L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
II L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
II Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
II Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
II Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
II Writeback_Ack [25 32 32 25 31 29 29 17 ] 220
|
||||
II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
II Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IT Load [0 0 1 0 0 0 0 2 ] 3
|
||||
IT Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IT Store [0 0 0 1 0 1 0 0 ] 2
|
||||
IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IT L1_to_L2 [0 0 0 1 0 11 9 3 ] 24
|
||||
IT Complete_L2_to_L1 [3 0 1 2 0 4 2 3 ] 15
|
||||
|
||||
ST Load [0 1 0 0 0 1 0 3 ] 5
|
||||
ST Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
ST Store [0 0 0 0 0 0 0 1 ] 1
|
||||
ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
ST L1_to_L2 [10 21 7 9 0 0 5 25 ] 77
|
||||
ST Complete_L2_to_L1 [2 5 4 1 0 2 3 6 ] 23
|
||||
|
||||
OT Load [0 0 0 0 0 0 0 2 ] 2
|
||||
OT Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
OT Store [0 0 0 0 0 0 0 0 ] 0
|
||||
OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
OT L1_to_L2 [0 0 0 6 0 0 0 0 ] 6
|
||||
OT Complete_L2_to_L1 [0 2 0 1 0 1 0 2 ] 6
|
||||
|
||||
MT Load [13 7 10 13 10 14 13 15 ] 95
|
||||
MT Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MT Store [6 9 9 9 9 7 5 2 ] 56
|
||||
MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
MT L1_to_L2 [179 117 164 171 115 155 80 166 ] 1147
|
||||
MT Complete_L2_to_L1 [49 40 60 51 41 55 37 40 ] 373
|
||||
|
||||
MMT Load [8 11 7 8 6 4 9 5 ] 58
|
||||
MMT Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MMT Store [4 3 4 2 5 3 5 2 ] 28
|
||||
MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
MMT L1_to_L2 [86 139 85 97 90 91 78 92 ] 758
|
||||
MMT Complete_L2_to_L1 [21 25 34 24 25 27 27 21 ] 204
|
||||
|
||||
MI_F Load [0 0 0 0 0 0 0 0 ] 0
|
||||
MI_F Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MI_F Store [0 0 0 0 0 0 0 0 ] 0
|
||||
MI_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
MI_F Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
MI_F Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MM_F Load [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Store [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Merged_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F All_acks [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_F Block_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IM_F Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Data [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
|
||||
IM_F Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
ISM_F Load [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F Store [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
|
||||
ISM_F Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SM_F Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Data [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
|
||||
SM_F Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
OM_F Load [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Store [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Other_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Other_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Merged_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Invalidate [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F All_acks [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
|
||||
OM_F Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MM_WF Load [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF Store [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF L2_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
|
||||
MM_WF Flush_line [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 811546
|
||||
memory_reads: 597507
|
||||
memory_writes: 214013
|
||||
memory_refreshes: 40249
|
||||
memory_total_request_delays: 49147842
|
||||
memory_delays_per_request: 60.5608
|
||||
memory_delays_in_input_queue: 408038
|
||||
memory_delays_behind_head_of_bank_queue: 19549348
|
||||
memory_delays_stalled_at_head_of_bank_queue: 29190456
|
||||
memory_stalls_for_bank_busy: 4395939
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 7180359
|
||||
memory_stalls_for_arbitration: 6011646
|
||||
memory_stalls_for_bus: 8156080
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 2068734
|
||||
memory_stalls_for_read_read_turnaround: 1377698
|
||||
accesses_per_bank: 25525 25047 25485 25568 25590 25517 25716 25410 25335 25484 25540 25414 25457 25303 25416 25361 25622 25433 25171 25194 25397 25498 25175 25106 25081 25088 24820 25599 25387 25331 25290 25186
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [220023 ] 220023
|
||||
GETS [406995 ] 406995
|
||||
PUT [585083 ] 585083
|
||||
Unblock [220 ] 220
|
||||
UnblockS [23931 ] 23931
|
||||
UnblockM [593445 ] 593445
|
||||
Writeback_Clean [8030 ] 8030
|
||||
Writeback_Dirty [349 ] 349
|
||||
Writeback_Exclusive_Clean [360015 ] 360015
|
||||
Writeback_Exclusive_Dirty [213674 ] 213674
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [597503 ] 597503
|
||||
Memory_Ack [214013 ] 214013
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [0 ] 0
|
||||
All_acks_and_shared_data [0 ] 0
|
||||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [439 ] 439
|
||||
GETF [0 ] 0
|
||||
PUTF [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NX GETX [61 ] 61
|
||||
NX GETS [97 ] 97
|
||||
NX PUT [8595 ] 8595
|
||||
NX Pf_Replacement [0 ] 0
|
||||
NX DMA_READ [0 ] 0
|
||||
NX DMA_WRITE [0 ] 0
|
||||
NX GETF [0 ] 0
|
||||
|
||||
NO GETX [6880 ] 6880
|
||||
NO GETS [12400 ] 12400
|
||||
NO PUT [573697 ] 573697
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [0 ] 0
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
S PUT [0 ] 0
|
||||
S Pf_Replacement [0 ] 0
|
||||
S DMA_READ [0 ] 0
|
||||
S DMA_WRITE [0 ] 0
|
||||
S GETF [0 ] 0
|
||||
|
||||
O GETX [8316 ] 8316
|
||||
O GETS [15375 ] 15375
|
||||
O PUT [0 ] 0
|
||||
O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [201220 ] 201220
|
||||
E GETS [372612 ] 372612
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [0 ] 0
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
O_R PUT [0 ] 0
|
||||
O_R Pf_Replacement [0 ] 0
|
||||
O_R DMA_READ [0 ] 0
|
||||
O_R DMA_WRITE [0 ] 0
|
||||
O_R Ack [0 ] 0
|
||||
O_R All_acks_and_data_no_sharers [0 ] 0
|
||||
O_R GETF [0 ] 0
|
||||
|
||||
S_R GETX [0 ] 0
|
||||
S_R GETS [0 ] 0
|
||||
S_R PUT [0 ] 0
|
||||
S_R Pf_Replacement [0 ] 0
|
||||
S_R DMA_READ [0 ] 0
|
||||
S_R DMA_WRITE [0 ] 0
|
||||
S_R Ack [0 ] 0
|
||||
S_R Data [0 ] 0
|
||||
S_R All_acks_and_data_no_sharers [0 ] 0
|
||||
S_R GETF [0 ] 0
|
||||
|
||||
NO_R GETX [0 ] 0
|
||||
NO_R GETS [0 ] 0
|
||||
NO_R PUT [0 ] 0
|
||||
NO_R Pf_Replacement [0 ] 0
|
||||
NO_R DMA_READ [0 ] 0
|
||||
NO_R DMA_WRITE [0 ] 0
|
||||
NO_R Ack [0 ] 0
|
||||
NO_R Data [0 ] 0
|
||||
NO_R Exclusive_Data [0 ] 0
|
||||
NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_R GETF [0 ] 0
|
||||
|
||||
NO_B GETX [205 ] 205
|
||||
NO_B GETS [439 ] 439
|
||||
NO_B PUT [2778 ] 2778
|
||||
NO_B UnblockS [8092 ] 8092
|
||||
NO_B UnblockM [592827 ] 592827
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
NO_B GETF [0 ] 0
|
||||
|
||||
NO_B_X GETX [0 ] 0
|
||||
NO_B_X GETS [0 ] 0
|
||||
NO_B_X PUT [0 ] 0
|
||||
NO_B_X UnblockS [4 ] 4
|
||||
NO_B_X UnblockM [201 ] 201
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
NO_B_X GETF [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
NO_B_S PUT [2 ] 2
|
||||
NO_B_S UnblockS [22 ] 22
|
||||
NO_B_S UnblockM [417 ] 417
|
||||
NO_B_S Pf_Replacement [0 ] 0
|
||||
NO_B_S DMA_READ [0 ] 0
|
||||
NO_B_S DMA_WRITE [0 ] 0
|
||||
NO_B_S GETF [0 ] 0
|
||||
|
||||
NO_B_S_W GETX [1 ] 1
|
||||
NO_B_S_W GETS [1 ] 1
|
||||
NO_B_S_W PUT [7 ] 7
|
||||
NO_B_S_W UnblockS [439 ] 439
|
||||
NO_B_S_W Pf_Replacement [0 ] 0
|
||||
NO_B_S_W DMA_READ [0 ] 0
|
||||
NO_B_S_W DMA_WRITE [0 ] 0
|
||||
NO_B_S_W All_Unblocks [439 ] 439
|
||||
NO_B_S_W GETF [0 ] 0
|
||||
|
||||
O_B GETX [9 ] 9
|
||||
O_B GETS [6 ] 6
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [15374 ] 15374
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
O_B GETF [0 ] 0
|
||||
|
||||
NO_B_W GETX [1957 ] 1957
|
||||
NO_B_W GETS [3492 ] 3492
|
||||
NO_B_W PUT [0 ] 0
|
||||
NO_B_W UnblockS [0 ] 0
|
||||
NO_B_W UnblockM [0 ] 0
|
||||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [582129 ] 582129
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [38 ] 38
|
||||
O_B_W GETS [103 ] 103
|
||||
O_B_W PUT [0 ] 0
|
||||
O_B_W UnblockS [0 ] 0
|
||||
O_B_W Pf_Replacement [0 ] 0
|
||||
O_B_W DMA_READ [0 ] 0
|
||||
O_B_W DMA_WRITE [0 ] 0
|
||||
O_B_W Memory_Data [15374 ] 15374
|
||||
O_B_W GETF [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W PUT [0 ] 0
|
||||
NO_W Pf_Replacement [0 ] 0
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W Memory_Data [0 ] 0
|
||||
NO_W GETF [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W PUT [0 ] 0
|
||||
O_W Pf_Replacement [0 ] 0
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W GETF [0 ] 0
|
||||
|
||||
NO_DW_B_W GETX [0 ] 0
|
||||
NO_DW_B_W GETS [0 ] 0
|
||||
NO_DW_B_W PUT [0 ] 0
|
||||
NO_DW_B_W Pf_Replacement [0 ] 0
|
||||
NO_DW_B_W DMA_READ [0 ] 0
|
||||
NO_DW_B_W DMA_WRITE [0 ] 0
|
||||
NO_DW_B_W Ack [0 ] 0
|
||||
NO_DW_B_W Data [0 ] 0
|
||||
NO_DW_B_W Exclusive_Data [0 ] 0
|
||||
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DW_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_W GETX [0 ] 0
|
||||
NO_DR_B_W GETS [0 ] 0
|
||||
NO_DR_B_W PUT [0 ] 0
|
||||
NO_DR_B_W Pf_Replacement [0 ] 0
|
||||
NO_DR_B_W DMA_READ [0 ] 0
|
||||
NO_DR_B_W DMA_WRITE [0 ] 0
|
||||
NO_DR_B_W Memory_Data [0 ] 0
|
||||
NO_DR_B_W Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Data [0 ] 0
|
||||
NO_DR_B_W Data [0 ] 0
|
||||
NO_DR_B_W Exclusive_Data [0 ] 0
|
||||
NO_DR_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_D GETX [0 ] 0
|
||||
NO_DR_B_D GETS [0 ] 0
|
||||
NO_DR_B_D PUT [0 ] 0
|
||||
NO_DR_B_D Pf_Replacement [0 ] 0
|
||||
NO_DR_B_D DMA_READ [0 ] 0
|
||||
NO_DR_B_D DMA_WRITE [0 ] 0
|
||||
NO_DR_B_D Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Data [0 ] 0
|
||||
NO_DR_B_D Data [0 ] 0
|
||||
NO_DR_B_D Exclusive_Data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B_D GETF [0 ] 0
|
||||
|
||||
NO_DR_B GETX [0 ] 0
|
||||
NO_DR_B GETS [0 ] 0
|
||||
NO_DR_B PUT [0 ] 0
|
||||
NO_DR_B Pf_Replacement [0 ] 0
|
||||
NO_DR_B DMA_READ [0 ] 0
|
||||
NO_DR_B DMA_WRITE [0 ] 0
|
||||
NO_DR_B Ack [0 ] 0
|
||||
NO_DR_B Shared_Ack [0 ] 0
|
||||
NO_DR_B Shared_Data [0 ] 0
|
||||
NO_DR_B Data [0 ] 0
|
||||
NO_DR_B Exclusive_Data [0 ] 0
|
||||
NO_DR_B All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B GETF [0 ] 0
|
||||
|
||||
NO_DW_W GETX [0 ] 0
|
||||
NO_DW_W GETS [0 ] 0
|
||||
NO_DW_W PUT [0 ] 0
|
||||
NO_DW_W Pf_Replacement [0 ] 0
|
||||
NO_DW_W DMA_READ [0 ] 0
|
||||
NO_DW_W DMA_WRITE [0 ] 0
|
||||
NO_DW_W Memory_Ack [0 ] 0
|
||||
NO_DW_W GETF [0 ] 0
|
||||
|
||||
O_DR_B_W GETX [0 ] 0
|
||||
O_DR_B_W GETS [0 ] 0
|
||||
O_DR_B_W PUT [0 ] 0
|
||||
O_DR_B_W Pf_Replacement [0 ] 0
|
||||
O_DR_B_W DMA_READ [0 ] 0
|
||||
O_DR_B_W DMA_WRITE [0 ] 0
|
||||
O_DR_B_W Memory_Data [0 ] 0
|
||||
O_DR_B_W Ack [0 ] 0
|
||||
O_DR_B_W Shared_Ack [0 ] 0
|
||||
O_DR_B_W GETF [0 ] 0
|
||||
|
||||
O_DR_B GETX [0 ] 0
|
||||
O_DR_B GETS [0 ] 0
|
||||
O_DR_B PUT [0 ] 0
|
||||
O_DR_B Pf_Replacement [0 ] 0
|
||||
O_DR_B DMA_READ [0 ] 0
|
||||
O_DR_B DMA_WRITE [0 ] 0
|
||||
O_DR_B Ack [0 ] 0
|
||||
O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [295 ] 295
|
||||
WB GETS [514 ] 514
|
||||
WB PUT [4 ] 4
|
||||
WB Unblock [220 ] 220
|
||||
WB Writeback_Clean [8030 ] 8030
|
||||
WB Writeback_Dirty [349 ] 349
|
||||
WB Writeback_Exclusive_Clean [360015 ] 360015
|
||||
WB Writeback_Exclusive_Dirty [213674 ] 213674
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
WB GETF [0 ] 0
|
||||
|
||||
WB_O_W GETX [0 ] 0
|
||||
WB_O_W GETS [3 ] 3
|
||||
WB_O_W PUT [0 ] 0
|
||||
WB_O_W Pf_Replacement [0 ] 0
|
||||
WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [348 ] 348
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [1041 ] 1041
|
||||
WB_E_W GETS [1953 ] 1953
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [213665 ] 213665
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
NO_F GETS [0 ] 0
|
||||
NO_F PUT [0 ] 0
|
||||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [0 ] 0
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
NO_F_W PUT [0 ] 0
|
||||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.005796 # Nu
|
|||
sim_ticks 5795833 # Number of ticks simulated
|
||||
final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 39688 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251648 # Number of bytes of host memory used
|
||||
host_seconds 146.03 # Real time elapsed on the host
|
||||
host_tick_rate 58867 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292456 # Number of bytes of host memory used
|
||||
host_seconds 98.46 # Real time elapsed on the host
|
||||
system.funcbus.throughput 0 # Throughput (bytes/s)
|
||||
system.funcbus.data_through_bus 0 # Total data (bytes)
|
||||
system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits
|
||||
|
|
@ -81,6 +81,24 @@ system.ruby.l1_cntrl3.L1Icache.demand_accesses 0
|
|||
system.ruby.l1_cntrl3.L2cache.demand_hits 77 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl3.L2cache.demand_misses 77331 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl3.L2cache.demand_accesses 77408 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 811546 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 597507 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 214013 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 40249 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 29190456 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 408038 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 19549348 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 49147842 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 60.560759 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 4395939 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 8156080 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2068734 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1377698 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 6011646 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 7180359 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 25525 3.15% 3.15% | 25047 3.09% 6.23% | 25485 3.14% 9.37% | 25568 3.15% 12.52% | 25590 3.15% 15.68% | 25517 3.14% 18.82% | 25716 3.17% 21.99% | 25410 3.13% 25.12% | 25335 3.12% 28.24% | 25484 3.14% 31.38% | 25540 3.15% 34.53% | 25414 3.13% 37.66% | 25457 3.14% 40.80% | 25303 3.12% 43.92% | 25416 3.13% 47.05% | 25361 3.13% 50.17% | 25622 3.16% 53.33% | 25433 3.13% 56.46% | 25171 3.10% 59.56% | 25194 3.10% 62.67% | 25397 3.13% 65.80% | 25498 3.14% 68.94% | 25175 3.10% 72.04% | 25106 3.09% 75.14% | 25081 3.09% 78.23% | 25088 3.09% 81.32% | 24820 3.06% 84.38% | 25599 3.15% 87.53% | 25387 3.13% 90.66% | 25331 3.12% 93.78% | 25290 3.12% 96.90% | 25186 3.10% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 811546 # Number of accesses per bank
|
||||
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
|
|
@ -108,5 +126,458 @@ system.cpu6.num_copies 0 # nu
|
|||
system.cpu7.num_reads 99102 # number of read accesses completed
|
||||
system.cpu7.num_writes 53848 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.ruby.l1_cntrl0.Load | 50266 12.51% 12.51% | 50315 12.53% 25.04% | 50271 12.52% 37.56% | 50212 12.50% 50.06% | 50263 12.51% 62.57% | 50069 12.47% 75.04% | 50306 12.52% 87.56% | 49970 12.44% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 401672
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 26762 12.34% 12.34% | 27215 12.55% 24.89% | 27106 12.50% 37.39% | 27272 12.58% 49.96% | 27014 12.46% 62.42% | 27080 12.49% 74.91% | 27361 12.62% 87.52% | 27054 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 216864
|
||||
|
||||
system.ruby.l1_cntrl0.L2_Replacement | 76877 12.45% 12.45% | 77378 12.53% 24.99% | 77204 12.51% 37.50% | 77319 12.53% 50.02% | 77135 12.50% 62.52% | 76978 12.47% 74.99% | 77528 12.56% 87.55% | 76877 12.45% 100.00%
|
||||
system.ruby.l1_cntrl0.L2_Replacement::total 617296
|
||||
|
||||
system.ruby.l1_cntrl0.L1_to_L2 | 839684 12.46% 12.46% | 843217 12.52% 24.98% | 843158 12.52% 37.50% | 840771 12.48% 49.98% | 842565 12.51% 62.49% | 841910 12.50% 74.98% | 845488 12.55% 87.54% | 839694 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.L1_to_L2::total 6736487
|
||||
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1D | 75 12.08% 12.08% | 72 11.59% 23.67% | 99 15.94% 39.61% | 79 12.72% 52.33% | 66 10.63% 62.96% | 89 14.33% 77.29% | 69 11.11% 88.41% | 72 11.59% 100.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1D::total 621
|
||||
|
||||
system.ruby.l1_cntrl0.Complete_L2_to_L1 | 75 12.08% 12.08% | 72 11.59% 23.67% | 99 15.94% 39.61% | 79 12.72% 52.33% | 66 10.63% 62.96% | 89 14.33% 77.29% | 69 11.11% 88.41% | 72 11.59% 100.00%
|
||||
system.ruby.l1_cntrl0.Complete_L2_to_L1::total 621
|
||||
|
||||
system.ruby.l1_cntrl0.Other_GETX | 189761 12.52% 12.52% | 189309 12.49% 25.02% | 189417 12.50% 37.52% | 189262 12.49% 50.01% | 189522 12.51% 62.51% | 189457 12.50% 75.01% | 189156 12.48% 87.50% | 189455 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.Other_GETX::total 1515339
|
||||
|
||||
system.ruby.l1_cntrl0.Other_GETS | 350360 12.50% 12.50% | 350304 12.50% 24.99% | 350380 12.50% 37.49% | 350430 12.50% 49.99% | 350354 12.50% 62.49% | 350578 12.51% 75.00% | 350311 12.50% 87.49% | 350671 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Other_GETS::total 2803388
|
||||
|
||||
system.ruby.l1_cntrl0.Merged_GETS | 67 15.26% 15.26% | 47 10.71% 25.97% | 56 12.76% 38.72% | 60 13.67% 52.39% | 48 10.93% 63.33% | 51 11.62% 74.94% | 52 11.85% 86.79% | 58 13.21% 100.00%
|
||||
system.ruby.l1_cntrl0.Merged_GETS::total 439
|
||||
|
||||
system.ruby.l1_cntrl0.Ack | 535380 12.45% 12.45% | 538939 12.54% 24.99% | 537669 12.51% 37.50% | 538458 12.53% 50.02% | 537124 12.49% 62.52% | 535993 12.47% 74.99% | 539952 12.56% 87.55% | 535252 12.45% 100.00%
|
||||
system.ruby.l1_cntrl0.Ack::total 4298767
|
||||
|
||||
system.ruby.l1_cntrl0.Shared_Ack | 61 12.55% 12.55% | 58 11.93% 24.49% | 61 12.55% 37.04% | 63 12.96% 50.00% | 51 10.49% 60.49% | 74 15.23% 75.72% | 50 10.29% 86.01% | 68 13.99% 100.00%
|
||||
system.ruby.l1_cntrl0.Shared_Ack::total 486
|
||||
|
||||
system.ruby.l1_cntrl0.Data | 2873 11.99% 11.99% | 3045 12.71% 24.69% | 2960 12.35% 37.04% | 3027 12.63% 49.67% | 2998 12.51% 62.18% | 3000 12.52% 74.70% | 2981 12.44% 87.14% | 3082 12.86% 100.00%
|
||||
system.ruby.l1_cntrl0.Data::total 23966
|
||||
|
||||
system.ruby.l1_cntrl0.Shared_Data | 1060 12.39% 12.39% | 1048 12.25% 24.63% | 1056 12.34% 36.98% | 1053 12.31% 49.28% | 1045 12.21% 61.49% | 1094 12.78% 74.28% | 1078 12.60% 86.88% | 1123 13.12% 100.00%
|
||||
system.ruby.l1_cntrl0.Shared_Data::total 8557
|
||||
|
||||
system.ruby.l1_cntrl0.Exclusive_Data | 72953 12.47% 12.47% | 73296 12.53% 25.01% | 73198 12.52% 37.52% | 73248 12.52% 50.05% | 73100 12.50% 62.54% | 72896 12.46% 75.01% | 73480 12.56% 87.57% | 72683 12.43% 100.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data::total 584854
|
||||
|
||||
system.ruby.l1_cntrl0.Writeback_Ack | 72619 12.47% 12.47% | 73022 12.54% 25.01% | 72821 12.51% 37.52% | 72965 12.53% 50.05% | 72792 12.50% 62.55% | 72564 12.46% 75.01% | 73169 12.57% 87.58% | 72340 12.42% 100.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack::total 582292
|
||||
|
||||
system.ruby.l1_cntrl0.All_acks | 1114 12.42% 12.42% | 1096 12.21% 24.63% | 1109 12.36% 36.99% | 1107 12.34% 49.33% | 1091 12.16% 61.48% | 1156 12.88% 74.37% | 1120 12.48% 86.85% | 1180 13.15% 100.00%
|
||||
system.ruby.l1_cntrl0.All_acks::total 8973
|
||||
|
||||
system.ruby.l1_cntrl0.All_acks_no_sharers | 75773 12.45% 12.45% | 76294 12.54% 24.99% | 76104 12.51% 37.50% | 76221 12.53% 50.03% | 76052 12.50% 62.53% | 75834 12.46% 75.00% | 76419 12.56% 87.56% | 75708 12.44% 100.00%
|
||||
system.ruby.l1_cntrl0.All_acks_no_sharers::total 608405
|
||||
|
||||
system.ruby.l1_cntrl0.I.Load | 50174 12.51% 12.51% | 50224 12.53% 25.04% | 50155 12.51% 37.55% | 50116 12.50% 50.05% | 50191 12.52% 62.57% | 49971 12.46% 75.04% | 50219 12.53% 87.56% | 49868 12.44% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Load::total 400918
|
||||
|
||||
system.ruby.l1_cntrl0.I.Store | 26713 12.34% 12.34% | 27165 12.55% 24.89% | 27060 12.50% 37.39% | 27213 12.57% 49.96% | 26955 12.45% 62.42% | 27016 12.48% 74.90% | 27320 12.62% 87.52% | 27019 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Store::total 216461
|
||||
|
||||
system.ruby.l1_cntrl0.I.L2_Replacement | 1339 11.82% 11.82% | 1403 12.39% 24.21% | 1446 12.76% 36.97% | 1410 12.45% 49.42% | 1437 12.69% 62.10% | 1441 12.72% 74.82% | 1373 12.12% 86.94% | 1479 13.06% 100.00%
|
||||
system.ruby.l1_cntrl0.I.L2_Replacement::total 11328
|
||||
|
||||
system.ruby.l1_cntrl0.I.L1_to_L2 | 263 12.00% 12.00% | 295 13.46% 25.47% | 253 11.55% 37.02% | 281 12.83% 49.84% | 292 13.33% 63.17% | 256 11.68% 74.85% | 261 11.91% 86.76% | 290 13.24% 100.00%
|
||||
system.ruby.l1_cntrl0.I.L1_to_L2::total 2191
|
||||
|
||||
system.ruby.l1_cntrl0.I.Trigger_L2_to_L1D | 3 20.00% 20.00% | 0 0.00% 20.00% | 1 6.67% 26.67% | 2 13.33% 40.00% | 0 0.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Trigger_L2_to_L1D::total 15
|
||||
|
||||
system.ruby.l1_cntrl0.I.Other_GETX | 188850 12.52% 12.52% | 188385 12.49% 25.02% | 188473 12.50% 37.52% | 188307 12.49% 50.00% | 188572 12.51% 62.51% | 188504 12.50% 75.01% | 188287 12.49% 87.50% | 188527 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Other_GETX::total 1507905
|
||||
|
||||
system.ruby.l1_cntrl0.I.Other_GETS | 348728 12.50% 12.50% | 348598 12.49% 24.99% | 348711 12.50% 37.49% | 348779 12.50% 49.99% | 348712 12.50% 62.49% | 348887 12.50% 75.00% | 348575 12.49% 87.49% | 348998 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Other_GETS::total 2789988
|
||||
|
||||
system.ruby.l1_cntrl0.S.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Load::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.S.L2_Replacement | 2919 12.33% 12.33% | 2953 12.47% 24.80% | 2937 12.41% 37.21% | 2944 12.44% 49.65% | 2906 12.28% 61.92% | 2973 12.56% 74.48% | 2984 12.60% 87.08% | 3058 12.92% 100.00%
|
||||
system.ruby.l1_cntrl0.S.L2_Replacement::total 23674
|
||||
|
||||
system.ruby.l1_cntrl0.S.L1_to_L2 | 2947 12.34% 12.34% | 2984 12.49% 24.83% | 2973 12.45% 37.27% | 2971 12.44% 49.71% | 2929 12.26% 61.97% | 2993 12.53% 74.50% | 3006 12.58% 87.08% | 3086 12.92% 100.00%
|
||||
system.ruby.l1_cntrl0.S.L1_to_L2::total 23889
|
||||
|
||||
system.ruby.l1_cntrl0.S.Trigger_L2_to_L1D | 2 8.70% 8.70% | 5 21.74% 30.43% | 4 17.39% 47.83% | 1 4.35% 52.17% | 0 0.00% 52.17% | 2 8.70% 60.87% | 3 13.04% 73.91% | 6 26.09% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Trigger_L2_to_L1D::total 23
|
||||
|
||||
system.ruby.l1_cntrl0.S.Other_GETX | 29 11.74% 11.74% | 31 12.55% 24.29% | 38 15.38% 39.68% | 33 13.36% 53.04% | 32 12.96% 65.99% | 28 11.34% 77.33% | 25 10.12% 87.45% | 31 12.55% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Other_GETX::total 247
|
||||
|
||||
system.ruby.l1_cntrl0.S.Other_GETS | 57 11.73% 11.73% | 56 11.52% 23.25% | 59 12.14% 35.39% | 72 14.81% 50.21% | 52 10.70% 60.91% | 62 12.76% 73.66% | 79 16.26% 89.92% | 49 10.08% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Other_GETS::total 486
|
||||
|
||||
system.ruby.l1_cntrl0.O.Store | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Store::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.O.L2_Replacement | 1037 12.92% 12.92% | 1033 12.87% 25.79% | 990 12.33% 38.12% | 999 12.45% 50.57% | 972 12.11% 62.68% | 1001 12.47% 75.15% | 1015 12.64% 87.79% | 980 12.21% 100.00%
|
||||
system.ruby.l1_cntrl0.O.L2_Replacement::total 8027
|
||||
|
||||
system.ruby.l1_cntrl0.O.L1_to_L2 | 204 12.62% 12.62% | 188 11.63% 24.26% | 202 12.50% 36.76% | 199 12.31% 49.07% | 190 11.76% 60.83% | 218 13.49% 74.32% | 217 13.43% 87.75% | 198 12.25% 100.00%
|
||||
system.ruby.l1_cntrl0.O.L1_to_L2::total 1616
|
||||
|
||||
system.ruby.l1_cntrl0.O.Trigger_L2_to_L1D | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Trigger_L2_to_L1D::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.O.Other_GETX | 7 12.50% 12.50% | 8 14.29% 26.79% | 8 14.29% 41.07% | 5 8.93% 50.00% | 3 5.36% 55.36% | 11 19.64% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Other_GETX::total 56
|
||||
|
||||
system.ruby.l1_cntrl0.O.Other_GETS | 9 9.89% 9.89% | 14 15.38% 25.27% | 12 13.19% 38.46% | 12 13.19% 51.65% | 13 14.29% 65.93% | 9 9.89% 75.82% | 9 9.89% 85.71% | 13 14.29% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Other_GETS::total 91
|
||||
|
||||
system.ruby.l1_cntrl0.O.Merged_GETS | 4 19.05% 19.05% | 3 14.29% 33.33% | 2 9.52% 42.86% | 6 28.57% 71.43% | 3 14.29% 85.71% | 1 4.76% 90.48% | 1 4.76% 95.24% | 1 4.76% 100.00%
|
||||
system.ruby.l1_cntrl0.O.Merged_GETS::total 21
|
||||
|
||||
system.ruby.l1_cntrl0.M.Load | 7 16.67% 16.67% | 3 7.14% 23.81% | 5 11.90% 35.71% | 6 14.29% 50.00% | 2 4.76% 54.76% | 11 26.19% 80.95% | 6 14.29% 95.24% | 2 4.76% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Load::total 42
|
||||
|
||||
system.ruby.l1_cntrl0.M.Store | 5 16.13% 16.13% | 5 16.13% 32.26% | 2 6.45% 38.71% | 5 16.13% 54.84% | 2 6.45% 61.29% | 9 29.03% 90.32% | 1 3.23% 93.55% | 2 6.45% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 31
|
||||
|
||||
system.ruby.l1_cntrl0.M.L2_Replacement | 45647 12.52% 12.52% | 45669 12.52% 25.04% | 45641 12.52% 37.56% | 45593 12.50% 50.06% | 45746 12.55% 62.61% | 45407 12.45% 75.06% | 45688 12.53% 87.59% | 45251 12.41% 100.00%
|
||||
system.ruby.l1_cntrl0.M.L2_Replacement::total 364642
|
||||
|
||||
system.ruby.l1_cntrl0.M.L1_to_L2 | 46941 12.52% 12.52% | 46960 12.53% 25.05% | 46927 12.52% 37.57% | 46865 12.50% 50.08% | 46980 12.53% 62.61% | 46700 12.46% 75.07% | 46933 12.52% 87.59% | 46507 12.41% 100.00%
|
||||
system.ruby.l1_cntrl0.M.L1_to_L2::total 374813
|
||||
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D | 49 13.14% 13.14% | 40 10.72% 23.86% | 60 16.09% 39.95% | 51 13.67% 53.62% | 41 10.99% 64.61% | 55 14.75% 79.36% | 37 9.92% 89.28% | 40 10.72% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D::total 373
|
||||
|
||||
system.ruby.l1_cntrl0.M.Other_GETX | 529 12.54% 12.54% | 518 12.28% 24.82% | 538 12.75% 37.57% | 533 12.63% 50.20% | 520 12.33% 62.53% | 540 12.80% 75.33% | 502 11.90% 87.22% | 539 12.78% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Other_GETX::total 4219
|
||||
|
||||
system.ruby.l1_cntrl0.M.Other_GETS | 983 12.81% 12.81% | 999 13.02% 25.84% | 944 12.31% 38.14% | 950 12.38% 50.53% | 931 12.14% 62.66% | 962 12.54% 75.21% | 974 12.70% 87.90% | 928 12.10% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Other_GETS::total 7671
|
||||
|
||||
system.ruby.l1_cntrl0.M.Merged_GETS | 39 15.29% 15.29% | 27 10.59% 25.88% | 33 12.94% 38.82% | 31 12.16% 50.98% | 27 10.59% 61.57% | 27 10.59% 72.16% | 29 11.37% 83.53% | 42 16.47% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Merged_GETS::total 255
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Load | 4 10.00% 10.00% | 8 20.00% 30.00% | 2 5.00% 35.00% | 6 15.00% 50.00% | 6 15.00% 65.00% | 4 10.00% 75.00% | 3 7.50% 82.50% | 7 17.50% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Load::total 40
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Store | 0 0.00% 0.00% | 5 26.32% 26.32% | 1 5.26% 31.58% | 2 10.53% 42.11% | 4 21.05% 63.16% | 4 21.05% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Store::total 19
|
||||
|
||||
system.ruby.l1_cntrl0.MM.L2_Replacement | 25935 12.37% 12.37% | 26320 12.56% 24.93% | 26190 12.49% 37.42% | 26373 12.58% 50.00% | 26074 12.44% 62.44% | 26156 12.48% 74.92% | 26468 12.63% 87.54% | 26109 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.L2_Replacement::total 209625
|
||||
|
||||
system.ruby.l1_cntrl0.MM.L1_to_L2 | 26603 12.35% 12.35% | 27029 12.54% 24.89% | 26955 12.51% 37.40% | 27088 12.57% 49.98% | 26817 12.45% 62.42% | 26905 12.49% 74.91% | 27186 12.62% 87.53% | 26874 12.47% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_to_L2::total 215457
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D | 21 10.29% 10.29% | 25 12.25% 22.55% | 34 16.67% 39.22% | 24 11.76% 50.98% | 25 12.25% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D::total 204
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Other_GETX | 296 12.11% 12.11% | 298 12.19% 24.30% | 301 12.32% 36.62% | 320 13.09% 49.71% | 334 13.67% 63.38% | 308 12.60% 75.98% | 279 11.42% 87.40% | 308 12.60% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Other_GETX::total 2444
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Other_GETS | 481 10.98% 10.98% | 549 12.54% 23.52% | 562 12.83% 36.36% | 521 11.90% 48.25% | 548 12.51% 60.77% | 558 12.74% 73.51% | 561 12.81% 86.32% | 599 13.68% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Other_GETS::total 4379
|
||||
|
||||
system.ruby.l1_cntrl0.MM.Merged_GETS | 23 14.37% 14.37% | 16 10.00% 24.38% | 21 13.12% 37.50% | 23 14.37% 51.88% | 18 11.25% 63.13% | 23 14.37% 77.50% | 21 13.12% 90.63% | 15 9.38% 100.00%
|
||||
system.ruby.l1_cntrl0.MM.Merged_GETS::total 160
|
||||
|
||||
system.ruby.l1_cntrl0.IR.Load | 1 16.67% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.IR.Load::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.IR.Store | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 3 33.33% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00%
|
||||
system.ruby.l1_cntrl0.IR.Store::total 9
|
||||
|
||||
system.ruby.l1_cntrl0.IR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 84.62% 84.62% | 0 0.00% 84.62% | 2 15.38% 100.00%
|
||||
system.ruby.l1_cntrl0.IR.L1_to_L2::total 13
|
||||
|
||||
system.ruby.l1_cntrl0.SR.Load | 2 11.76% 11.76% | 3 17.65% 29.41% | 4 23.53% 52.94% | 1 5.88% 58.82% | 0 0.00% 58.82% | 1 5.88% 64.71% | 2 11.76% 76.47% | 4 23.53% 100.00%
|
||||
system.ruby.l1_cntrl0.SR.Load::total 17
|
||||
|
||||
system.ruby.l1_cntrl0.SR.Store | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.SR.Store::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.SR.L1_to_L2 | 0 0.00% 0.00% | 3 18.75% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 13 81.25% 100.00%
|
||||
system.ruby.l1_cntrl0.SR.L1_to_L2::total 16
|
||||
|
||||
system.ruby.l1_cntrl0.OR.Load | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OR.Load::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.OR.Store | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OR.Store::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.MR.Load | 32 12.85% 12.85% | 27 10.84% 23.69% | 42 16.87% 40.56% | 33 13.25% 53.82% | 20 8.03% 61.85% | 37 14.86% 76.71% | 27 10.84% 87.55% | 31 12.45% 100.00%
|
||||
system.ruby.l1_cntrl0.MR.Load::total 249
|
||||
|
||||
system.ruby.l1_cntrl0.MR.Store | 17 13.71% 13.71% | 13 10.48% 24.19% | 18 14.52% 38.71% | 18 14.52% 53.23% | 21 16.94% 70.16% | 18 14.52% 84.68% | 10 8.06% 92.74% | 9 7.26% 100.00%
|
||||
system.ruby.l1_cntrl0.MR.Store::total 124
|
||||
|
||||
system.ruby.l1_cntrl0.MR.L1_to_L2 | 91 14.35% 14.35% | 56 8.83% 23.19% | 102 16.09% 39.27% | 86 13.56% 52.84% | 95 14.98% 67.82% | 89 14.04% 81.86% | 59 9.31% 91.17% | 56 8.83% 100.00%
|
||||
system.ruby.l1_cntrl0.MR.L1_to_L2::total 634
|
||||
|
||||
system.ruby.l1_cntrl0.MMR.Load | 14 10.22% 10.22% | 17 12.41% 22.63% | 26 18.98% 41.61% | 16 11.68% 53.28% | 16 11.68% 64.96% | 16 11.68% 76.64% | 18 13.14% 89.78% | 14 10.22% 100.00%
|
||||
system.ruby.l1_cntrl0.MMR.Load::total 137
|
||||
|
||||
system.ruby.l1_cntrl0.MMR.Store | 7 10.45% 10.45% | 8 11.94% 22.39% | 8 11.94% 34.33% | 8 11.94% 46.27% | 9 13.43% 59.70% | 11 16.42% 76.12% | 9 13.43% 89.55% | 7 10.45% 100.00%
|
||||
system.ruby.l1_cntrl0.MMR.Store::total 67
|
||||
|
||||
system.ruby.l1_cntrl0.MMR.L1_to_L2 | 59 15.28% 15.28% | 75 19.43% 34.72% | 46 11.92% 46.63% | 41 10.62% 57.25% | 49 12.69% 69.95% | 33 8.55% 78.50% | 49 12.69% 91.19% | 34 8.81% 100.00%
|
||||
system.ruby.l1_cntrl0.MMR.L1_to_L2::total 386
|
||||
|
||||
system.ruby.l1_cntrl0.IM.L1_to_L2 | 264282 12.35% 12.35% | 266577 12.46% 24.81% | 267890 12.52% 37.33% | 269848 12.61% 49.94% | 268056 12.53% 62.46% | 268579 12.55% 75.02% | 269306 12.59% 87.60% | 265306 12.40% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_to_L2::total 2139844
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Other_GETX | 7 7.69% 7.69% | 12 13.19% 20.88% | 10 10.99% 31.87% | 15 16.48% 48.35% | 9 9.89% 58.24% | 15 16.48% 74.73% | 10 10.99% 85.71% | 13 14.29% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Other_GETX::total 91
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Other_GETS | 21 14.00% 14.00% | 19 12.67% 26.67% | 20 13.33% 40.00% | 24 16.00% 56.00% | 14 9.33% 65.33% | 14 9.33% 74.67% | 22 14.67% 89.33% | 16 10.67% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Other_GETS::total 150
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Ack | 183448 12.33% 12.33% | 186647 12.55% 24.88% | 185973 12.50% 37.38% | 187270 12.59% 49.97% | 185299 12.46% 62.42% | 185768 12.49% 74.91% | 187652 12.61% 87.52% | 185613 12.48% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Ack::total 1487670
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data | 985 11.47% 11.47% | 1103 12.85% 24.32% | 1041 12.12% 36.44% | 1101 12.82% 49.27% | 1105 12.87% 62.14% | 1091 12.71% 74.84% | 1048 12.21% 87.05% | 1112 12.95% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data::total 8586
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data | 25729 12.38% 12.38% | 26061 12.54% 24.91% | 26018 12.52% 37.43% | 26114 12.56% 49.99% | 25848 12.43% 62.43% | 25928 12.47% 74.90% | 26272 12.64% 87.54% | 25907 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data::total 207877
|
||||
|
||||
system.ruby.l1_cntrl0.SM.L1_to_L2 | 0 0.00% 0.00% | 11 57.89% 57.89% | 0 0.00% 57.89% | 0 0.00% 57.89% | 0 0.00% 57.89% | 1 5.26% 63.16% | 7 36.84% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.L1_to_L2::total 19
|
||||
|
||||
system.ruby.l1_cntrl0.SM.Ack | 0 0.00% 0.00% | 14 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 7 16.67% 50.00% | 7 16.67% 66.67% | 14 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.Ack::total 42
|
||||
|
||||
system.ruby.l1_cntrl0.SM.Data | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.SM.Data::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.OM.Ack | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.Ack::total 14
|
||||
|
||||
system.ruby.l1_cntrl0.OM.All_acks_no_sharers | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OM.All_acks_no_sharers::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.ISM.L1_to_L2 | 2 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 5.56% 16.67% | 0 0.00% 16.67% | 14 77.78% 94.44% | 1 5.56% 100.00%
|
||||
system.ruby.l1_cntrl0.ISM.L1_to_L2::total 18
|
||||
|
||||
system.ruby.l1_cntrl0.ISM.Ack | 104 12.84% 12.84% | 73 9.01% 21.85% | 108 13.33% 35.19% | 117 14.44% 49.63% | 100 12.35% 61.98% | 106 13.09% 75.06% | 115 14.20% 89.26% | 87 10.74% 100.00%
|
||||
system.ruby.l1_cntrl0.ISM.Ack::total 810
|
||||
|
||||
system.ruby.l1_cntrl0.ISM.All_acks_no_sharers | 985 11.46% 11.46% | 1105 12.86% 24.32% | 1041 12.12% 36.44% | 1101 12.81% 49.26% | 1105 12.86% 62.12% | 1092 12.71% 74.83% | 1049 12.21% 87.03% | 1114 12.97% 100.00%
|
||||
system.ruby.l1_cntrl0.ISM.All_acks_no_sharers::total 8592
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.L1_to_L2 | 539 13.66% 13.66% | 550 13.94% 27.60% | 404 10.24% 37.84% | 533 13.51% 51.34% | 478 12.11% 63.46% | 492 12.47% 75.92% | 525 13.30% 89.23% | 425 10.77% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_to_L2::total 3946
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.Ack | 1618 12.50% 12.50% | 1714 13.24% 25.73% | 1578 12.19% 37.92% | 1607 12.41% 50.33% | 1665 12.86% 63.19% | 1631 12.60% 75.78% | 1583 12.22% 88.01% | 1553 11.99% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.Ack::total 12949
|
||||
|
||||
system.ruby.l1_cntrl0.M_W.All_acks_no_sharers | 47224 12.53% 12.53% | 47235 12.53% 25.06% | 47179 12.52% 37.57% | 47134 12.50% 50.08% | 47252 12.53% 62.61% | 46968 12.46% 75.07% | 47208 12.52% 87.59% | 46776 12.41% 100.00%
|
||||
system.ruby.l1_cntrl0.M_W.All_acks_no_sharers::total 376976
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.L1_to_L2 | 1079 15.32% 15.32% | 875 12.43% 27.75% | 817 11.60% 39.36% | 808 11.48% 50.83% | 798 11.33% 62.16% | 840 11.93% 74.09% | 931 13.22% 87.32% | 893 12.68% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_to_L2::total 7041
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.Ack | 2578 12.99% 12.99% | 2557 12.89% 25.88% | 2465 12.42% 38.30% | 2275 11.47% 49.77% | 2427 12.23% 62.00% | 2427 12.23% 74.23% | 2583 13.02% 87.24% | 2531 12.76% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Ack::total 19843
|
||||
|
||||
system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers | 25729 12.38% 12.38% | 26061 12.54% 24.91% | 26018 12.52% 37.43% | 26114 12.56% 49.99% | 25848 12.43% 62.43% | 25928 12.47% 74.90% | 26272 12.64% 87.54% | 25907 12.46% 100.00%
|
||||
system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers::total 207877
|
||||
|
||||
system.ruby.l1_cntrl0.IS.L1_to_L2 | 495283 12.52% 12.52% | 496463 12.55% 25.07% | 495139 12.51% 37.58% | 490703 12.40% 49.98% | 494908 12.51% 62.49% | 493655 12.48% 74.97% | 495921 12.53% 87.50% | 494562 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_to_L2::total 3956634
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Other_GETX | 18 11.46% 11.46% | 25 15.92% 27.39% | 17 10.83% 38.22% | 24 15.29% 53.50% | 21 13.38% 66.88% | 22 14.01% 80.89% | 15 9.55% 90.45% | 15 9.55% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Other_GETX::total 157
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Other_GETS | 33 12.36% 12.36% | 30 11.24% 23.60% | 33 12.36% 35.96% | 29 10.86% 46.82% | 36 13.48% 60.30% | 40 14.98% 75.28% | 28 10.49% 85.77% | 38 14.23% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Other_GETS::total 267
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Ack | 344673 12.52% 12.52% | 344866 12.53% 25.05% | 344538 12.51% 37.56% | 344199 12.50% 50.06% | 344619 12.52% 62.58% | 343059 12.46% 75.04% | 344891 12.53% 87.57% | 342300 12.43% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Ack::total 2753145
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Shared_Ack | 57 12.61% 12.61% | 54 11.95% 24.56% | 57 12.61% 37.17% | 59 13.05% 50.22% | 48 10.62% 60.84% | 68 15.04% 75.88% | 45 9.96% 85.84% | 64 14.16% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Shared_Ack::total 452
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data | 1888 12.28% 12.28% | 1940 12.62% 24.90% | 1919 12.48% 37.38% | 1926 12.53% 49.91% | 1893 12.31% 62.22% | 1908 12.41% 74.63% | 1932 12.57% 87.20% | 1968 12.80% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data::total 15374
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Shared_Data | 1060 12.39% 12.39% | 1048 12.25% 24.63% | 1056 12.34% 36.98% | 1053 12.31% 49.28% | 1045 12.21% 61.49% | 1094 12.78% 74.28% | 1078 12.60% 86.88% | 1123 13.12% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Shared_Data::total 8557
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data | 47224 12.53% 12.53% | 47235 12.53% 25.06% | 47180 12.52% 37.57% | 47134 12.50% 50.08% | 47252 12.53% 62.61% | 46968 12.46% 75.07% | 47208 12.52% 87.59% | 46776 12.41% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data::total 376977
|
||||
|
||||
system.ruby.l1_cntrl0.SS.L1_to_L2 | 1116 14.02% 14.02% | 874 10.98% 25.01% | 1194 15.00% 40.01% | 1064 13.37% 53.38% | 767 9.64% 63.02% | 881 11.07% 74.09% | 901 11.32% 85.41% | 1161 14.59% 100.00%
|
||||
system.ruby.l1_cntrl0.SS.L1_to_L2::total 7958
|
||||
|
||||
system.ruby.l1_cntrl0.SS.Ack | 2952 12.15% 12.15% | 3061 12.60% 24.75% | 3007 12.38% 37.13% | 2990 12.31% 49.44% | 3014 12.41% 61.84% | 2995 12.33% 74.17% | 3121 12.85% 87.02% | 3154 12.98% 100.00%
|
||||
system.ruby.l1_cntrl0.SS.Ack::total 24294
|
||||
|
||||
system.ruby.l1_cntrl0.SS.Shared_Ack | 4 11.76% 11.76% | 4 11.76% 23.53% | 4 11.76% 35.29% | 4 11.76% 47.06% | 3 8.82% 55.88% | 6 17.65% 73.53% | 5 14.71% 88.24% | 4 11.76% 100.00%
|
||||
system.ruby.l1_cntrl0.SS.Shared_Ack::total 34
|
||||
|
||||
system.ruby.l1_cntrl0.SS.All_acks | 1114 12.42% 12.42% | 1096 12.21% 24.63% | 1109 12.36% 36.99% | 1107 12.34% 49.33% | 1091 12.16% 61.48% | 1156 12.88% 74.37% | 1120 12.48% 86.85% | 1180 13.15% 100.00%
|
||||
system.ruby.l1_cntrl0.SS.All_acks::total 8973
|
||||
|
||||
system.ruby.l1_cntrl0.SS.All_acks_no_sharers | 1834 12.26% 12.26% | 1892 12.65% 24.91% | 1866 12.47% 37.38% | 1872 12.52% 49.90% | 1847 12.35% 62.25% | 1846 12.34% 74.59% | 1890 12.64% 87.22% | 1911 12.78% 100.00%
|
||||
system.ruby.l1_cntrl0.SS.All_acks_no_sharers::total 14958
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Load | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Load::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Other_GETX::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Other_GETS | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Other_GETS::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Merged_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Merged_GETS::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.OI.Writeback_Ack | 1085 12.95% 12.95% | 1073 12.81% 25.75% | 1027 12.26% 38.01% | 1041 12.42% 50.44% | 1020 12.17% 62.61% | 1047 12.50% 75.10% | 1077 12.85% 87.96% | 1009 12.04% 100.00%
|
||||
system.ruby.l1_cntrl0.OI.Writeback_Ack::total 8379
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Load | 10 11.63% 11.63% | 11 12.79% 24.42% | 14 16.28% 40.70% | 12 13.95% 54.65% | 12 13.95% 68.60% | 8 9.30% 77.91% | 7 8.14% 86.05% | 12 13.95% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Load::total 86
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Store | 7 12.07% 12.07% | 4 6.90% 18.97% | 4 6.90% 25.86% | 12 20.69% 46.55% | 9 15.52% 62.07% | 7 12.07% 74.14% | 8 13.79% 87.93% | 7 12.07% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Store::total 58
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Other_GETX | 25 11.47% 11.47% | 32 14.68% 26.15% | 30 13.76% 39.91% | 25 11.47% 51.38% | 31 14.22% 65.60% | 29 13.30% 78.90% | 29 13.30% 92.20% | 17 7.80% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Other_GETX::total 218
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Other_GETS | 47 13.31% 13.31% | 39 11.05% 24.36% | 39 11.05% 35.41% | 42 11.90% 47.31% | 48 13.60% 60.91% | 46 13.03% 73.94% | 63 17.85% 91.78% | 29 8.22% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Other_GETS::total 353
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Merged_GETS | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Merged_GETS::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack | 71509 12.46% 12.46% | 71917 12.54% 25.00% | 71762 12.51% 37.51% | 71899 12.53% 50.04% | 71741 12.51% 62.55% | 71488 12.46% 75.01% | 72063 12.56% 87.57% | 71314 12.43% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack::total 573693
|
||||
|
||||
system.ruby.l1_cntrl0.II.Writeback_Ack | 25 11.36% 11.36% | 32 14.55% 25.91% | 32 14.55% 40.45% | 25 11.36% 51.82% | 31 14.09% 65.91% | 29 13.18% 79.09% | 29 13.18% 92.27% | 17 7.73% 100.00%
|
||||
system.ruby.l1_cntrl0.II.Writeback_Ack::total 220
|
||||
|
||||
system.ruby.l1_cntrl0.IT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00%
|
||||
system.ruby.l1_cntrl0.IT.Load::total 3
|
||||
|
||||
system.ruby.l1_cntrl0.IT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IT.Store::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.IT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 4.17% 4.17% | 0 0.00% 4.17% | 11 45.83% 50.00% | 9 37.50% 87.50% | 3 12.50% 100.00%
|
||||
system.ruby.l1_cntrl0.IT.L1_to_L2::total 24
|
||||
|
||||
system.ruby.l1_cntrl0.IT.Complete_L2_to_L1 | 3 20.00% 20.00% | 0 0.00% 20.00% | 1 6.67% 26.67% | 2 13.33% 40.00% | 0 0.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00%
|
||||
system.ruby.l1_cntrl0.IT.Complete_L2_to_L1::total 15
|
||||
|
||||
system.ruby.l1_cntrl0.ST.Load | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00%
|
||||
system.ruby.l1_cntrl0.ST.Load::total 5
|
||||
|
||||
system.ruby.l1_cntrl0.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.l1_cntrl0.ST.Store::total 1
|
||||
|
||||
system.ruby.l1_cntrl0.ST.L1_to_L2 | 10 12.99% 12.99% | 21 27.27% 40.26% | 7 9.09% 49.35% | 9 11.69% 61.04% | 0 0.00% 61.04% | 0 0.00% 61.04% | 5 6.49% 67.53% | 25 32.47% 100.00%
|
||||
system.ruby.l1_cntrl0.ST.L1_to_L2::total 77
|
||||
|
||||
system.ruby.l1_cntrl0.ST.Complete_L2_to_L1 | 2 8.70% 8.70% | 5 21.74% 30.43% | 4 17.39% 47.83% | 1 4.35% 52.17% | 0 0.00% 52.17% | 2 8.70% 60.87% | 3 13.04% 73.91% | 6 26.09% 100.00%
|
||||
system.ruby.l1_cntrl0.ST.Complete_L2_to_L1::total 23
|
||||
|
||||
system.ruby.l1_cntrl0.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OT.Load::total 2
|
||||
|
||||
system.ruby.l1_cntrl0.OT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.l1_cntrl0.OT.L1_to_L2::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.OT.Complete_L2_to_L1 | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00%
|
||||
system.ruby.l1_cntrl0.OT.Complete_L2_to_L1::total 6
|
||||
|
||||
system.ruby.l1_cntrl0.MT.Load | 13 13.68% 13.68% | 7 7.37% 21.05% | 10 10.53% 31.58% | 13 13.68% 45.26% | 10 10.53% 55.79% | 14 14.74% 70.53% | 13 13.68% 84.21% | 15 15.79% 100.00%
|
||||
system.ruby.l1_cntrl0.MT.Load::total 95
|
||||
|
||||
system.ruby.l1_cntrl0.MT.Store | 6 10.71% 10.71% | 9 16.07% 26.79% | 9 16.07% 42.86% | 9 16.07% 58.93% | 9 16.07% 75.00% | 7 12.50% 87.50% | 5 8.93% 96.43% | 2 3.57% 100.00%
|
||||
system.ruby.l1_cntrl0.MT.Store::total 56
|
||||
|
||||
system.ruby.l1_cntrl0.MT.L1_to_L2 | 179 15.61% 15.61% | 117 10.20% 25.81% | 164 14.30% 40.10% | 171 14.91% 55.01% | 115 10.03% 65.04% | 155 13.51% 78.55% | 80 6.97% 85.53% | 166 14.47% 100.00%
|
||||
system.ruby.l1_cntrl0.MT.L1_to_L2::total 1147
|
||||
|
||||
system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 | 49 13.14% 13.14% | 40 10.72% 23.86% | 60 16.09% 39.95% | 51 13.67% 53.62% | 41 10.99% 64.61% | 55 14.75% 79.36% | 37 9.92% 89.28% | 40 10.72% 100.00%
|
||||
system.ruby.l1_cntrl0.MT.Complete_L2_to_L1::total 373
|
||||
|
||||
system.ruby.l1_cntrl0.MMT.Load | 8 13.79% 13.79% | 11 18.97% 32.76% | 7 12.07% 44.83% | 8 13.79% 58.62% | 6 10.34% 68.97% | 4 6.90% 75.86% | 9 15.52% 91.38% | 5 8.62% 100.00%
|
||||
system.ruby.l1_cntrl0.MMT.Load::total 58
|
||||
|
||||
system.ruby.l1_cntrl0.MMT.Store | 4 14.29% 14.29% | 3 10.71% 25.00% | 4 14.29% 39.29% | 2 7.14% 46.43% | 5 17.86% 64.29% | 3 10.71% 75.00% | 5 17.86% 92.86% | 2 7.14% 100.00%
|
||||
system.ruby.l1_cntrl0.MMT.Store::total 28
|
||||
|
||||
system.ruby.l1_cntrl0.MMT.L1_to_L2 | 86 11.35% 11.35% | 139 18.34% 29.68% | 85 11.21% 40.90% | 97 12.80% 53.69% | 90 11.87% 65.57% | 91 12.01% 77.57% | 78 10.29% 87.86% | 92 12.14% 100.00%
|
||||
system.ruby.l1_cntrl0.MMT.L1_to_L2::total 758
|
||||
|
||||
system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 | 21 10.29% 10.29% | 25 12.25% 22.55% | 34 16.67% 39.22% | 24 11.76% 50.98% | 25 12.25% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00%
|
||||
system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1::total 204
|
||||
|
||||
system.ruby.dir_cntrl0.GETX 220023 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 406995 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUT 585083 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Unblock 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.UnblockS 23931 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.UnblockM 593445 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Clean 8030 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Dirty 349 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 360015 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 213674 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 597503 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 214013 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.All_Unblocks 439 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NX.GETX 61 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NX.GETS 97 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NX.PUT 8595 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETX 6880 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETS 12400 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.PUT 573697 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETX 8316 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETS 15375 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETX 201220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETS 372612 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.GETX 205 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.GETS 439 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.PUT 2778 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.UnblockS 8092 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.UnblockM 592827 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_X.UnblockS 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_X.UnblockM 201 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S.PUT 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S.UnblockS 22 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S.UnblockM 417 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S_W.GETX 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S_W.GETS 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S_W.PUT 7 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S_W.UnblockS 439 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_S_W.All_Unblocks 439 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_B.GETX 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_B.GETS 6 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_B.UnblockS 15374 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_W.GETX 1957 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_W.GETS 3492 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_W.Memory_Data 582129 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_B_W.GETX 38 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_B_W.GETS 103 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_B_W.Memory_Data 15374 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETX 295 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETS 514 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.PUT 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Unblock 220 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Clean 8030 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Dirty 349 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 360015 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 213674 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_O_W.GETS 3 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_O_W.Memory_Ack 348 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.GETX 1041 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.GETS 1953 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 213665 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,24 @@
|
|||
Real time: Apr/09/2013 01:55:51
|
||||
Real time: Jun/08/2013 13:42:59
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 52
|
||||
Elapsed_time_in_minutes: 0.866667
|
||||
Elapsed_time_in_hours: 0.0144444
|
||||
Elapsed_time_in_days: 0.000601852
|
||||
Elapsed_time_in_seconds: 38
|
||||
Elapsed_time_in_minutes: 0.633333
|
||||
Elapsed_time_in_hours: 0.0105556
|
||||
Elapsed_time_in_days: 0.000439815
|
||||
|
||||
Virtual_time_in_seconds: 52.85
|
||||
Virtual_time_in_minutes: 0.880833
|
||||
Virtual_time_in_hours: 0.0146806
|
||||
Virtual_time_in_days: 0.00061169
|
||||
Virtual_time_in_seconds: 38.03
|
||||
Virtual_time_in_minutes: 0.633833
|
||||
Virtual_time_in_hours: 0.0105639
|
||||
Virtual_time_in_days: 0.000440162
|
||||
|
||||
Ruby_current_time: 8664886
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 8664886
|
||||
|
||||
mbytes_resident: 64.3945
|
||||
mbytes_total: 243.918
|
||||
resident_ratio: 0.264001
|
||||
|
||||
ruby_cycles_executed: [ 8664887 8664887 8664887 8664887 8664887 8664887 8664887 8664887 ]
|
||||
mbytes_resident: 69.8516
|
||||
mbytes_total: 283.504
|
||||
resident_ratio: 0.246414
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -62,7 +60,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -81,12 +78,12 @@ Total_delay_cycles: [binsize: 1 max: 22 count: 1237687 average: 0.00723931 | sta
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 52
|
||||
user_time: 37
|
||||
system_time: 0
|
||||
page_reclaims: 17037
|
||||
page_reclaims: 10989
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 24
|
||||
block_inputs: 264
|
||||
block_outputs: 200
|
||||
|
||||
Network Stats
|
||||
|
|
@ -237,129 +234,3 @@ links_utilized_percent_switch_9: 7.88828
|
|||
outgoing_messages_switch_9_link_8_Control: 617562 4940496 [ 0 0 617562 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 611948 44060256 [ 0 0 611948 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50370 50258 50037 49672 50004 50305 50279 50578 ] 401503
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [27007 26935 26787 27153 27327 27084 27075 26703 ] 216071
|
||||
Data [77375 77192 76821 76821 77329 77385 77352 77277 ] 617552
|
||||
Fwd_GETX [1048 1042 1040 1065 995 1001 998 1019 ] 8208
|
||||
Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
Replacement [77373 77189 76820 76821 77327 77385 77350 77277 ] 617542
|
||||
Writeback_Ack [76323 76144 75775 75751 76330 76378 76350 76253 ] 609304
|
||||
Writeback_Nack [342 322 324 341 327 344 310 313 ] 2623
|
||||
|
||||
- Transitions -
|
||||
I Load [50370 50258 50037 49672 50004 50305 50279 50578 ] 401503
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [27007 26935 26787 27153 27327 27084 27075 26703 ] 216071
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I Replacement [706 720 716 724 668 657 688 706 ] 5585
|
||||
|
||||
II Writeback_Nack [342 322 324 341 327 344 310 313 ] 2623
|
||||
|
||||
M Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M Fwd_GETX [706 720 716 724 668 657 688 706 ] 5585
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M Replacement [76667 76469 76104 76097 76659 76728 76662 76571 ] 611957
|
||||
|
||||
MI Fwd_GETX [342 322 324 341 327 344 310 313 ] 2623
|
||||
MI Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [76323 76144 75775 75751 76330 76378 76350 76253 ] 609304
|
||||
MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Data [50370 50258 50035 49669 50002 50301 50278 50576 ] 401489
|
||||
|
||||
IM Data [27005 26934 26786 27152 27327 27084 27074 26701 ] 216063
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1218678
|
||||
memory_reads: 609346
|
||||
memory_writes: 609308
|
||||
memory_refreshes: 60173
|
||||
memory_total_request_delays: 87480258
|
||||
memory_delays_per_request: 71.7829
|
||||
memory_delays_in_input_queue: 1522193
|
||||
memory_delays_behind_head_of_bank_queue: 40100008
|
||||
memory_delays_stalled_at_head_of_bank_queue: 45858057
|
||||
memory_stalls_for_bank_busy: 7076344
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 11282671
|
||||
memory_stalls_for_arbitration: 9195209
|
||||
memory_stalls_for_bus: 12585722
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4642017
|
||||
memory_stalls_for_read_read_turnaround: 1076094
|
||||
accesses_per_bank: 38404 37646 38381 38273 38109 38021 38580 38357 38057 38004 38123 37658 37751 38546 37560 38514 38232 38045 38749 38589 38066 37687 38032 38060 37804 38206 37726 38148 37682 38049 37701 37918
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [791175 ] 791175
|
||||
GETS [0 ] 0
|
||||
PUTX [609324 ] 609324
|
||||
PUTX_NotOwner [2623 ] 2623
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [609345 ] 609345
|
||||
Memory_Ack [609304 ] 609304
|
||||
|
||||
- Transitions -
|
||||
I GETX [609354 ] 609354
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [8208 ] 8208
|
||||
M PUTX [609324 ] 609324
|
||||
M PUTX_NotOwner [2623 ] 2623
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [65257 ] 65257
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [609345 ] 609345
|
||||
|
||||
MI GETX [108356 ] 108356
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [609304 ] 609304
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.008665 # Nu
|
|||
sim_ticks 8664886 # Number of ticks simulated
|
||||
final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 321644 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252216 # Number of bytes of host memory used
|
||||
host_seconds 26.94 # Real time elapsed on the host
|
||||
host_tick_rate 229644 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290312 # Number of bytes of host memory used
|
||||
host_seconds 37.73 # Real time elapsed on the host
|
||||
system.funcbus.throughput 0 # Throughput (bytes/s)
|
||||
system.funcbus.data_through_bus 0 # Total data (bytes)
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
|
|
@ -33,6 +33,24 @@ system.ruby.l1_cntrl2.cacheMemory.demand_accesses 76824
|
|||
system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_misses 76825 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_accesses 76825 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1218678 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 609346 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 609308 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 60173 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 45858057 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 1522193 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 40100008 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 87480258 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 71.782914 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 7076344 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 12585722 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4642017 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1076094 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 9195209 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 11282671 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 38404 3.15% 3.15% | 37646 3.09% 6.24% | 38381 3.15% 9.39% | 38273 3.14% 12.53% | 38109 3.13% 15.66% | 38021 3.12% 18.78% | 38580 3.17% 21.94% | 38357 3.15% 25.09% | 38057 3.12% 28.21% | 38004 3.12% 31.33% | 38123 3.13% 34.46% | 37658 3.09% 37.55% | 37751 3.10% 40.65% | 38546 3.16% 43.81% | 37560 3.08% 46.89% | 38514 3.16% 50.05% | 38232 3.14% 53.19% | 38045 3.12% 56.31% | 38749 3.18% 59.49% | 38589 3.17% 62.66% | 38066 3.12% 65.78% | 37687 3.09% 68.87% | 38032 3.12% 71.99% | 38060 3.12% 75.12% | 37804 3.10% 78.22% | 38206 3.14% 81.35% | 37726 3.10% 84.45% | 38148 3.13% 87.58% | 37682 3.09% 90.67% | 38049 3.12% 93.79% | 37701 3.09% 96.89% | 37918 3.11% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1218678 # Number of accesses per bank
|
||||
|
||||
system.cpu0.num_reads 99885 # number of read accesses completed
|
||||
system.cpu0.num_writes 54375 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
|
|
@ -57,5 +75,69 @@ system.cpu6.num_copies 0 # nu
|
|||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53796 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.ruby.l1_cntrl0.Load | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50037 12.46% 37.53% | 49672 12.37% 49.90% | 50004 12.45% 62.35% | 50305 12.53% 74.88% | 50279 12.52% 87.40% | 50578 12.60% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 401503
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 27007 12.50% 12.50% | 26935 12.47% 24.96% | 26787 12.40% 37.36% | 27153 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.53% 75.11% | 27075 12.53% 87.64% | 26703 12.36% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 216071
|
||||
|
||||
system.ruby.l1_cntrl0.Data | 77375 12.53% 12.53% | 77192 12.50% 25.03% | 76821 12.44% 37.47% | 76821 12.44% 49.91% | 77329 12.52% 62.43% | 77385 12.53% 74.96% | 77352 12.53% 87.49% | 77277 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Data::total 617552
|
||||
|
||||
system.ruby.l1_cntrl0.Fwd_GETX | 1048 12.77% 12.77% | 1042 12.69% 25.46% | 1040 12.67% 38.13% | 1065 12.98% 51.11% | 995 12.12% 63.23% | 1001 12.20% 75.43% | 998 12.16% 87.59% | 1019 12.41% 100.00%
|
||||
system.ruby.l1_cntrl0.Fwd_GETX::total 8208
|
||||
|
||||
system.ruby.l1_cntrl0.Replacement | 77373 12.53% 12.53% | 77189 12.50% 25.03% | 76820 12.44% 37.47% | 76821 12.44% 49.91% | 77327 12.52% 62.43% | 77385 12.53% 74.96% | 77350 12.53% 87.49% | 77277 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Replacement::total 617542
|
||||
|
||||
system.ruby.l1_cntrl0.Writeback_Ack | 76323 12.53% 12.53% | 76144 12.50% 25.02% | 75775 12.44% 37.46% | 75751 12.43% 49.89% | 76330 12.53% 62.42% | 76378 12.54% 74.95% | 76350 12.53% 87.49% | 76253 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack::total 609304
|
||||
|
||||
system.ruby.l1_cntrl0.Writeback_Nack | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Nack::total 2623
|
||||
|
||||
system.ruby.l1_cntrl0.I.Load | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50037 12.46% 37.53% | 49672 12.37% 49.90% | 50004 12.45% 62.35% | 50305 12.53% 74.88% | 50279 12.52% 87.40% | 50578 12.60% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Load::total 401503
|
||||
|
||||
system.ruby.l1_cntrl0.I.Store | 27007 12.50% 12.50% | 26935 12.47% 24.96% | 26787 12.40% 37.36% | 27153 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.53% 75.11% | 27075 12.53% 87.64% | 26703 12.36% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Store::total 216071
|
||||
|
||||
system.ruby.l1_cntrl0.I.Replacement | 706 12.64% 12.64% | 720 12.89% 25.53% | 716 12.82% 38.35% | 724 12.96% 51.32% | 668 11.96% 63.28% | 657 11.76% 75.04% | 688 12.32% 87.36% | 706 12.64% 100.00%
|
||||
system.ruby.l1_cntrl0.I.Replacement::total 5585
|
||||
|
||||
system.ruby.l1_cntrl0.II.Writeback_Nack | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00%
|
||||
system.ruby.l1_cntrl0.II.Writeback_Nack::total 2623
|
||||
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX | 706 12.64% 12.64% | 720 12.89% 25.53% | 716 12.82% 38.35% | 724 12.96% 51.32% | 668 11.96% 63.28% | 657 11.76% 75.04% | 688 12.32% 87.36% | 706 12.64% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Fwd_GETX::total 5585
|
||||
|
||||
system.ruby.l1_cntrl0.M.Replacement | 76667 12.53% 12.53% | 76469 12.50% 25.02% | 76104 12.44% 37.46% | 76097 12.44% 49.90% | 76659 12.53% 62.42% | 76728 12.54% 74.96% | 76662 12.53% 87.49% | 76571 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement::total 611957
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Fwd_GETX | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Fwd_GETX::total 2623
|
||||
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack | 76323 12.53% 12.53% | 76144 12.50% 25.02% | 75775 12.44% 37.46% | 75751 12.43% 49.89% | 76330 12.53% 62.42% | 76378 12.54% 74.95% | 76350 12.53% 87.49% | 76253 12.51% 100.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack::total 609304
|
||||
|
||||
system.ruby.l1_cntrl0.IS.Data | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50035 12.46% 37.53% | 49669 12.37% 49.90% | 50002 12.45% 62.35% | 50301 12.53% 74.88% | 50278 12.52% 87.40% | 50576 12.60% 100.00%
|
||||
system.ruby.l1_cntrl0.IS.Data::total 401489
|
||||
|
||||
system.ruby.l1_cntrl0.IM.Data | 27005 12.50% 12.50% | 26934 12.47% 24.96% | 26786 12.40% 37.36% | 27152 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.54% 75.11% | 27074 12.53% 87.64% | 26701 12.36% 100.00%
|
||||
system.ruby.l1_cntrl0.IM.Data::total 216063
|
||||
|
||||
system.ruby.dir_cntrl0.GETX 791175 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 609324 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX_NotOwner 2623 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 609345 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 609304 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 609354 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.GETX 8208 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 609324 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX_NotOwner 2623 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.GETX 65257 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 609345 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.GETX 108356 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 609304 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Feb/02/2013 08:14:08
|
||||
Real time: Jun/08/2013 14:12:22
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.56
|
||||
Virtual_time_in_minutes: 0.00933333
|
||||
Virtual_time_in_hours: 0.000155556
|
||||
Virtual_time_in_days: 6.48148e-06
|
||||
Virtual_time_in_seconds: 0.55
|
||||
Virtual_time_in_minutes: 0.00916667
|
||||
Virtual_time_in_hours: 0.000152778
|
||||
Virtual_time_in_days: 6.36574e-06
|
||||
|
||||
Ruby_current_time: 318321
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 318321
|
||||
|
||||
mbytes_resident: 49.3398
|
||||
mbytes_total: 265.707
|
||||
resident_ratio: 0.185751
|
||||
|
||||
ruby_cycles_executed: [ 318322 ]
|
||||
mbytes_resident: 51.1211
|
||||
mbytes_total: 139.629
|
||||
resident_ratio: 0.366177
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -61,7 +59,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -82,11 +79,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10276
|
||||
page_faults: 11
|
||||
page_reclaims: 9776
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 16
|
||||
block_outputs: 248
|
||||
block_inputs: 8
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 2.05746
|
|||
outgoing_messages_switch_3_link_2_Response_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [44 ] 44
|
||||
Ifetch [67 ] 67
|
||||
Store [898 ] 898
|
||||
Inv [563 ] 563
|
||||
L1_Replacement [10398 ] 10398
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [41 ] 41
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [874 ] 874
|
||||
Ack [0 ] 0
|
||||
Ack_all [1 ] 1
|
||||
WB_Ack [755 ] 755
|
||||
PF_Load [0 ] 0
|
||||
PF_Ifetch [0 ] 0
|
||||
PF_Store [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [42 ] 42
|
||||
NP Ifetch [56 ] 56
|
||||
NP Store [818 ] 818
|
||||
NP Inv [1 ] 1
|
||||
NP L1_Replacement [0 ] 0
|
||||
NP PF_Load [0 ] 0
|
||||
NP PF_Ifetch [0 ] 0
|
||||
NP PF_Store [0 ] 0
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [145 ] 145
|
||||
I PF_Load [0 ] 0
|
||||
I PF_Ifetch [0 ] 0
|
||||
I PF_Store [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [1 ] 1
|
||||
S Inv [31 ] 31
|
||||
S L1_Replacement [11 ] 11
|
||||
S PF_Load [0 ] 0
|
||||
S PF_Store [0 ] 0
|
||||
|
||||
E Load [0 ] 0
|
||||
E Ifetch [0 ] 0
|
||||
E Store [2 ] 2
|
||||
E Inv [4 ] 4
|
||||
E L1_Replacement [34 ] 34
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
E PF_Load [0 ] 0
|
||||
E PF_Store [0 ] 0
|
||||
|
||||
M Load [2 ] 2
|
||||
M Ifetch [0 ] 0
|
||||
M Store [77 ] 77
|
||||
M Inv [97 ] 97
|
||||
M L1_Replacement [722 ] 722
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
M PF_Load [0 ] 0
|
||||
M PF_Store [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [14 ] 14
|
||||
IS L1_Replacement [374 ] 374
|
||||
IS Data_Exclusive [41 ] 41
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [43 ] 43
|
||||
IS PF_Load [0 ] 0
|
||||
IS PF_Store [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [9112 ] 9112
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [817 ] 817
|
||||
IM Ack [0 ] 0
|
||||
IM PF_Load [0 ] 0
|
||||
IM PF_Store [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [1 ] 1
|
||||
SM PF_Load [0 ] 0
|
||||
SM PF_Store [0 ] 0
|
||||
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
IS_I Store [0 ] 0
|
||||
IS_I Inv [0 ] 0
|
||||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [14 ] 14
|
||||
IS_I PF_Load [0 ] 0
|
||||
IS_I PF_Store [0 ] 0
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [10 ] 10
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [416 ] 416
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [340 ] 340
|
||||
M_I PF_Load [0 ] 0
|
||||
M_I PF_Store [0 ] 0
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [1 ] 1
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [415 ] 415
|
||||
SINK_WB_ACK PF_Load [0 ] 0
|
||||
SINK_WB_ACK PF_Store [0 ] 0
|
||||
|
||||
PF_IS Load [0 ] 0
|
||||
PF_IS Ifetch [0 ] 0
|
||||
PF_IS Store [0 ] 0
|
||||
PF_IS Inv [0 ] 0
|
||||
PF_IS L1_Replacement [0 ] 0
|
||||
PF_IS Data_Exclusive [0 ] 0
|
||||
PF_IS DataS_fromL1 [0 ] 0
|
||||
PF_IS Data_all_Acks [0 ] 0
|
||||
PF_IS PF_Load [0 ] 0
|
||||
PF_IS PF_Store [0 ] 0
|
||||
|
||||
PF_IM Load [0 ] 0
|
||||
PF_IM Ifetch [0 ] 0
|
||||
PF_IM Store [0 ] 0
|
||||
PF_IM Inv [0 ] 0
|
||||
PF_IM L1_Replacement [0 ] 0
|
||||
PF_IM Data [0 ] 0
|
||||
PF_IM Data_all_Acks [0 ] 0
|
||||
PF_IM Ack [0 ] 0
|
||||
PF_IM PF_Load [0 ] 0
|
||||
PF_IM PF_Store [0 ] 0
|
||||
|
||||
PF_SM Load [0 ] 0
|
||||
PF_SM Ifetch [0 ] 0
|
||||
PF_SM Store [0 ] 0
|
||||
PF_SM Inv [0 ] 0
|
||||
PF_SM L1_Replacement [0 ] 0
|
||||
PF_SM Ack [0 ] 0
|
||||
PF_SM Ack_all [0 ] 0
|
||||
|
||||
PF_IS_I Load [0 ] 0
|
||||
PF_IS_I Store [0 ] 0
|
||||
PF_IS_I Inv [0 ] 0
|
||||
PF_IS_I L1_Replacement [0 ] 0
|
||||
PF_IS_I Data_Exclusive [0 ] 0
|
||||
PF_IS_I DataS_fromL1 [0 ] 0
|
||||
PF_IS_I Data_all_Acks [0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [56 ] 56
|
||||
L1_GETS [42 ] 42
|
||||
L1_GETX [818 ] 818
|
||||
L1_UPGRADE [1 ] 1
|
||||
L1_PUTX [345 ] 345
|
||||
L1_PUTX_old [796 ] 796
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [291 ] 291
|
||||
L2_Replacement_clean [1216 ] 1216
|
||||
Mem_Data [873 ] 873
|
||||
Mem_Ack [869 ] 869
|
||||
WB_Data [495 ] 495
|
||||
WB_Data_clean [18 ] 18
|
||||
Ack [0 ] 0
|
||||
Ack_all [50 ] 50
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [858 ] 858
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [46 ] 46
|
||||
NP L1_GETS [41 ] 41
|
||||
NP L1_GETX [787 ] 787
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [302 ] 302
|
||||
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [1 ] 1
|
||||
SS L1_GETX [9 ] 9
|
||||
SS L1_UPGRADE [1 ] 1
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [46 ] 46
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [10 ] 10
|
||||
M L1_GETS [0 ] 0
|
||||
M L1_GETX [22 ] 22
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [291 ] 291
|
||||
M L2_Replacement_clean [16 ] 16
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [340 ] 340
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L2_Replacement_clean [517 ] 517
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [113 ] 113
|
||||
M_I Mem_Ack [869 ] 869
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [0 ] 0
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [0 ] 0
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [210 ] 210
|
||||
MCT_I WB_Data [495 ] 495
|
||||
MCT_I WB_Data_clean [18 ] 18
|
||||
MCT_I Ack_all [4 ] 4
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [46 ] 46
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [11 ] 11
|
||||
ISS Mem_Data [41 ] 41
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [57 ] 57
|
||||
IS Mem_Data [46 ] 46
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [219 ] 219
|
||||
IM Mem_Data [786 ] 786
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [10 ] 10
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [5 ] 5
|
||||
MT_MB L1_PUTX_old [171 ] 171
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [350 ] 350
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [848 ] 848
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [0 ] 0
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [0 ] 0
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [0 ] 0
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1660
|
||||
memory_reads: 874
|
||||
memory_writes: 786
|
||||
memory_refreshes: 2210
|
||||
memory_total_request_delays: 601
|
||||
memory_delays_per_request: 0.362048
|
||||
memory_delays_in_input_queue: 44
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 555
|
||||
memory_stalls_for_bank_busy: 169
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 30
|
||||
memory_stalls_for_bus: 188
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 104
|
||||
memory_stalls_for_read_read_turnaround: 64
|
||||
accesses_per_bank: 42 51 50 73 73 71 65 49 54 41 50 44 58 48 47 63 57 47 58 57 41 49 46 49 57 45 42 49 45 53 48 38
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [874 ] 874
|
||||
Data [786 ] 786
|
||||
Memory_Data [874 ] 874
|
||||
Memory_Ack [786 ] 786
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [84 ] 84
|
||||
|
||||
- Transitions -
|
||||
I Fetch [874 ] 874
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [786 ] 786
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [84 ] 84
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [874 ] 874
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [786 ] 786
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000318 # Nu
|
|||
sim_ticks 318321 # Number of ticks simulated
|
||||
final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 1383719 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 149800 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
host_tick_rate 2084436 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 142984 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses
|
||||
|
|
@ -25,5 +25,115 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1660 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 786 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 2210 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 555 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 44 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 601 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.362048 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 169 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 188 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 104 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 64 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 30 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 42 2.53% 2.53% | 51 3.07% 5.60% | 50 3.01% 8.61% | 73 4.40% 13.01% | 73 4.40% 17.41% | 71 4.28% 21.69% | 65 3.92% 25.60% | 49 2.95% 28.55% | 54 3.25% 31.81% | 41 2.47% 34.28% | 50 3.01% 37.29% | 44 2.65% 39.94% | 58 3.49% 43.43% | 48 2.89% 46.33% | 47 2.83% 49.16% | 63 3.80% 52.95% | 57 3.43% 56.39% | 47 2.83% 59.22% | 58 3.49% 62.71% | 57 3.43% 66.14% | 41 2.47% 68.61% | 49 2.95% 71.57% | 46 2.77% 74.34% | 49 2.95% 77.29% | 57 3.43% 80.72% | 45 2.71% 83.43% | 42 2.53% 85.96% | 49 2.95% 88.92% | 45 2.71% 91.63% | 53 3.19% 94.82% | 48 2.89% 97.71% | 38 2.29% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1660 # Number of accesses per bank
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GET_INSTR 56 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETS 42 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 818 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_UPGRADE 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 345 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX_old 796 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 291 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement_clean 1216 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Data 873 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Mem_Ack 869 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data 495 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.WB_Data_clean 18 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Ack_all 50 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 858 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GET_INSTR 46 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 41 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 787 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_PUTX_old 302 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GETS 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_GETX 9 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L1_UPGRADE 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS.L2_Replacement_clean 46 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GET_INSTR 10 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 22 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 291 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement_clean 16 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L1_PUTX 340 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT.L2_Replacement_clean 517 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.L1_PUTX_old 113 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M_I.Mem_Ack 869 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 210 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data 495 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 18 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MCT_I.Ack_all 4 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_I.Ack_all 46 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ISS.Mem_Data 41 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.L2_Replacement_clean 57 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IS.Mem_Data 46 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.L2_Replacement_clean 219 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IM.Mem_Data 786 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 10 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_PUTX 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 171 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 350 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 848 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 44 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 67 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 898 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Inv 563 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 10398 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Exclusive 41 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_all_Acks 874 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ack_all 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.WB_Ack 755 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Load 42 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch 56 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Store 818 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Inv 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.L1_Replacement 145 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Store 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.Inv 31 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement 11 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Store 2 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.Inv 4 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.E.L1_Replacement 34 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Load 2 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 77 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Inv 97 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 722 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Inv 14 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement 374 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Exclusive 41 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_all_Acks 43 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement 9112 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_all_Acks 817 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.SM.Ack_all 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS_I.Data_all_Acks 14 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_I.Ifetch 10 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_I.Inv 416 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_I.WB_Ack 340 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack 415 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Fetch 874 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data 786 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 874 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 786 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.CleanReplacement 84 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Fetch 874 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.Data 786 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.CleanReplacement 84 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 874 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 786 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000327 # Nu
|
|||
sim_ticks 327361 # Number of ticks simulated
|
||||
final_tick 327361 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 517762 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 149964 # Number of bytes of host memory used
|
||||
host_seconds 0.63 # Real time elapsed on the host
|
||||
host_tick_rate 849675 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 144052 # Number of bytes of host memory used
|
||||
host_seconds 0.39 # Real time elapsed on the host
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 53 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 855 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 908 # Number of cache demand accesses
|
||||
|
|
@ -16,5 +16,104 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 930
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1619 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 854 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 765 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 2273 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 420 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 26 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 446 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.275479 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 163 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 144 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 21 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 32 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 49 3.03% 3.03% | 44 2.72% 5.74% | 48 2.96% 8.71% | 84 5.19% 13.90% | 49 3.03% 16.92% | 52 3.21% 20.14% | 64 3.95% 24.09% | 51 3.15% 27.24% | 40 2.47% 29.71% | 45 2.78% 32.49% | 48 2.96% 35.45% | 41 2.53% 37.99% | 74 4.57% 42.56% | 47 2.90% 45.46% | 51 3.15% 48.61% | 38 2.35% 50.96% | 56 3.46% 54.42% | 62 3.83% 58.25% | 37 2.29% 60.53% | 58 3.58% 64.11% | 46 2.84% 66.95% | 50 3.09% 70.04% | 55 3.40% 73.44% | 36 2.22% 75.66% | 49 3.03% 78.69% | 71 4.39% 83.08% | 52 3.21% 86.29% | 40 2.47% 88.76% | 42 2.59% 91.35% | 33 2.04% 93.39% | 48 2.96% 96.36% | 59 3.64% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1619 # Number of accesses per bank
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GETS 127 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 895 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_PUTX 2308 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.All_Acks 766 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data 766 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Data_Exclusive 88 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBCLEANDATA 86 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_WBDIRTYDATA 817 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Ack 845 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Exclusive_Unblock 906 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 847 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 88 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 767 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILX.L1_PUTX 903 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 47 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 847 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_GETS 33 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 86 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 817 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.L1_PUTX 65 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Data_Exclusive 88 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 87 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGM.Data 766 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.L1_PUTX 1324 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.All_Acks 766 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 766 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.L1_PUTX 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MM.Exclusive_Unblock 47 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.L1_PUTX 11 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.OO.Exclusive_Unblock 6 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.L1_GETX 81 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MI.Writeback_Ack 845 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 44 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 192 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 1001 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 465203 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data 907 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack_Data 903 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.All_acks 813 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Use_Timeout 905 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 38 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 56 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 814 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 92 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement 1319 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_Timeout 93 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 66 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement 811 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement 29843 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_Timeout 812 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement 399867 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data 813 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.L1_Replacement 17168 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.All_acks 813 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement 16103 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data 94 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Ifetch 136 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Store 115 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 903 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 837 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 88 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 845 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Exclusive_Unblock 852 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Clean_Writeback 80 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Dirty_Writeback 765 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 854 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 765 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 766 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETS 88 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.Memory_Ack 760 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 845 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Exclusive_Unblock 87 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Data 88 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IS.Memory_Ack 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Exclusive_Unblock 765 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Memory_Data 766 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MM.Memory_Ack 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.GETX 71 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Clean_Writeback 80 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Dirty_Writeback 765 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Feb/02/2013 08:20:04
|
||||
Real time: Jun/08/2013 14:15:47
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -16,11 +16,9 @@ Ruby_current_time: 225141
|
|||
Ruby_start_time: 0
|
||||
Ruby_cycles: 225141
|
||||
|
||||
mbytes_resident: 49.4062
|
||||
mbytes_total: 265.762
|
||||
resident_ratio: 0.185963
|
||||
|
||||
ruby_cycles_executed: [ 225142 ]
|
||||
mbytes_resident: 51.3164
|
||||
mbytes_total: 139.676
|
||||
resident_ratio: 0.367453
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -68,7 +66,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -89,7 +86,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10328
|
||||
page_reclaims: 10866
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -173,805 +170,3 @@ links_utilized_percent_switch_3: 1.99349
|
|||
outgoing_messages_switch_3_link_2_Writeback_Control: 72 576 [ 0 0 0 0 72 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [53 ] 53
|
||||
Ifetch [47 ] 47
|
||||
Store [893 ] 893
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [19950 ] 19950
|
||||
Data_Shared [3 ] 3
|
||||
Data_Owner [1 ] 1
|
||||
Data_All_Tokens [993 ] 993
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [1 ] 1
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_Local_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
Transient_Local_GETS_Last_Token [0 ] 0
|
||||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [373 ] 373
|
||||
Request_Timeout [509 ] 509
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [906 ] 906
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [48 ] 48
|
||||
NP Ifetch [47 ] 47
|
||||
NP Store [816 ] 816
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [87 ] 87
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Transient_Local_GETS [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [180 ] 180
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Atomic [0 ] 0
|
||||
I L1_Replacement [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_Local_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_Local_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I Transient_Local_GETS_Last_Token [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [3 ] 3
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_Local_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_Local_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S Transient_Local_GETS_Last_Token [0 ] 0
|
||||
S Persistent_GETX [0 ] 0
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O Atomic [0 ] 0
|
||||
O L1_Replacement [0 ] 0
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_Local_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_Local_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O Transient_Local_GETS_Last_Token [0 ] 0
|
||||
O Persistent_GETX [0 ] 0
|
||||
O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
M Store [0 ] 0
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [89 ] 89
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [18 ] 18
|
||||
|
||||
MM Load [5 ] 5
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [66 ] 66
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [814 ] 814
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [15 ] 15
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [468 ] 468
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
M_W Transient_Local_GETS [0 ] 0
|
||||
M_W Persistent_GETX [0 ] 0
|
||||
M_W Persistent_GETS [0 ] 0
|
||||
M_W Own_Lock_or_Unlock [1 ] 1
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [91 ] 91
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [11 ] 11
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [7711 ] 7711
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [25 ] 25
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [815 ] 815
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [10210 ] 10210
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [1 ] 1
|
||||
IM Data_All_Tokens [814 ] 814
|
||||
IM Ack [0 ] 0
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
IM Transient_Local_GETS [0 ] 0
|
||||
IM Transient_GETS_Last_Token [0 ] 0
|
||||
IM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [114 ] 114
|
||||
IM Request_Timeout [443 ] 443
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Atomic [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
SM Transient_GETS [0 ] 0
|
||||
SM Transient_Local_GETS [0 ] 0
|
||||
SM Transient_GETS_Last_Token [0 ] 0
|
||||
SM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
SM Persistent_GETX [0 ] 0
|
||||
SM Persistent_GETS [0 ] 0
|
||||
SM Persistent_GETS_Last_Token [0 ] 0
|
||||
SM Own_Lock_or_Unlock [0 ] 0
|
||||
SM Request_Timeout [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM Atomic [0 ] 0
|
||||
OM L1_Replacement [0 ] 0
|
||||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [1 ] 1
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
OM Transient_Local_GETS [0 ] 0
|
||||
OM Transient_GETS_Last_Token [0 ] 0
|
||||
OM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [1 ] 1
|
||||
OM Request_Timeout [6 ] 6
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [655 ] 655
|
||||
IS Data_Shared [3 ] 3
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [92 ] 92
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
IS Transient_GETS [0 ] 0
|
||||
IS Transient_Local_GETS [0 ] 0
|
||||
IS Transient_GETS_Last_Token [0 ] 0
|
||||
IS Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [19 ] 19
|
||||
IS Request_Timeout [60 ] 60
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
I_L Store [0 ] 0
|
||||
I_L Atomic [0 ] 0
|
||||
I_L L1_Replacement [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_Local_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_Local_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
I_L Persistent_GETX [0 ] 0
|
||||
I_L Persistent_GETS [0 ] 0
|
||||
I_L Persistent_GETS_Last_Token [0 ] 0
|
||||
I_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S_L Load [0 ] 0
|
||||
S_L Ifetch [0 ] 0
|
||||
S_L Store [0 ] 0
|
||||
S_L Atomic [0 ] 0
|
||||
S_L L1_Replacement [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_Local_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_Local_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
IM_L Load [0 ] 0
|
||||
IM_L Ifetch [0 ] 0
|
||||
IM_L Store [0 ] 0
|
||||
IM_L Atomic [0 ] 0
|
||||
IM_L L1_Replacement [0 ] 0
|
||||
IM_L Data_Shared [0 ] 0
|
||||
IM_L Data_Owner [0 ] 0
|
||||
IM_L Data_All_Tokens [0 ] 0
|
||||
IM_L Ack [0 ] 0
|
||||
IM_L Transient_GETX [0 ] 0
|
||||
IM_L Transient_Local_GETX [0 ] 0
|
||||
IM_L Transient_GETS [0 ] 0
|
||||
IM_L Transient_Local_GETS [0 ] 0
|
||||
IM_L Transient_GETS_Last_Token [0 ] 0
|
||||
IM_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM_L Persistent_GETX [0 ] 0
|
||||
IM_L Persistent_GETS [0 ] 0
|
||||
IM_L Own_Lock_or_Unlock [0 ] 0
|
||||
IM_L Request_Timeout [0 ] 0
|
||||
|
||||
SM_L Load [0 ] 0
|
||||
SM_L Ifetch [0 ] 0
|
||||
SM_L Store [0 ] 0
|
||||
SM_L Atomic [0 ] 0
|
||||
SM_L L1_Replacement [0 ] 0
|
||||
SM_L Data_Shared [0 ] 0
|
||||
SM_L Data_Owner [0 ] 0
|
||||
SM_L Data_All_Tokens [0 ] 0
|
||||
SM_L Ack [0 ] 0
|
||||
SM_L Transient_GETX [0 ] 0
|
||||
SM_L Transient_Local_GETX [0 ] 0
|
||||
SM_L Transient_GETS [0 ] 0
|
||||
SM_L Transient_Local_GETS [0 ] 0
|
||||
SM_L Transient_GETS_Last_Token [0 ] 0
|
||||
SM_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
SM_L Persistent_GETX [0 ] 0
|
||||
SM_L Persistent_GETS [0 ] 0
|
||||
SM_L Persistent_GETS_Last_Token [0 ] 0
|
||||
SM_L Own_Lock_or_Unlock [0 ] 0
|
||||
SM_L Request_Timeout [0 ] 0
|
||||
|
||||
IS_L Load [0 ] 0
|
||||
IS_L Ifetch [0 ] 0
|
||||
IS_L Store [0 ] 0
|
||||
IS_L Atomic [0 ] 0
|
||||
IS_L L1_Replacement [0 ] 0
|
||||
IS_L Data_Shared [0 ] 0
|
||||
IS_L Data_Owner [0 ] 0
|
||||
IS_L Data_All_Tokens [0 ] 0
|
||||
IS_L Ack [0 ] 0
|
||||
IS_L Transient_GETX [0 ] 0
|
||||
IS_L Transient_Local_GETX [0 ] 0
|
||||
IS_L Transient_GETS [0 ] 0
|
||||
IS_L Transient_Local_GETS [0 ] 0
|
||||
IS_L Transient_GETS_Last_Token [0 ] 0
|
||||
IS_L Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS_L Persistent_GETX [0 ] 0
|
||||
IS_L Persistent_GETS [0 ] 0
|
||||
IS_L Own_Lock_or_Unlock [0 ] 0
|
||||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [95 ] 95
|
||||
L1_GETS_Last_Token [0 ] 0
|
||||
L1_GETX [816 ] 816
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [817 ] 817
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [1 ] 1
|
||||
Writeback_All_Tokens [905 ] 905
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [163 ] 163
|
||||
Persistent_GETS [24 ] 24
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [186 ] 186
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [91 ] 91
|
||||
NP L1_GETX [779 ] 779
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [0 ] 0
|
||||
NP Writeback_All_Tokens [821 ] 821
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [0 ] 0
|
||||
NP Ack [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [158 ] 158
|
||||
|
||||
I L1_GETS [1 ] 1
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [0 ] 0
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [32 ] 32
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [1 ] 1
|
||||
I Writeback_All_Tokens [31 ] 31
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [0 ] 0
|
||||
S L1_GETX [0 ] 0
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [0 ] 0
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
S Writeback_Owned [0 ] 0
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Persistent_GETX [1 ] 1
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [0 ] 0
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [2 ] 2
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Persistent_GETX [0 ] 0
|
||||
O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [3 ] 3
|
||||
M L1_GETX [36 ] 36
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [784 ] 784
|
||||
M Persistent_GETX [23 ] 23
|
||||
M Persistent_GETS [5 ] 5
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
I_L L1_GETX [0 ] 0
|
||||
I_L L1_INV [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [1 ] 1
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [51 ] 51
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [139 ] 139
|
||||
I_L Persistent_GETS [19 ] 19
|
||||
I_L Own_Lock_or_Unlock [28 ] 28
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
S_L L1_GETX [0 ] 0
|
||||
S_L L1_INV [0 ] 0
|
||||
S_L Transient_GETX [0 ] 0
|
||||
S_L Transient_GETS [0 ] 0
|
||||
S_L Transient_GETS_Last_Token [0 ] 0
|
||||
S_L L2_Replacement [0 ] 0
|
||||
S_L Writeback_Tokens [0 ] 0
|
||||
S_L Writeback_Shared_Data [0 ] 0
|
||||
S_L Writeback_All_Tokens [0 ] 0
|
||||
S_L Writeback_Owned [0 ] 0
|
||||
S_L Data_Shared [0 ] 0
|
||||
S_L Data_Owner [0 ] 0
|
||||
S_L Data_All_Tokens [0 ] 0
|
||||
S_L Ack [0 ] 0
|
||||
S_L Persistent_GETX [0 ] 0
|
||||
S_L Persistent_GETS [0 ] 0
|
||||
S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1655
|
||||
memory_reads: 868
|
||||
memory_writes: 787
|
||||
memory_refreshes: 1564
|
||||
memory_total_request_delays: 503
|
||||
memory_delays_per_request: 0.303927
|
||||
memory_delays_in_input_queue: 34
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 469
|
||||
memory_stalls_for_bank_busy: 134
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 39
|
||||
memory_stalls_for_bus: 192
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 48
|
||||
memory_stalls_for_read_read_turnaround: 56
|
||||
accesses_per_bank: 51 47 34 94 74 59 55 45 53 55 62 49 52 51 44 57 49 51 46 44 46 41 54 56 46 55 50 43 43 47 62 40
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [789 ] 789
|
||||
GETS [94 ] 94
|
||||
Lockdown [187 ] 187
|
||||
Unlockdown [186 ] 186
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [799 ] 799
|
||||
Ack_Owner [0 ] 0
|
||||
Ack_Owner_All_Tokens [72 ] 72
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [868 ] 868
|
||||
Memory_Ack [787 ] 787
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [768 ] 768
|
||||
O GETS [86 ] 86
|
||||
O Lockdown [14 ] 14
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [2 ] 2
|
||||
NO GETS [4 ] 4
|
||||
NO Lockdown [166 ] 166
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [0 ] 0
|
||||
NO Data_All_Tokens [787 ] 787
|
||||
NO Ack_Owner [0 ] 0
|
||||
NO Ack_Owner_All_Tokens [72 ] 72
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [10 ] 10
|
||||
L GETS [2 ] 2
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [185 ] 185
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [12 ] 12
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [0 ] 0
|
||||
L Tokens [0 ] 0
|
||||
L DMA_READ [0 ] 0
|
||||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W Lockdown [0 ] 0
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_W Data_Owner [0 ] 0
|
||||
O_W Data_All_Tokens [0 ] 0
|
||||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [1 ] 1
|
||||
O_W Memory_Ack [787 ] 787
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [9 ] 9
|
||||
L_O_W GETS [2 ] 2
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [1 ] 1
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
L_O_W Data_All_Tokens [0 ] 0
|
||||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [13 ] 13
|
||||
L_O_W Memory_Ack [0 ] 0
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_NO_W GETX [0 ] 0
|
||||
L_NO_W GETS [0 ] 0
|
||||
L_NO_W Lockdown [0 ] 0
|
||||
L_NO_W Unlockdown [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_NO_W Data_Owner [0 ] 0
|
||||
L_NO_W Data_All_Tokens [0 ] 0
|
||||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [7 ] 7
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L_W GETX [0 ] 0
|
||||
DR_L_W GETS [0 ] 0
|
||||
DR_L_W Lockdown [0 ] 0
|
||||
DR_L_W Unlockdown [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L_W Data_Owner [0 ] 0
|
||||
DR_L_W Data_All_Tokens [0 ] 0
|
||||
DR_L_W Ack_Owner [0 ] 0
|
||||
DR_L_W Tokens [0 ] 0
|
||||
DR_L_W Ack_All_Tokens [0 ] 0
|
||||
DR_L_W Request_Timeout [0 ] 0
|
||||
DR_L_W Memory_Data [0 ] 0
|
||||
DR_L_W DMA_READ [0 ] 0
|
||||
DR_L_W DMA_WRITE [0 ] 0
|
||||
DR_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L_W GETX [0 ] 0
|
||||
DW_L_W GETS [0 ] 0
|
||||
DW_L_W Lockdown [0 ] 0
|
||||
DW_L_W Unlockdown [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L_W Data_Owner [0 ] 0
|
||||
DW_L_W Data_All_Tokens [0 ] 0
|
||||
DW_L_W Ack_Owner [0 ] 0
|
||||
DW_L_W Tokens [0 ] 0
|
||||
DW_L_W Ack_All_Tokens [0 ] 0
|
||||
DW_L_W Request_Timeout [0 ] 0
|
||||
DW_L_W Memory_Ack [0 ] 0
|
||||
DW_L_W DMA_READ [0 ] 0
|
||||
DW_L_W DMA_WRITE [0 ] 0
|
||||
DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [7 ] 7
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_W Data_Owner [0 ] 0
|
||||
NO_W Data_All_Tokens [0 ] 0
|
||||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [847 ] 847
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW_W GETX [0 ] 0
|
||||
O_DW_W GETS [0 ] 0
|
||||
O_DW_W Lockdown [0 ] 0
|
||||
O_DW_W Unlockdown [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW_W Data_Owner [0 ] 0
|
||||
O_DW_W Data_All_Tokens [0 ] 0
|
||||
O_DW_W Ack_Owner [0 ] 0
|
||||
O_DW_W Tokens [0 ] 0
|
||||
O_DW_W Ack_All_Tokens [0 ] 0
|
||||
O_DW_W Request_Timeout [0 ] 0
|
||||
O_DW_W Memory_Ack [0 ] 0
|
||||
O_DW_W DMA_READ [0 ] 0
|
||||
O_DW_W DMA_WRITE [0 ] 0
|
||||
O_DW_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DR_W GETX [0 ] 0
|
||||
O_DR_W GETS [0 ] 0
|
||||
O_DR_W Lockdown [0 ] 0
|
||||
O_DR_W Unlockdown [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DR_W Data_Owner [0 ] 0
|
||||
O_DR_W Data_All_Tokens [0 ] 0
|
||||
O_DR_W Ack_Owner [0 ] 0
|
||||
O_DR_W Tokens [0 ] 0
|
||||
O_DR_W Ack_All_Tokens [0 ] 0
|
||||
O_DR_W Request_Timeout [0 ] 0
|
||||
O_DR_W Memory_Data [0 ] 0
|
||||
O_DR_W DMA_READ [0 ] 0
|
||||
O_DR_W DMA_WRITE [0 ] 0
|
||||
O_DR_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_DW GETX [0 ] 0
|
||||
O_DW GETS [0 ] 0
|
||||
O_DW Lockdown [0 ] 0
|
||||
O_DW Unlockdown [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock [0 ] 0
|
||||
O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O_DW Data_Owner [0 ] 0
|
||||
O_DW Data_All_Tokens [0 ] 0
|
||||
O_DW Ack_Owner [0 ] 0
|
||||
O_DW Ack_Owner_All_Tokens [0 ] 0
|
||||
O_DW Tokens [0 ] 0
|
||||
O_DW Ack_All_Tokens [0 ] 0
|
||||
O_DW Request_Timeout [0 ] 0
|
||||
O_DW DMA_READ [0 ] 0
|
||||
O_DW DMA_WRITE [0 ] 0
|
||||
O_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DW GETX [0 ] 0
|
||||
NO_DW GETS [0 ] 0
|
||||
NO_DW Lockdown [0 ] 0
|
||||
NO_DW Unlockdown [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DW Data_Owner [0 ] 0
|
||||
NO_DW Data_All_Tokens [0 ] 0
|
||||
NO_DW Tokens [0 ] 0
|
||||
NO_DW Request_Timeout [0 ] 0
|
||||
NO_DW DMA_READ [0 ] 0
|
||||
NO_DW DMA_WRITE [0 ] 0
|
||||
NO_DW DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_DR GETX [0 ] 0
|
||||
NO_DR GETS [0 ] 0
|
||||
NO_DR Lockdown [0 ] 0
|
||||
NO_DR Unlockdown [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock [0 ] 0
|
||||
NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO_DR Data_Owner [0 ] 0
|
||||
NO_DR Data_All_Tokens [0 ] 0
|
||||
NO_DR Tokens [0 ] 0
|
||||
NO_DR Request_Timeout [0 ] 0
|
||||
NO_DR DMA_READ [0 ] 0
|
||||
NO_DR DMA_WRITE [0 ] 0
|
||||
NO_DR DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DW_L GETX [0 ] 0
|
||||
DW_L GETS [0 ] 0
|
||||
DW_L Lockdown [0 ] 0
|
||||
DW_L Unlockdown [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock [0 ] 0
|
||||
DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DW_L Data_Owner [0 ] 0
|
||||
DW_L Data_All_Tokens [0 ] 0
|
||||
DW_L Ack_Owner [0 ] 0
|
||||
DW_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DW_L Tokens [0 ] 0
|
||||
DW_L Request_Timeout [0 ] 0
|
||||
DW_L DMA_READ [0 ] 0
|
||||
DW_L DMA_WRITE [0 ] 0
|
||||
DW_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
DR_L GETX [0 ] 0
|
||||
DR_L GETS [0 ] 0
|
||||
DR_L Lockdown [0 ] 0
|
||||
DR_L Unlockdown [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock [0 ] 0
|
||||
DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
DR_L Data_Owner [0 ] 0
|
||||
DR_L Data_All_Tokens [0 ] 0
|
||||
DR_L Ack_Owner [0 ] 0
|
||||
DR_L Ack_Owner_All_Tokens [0 ] 0
|
||||
DR_L Tokens [0 ] 0
|
||||
DR_L Request_Timeout [0 ] 0
|
||||
DR_L DMA_READ [0 ] 0
|
||||
DR_L DMA_WRITE [0 ] 0
|
||||
DR_L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000225 # Nu
|
|||
sim_ticks 225141 # Number of ticks simulated
|
||||
final_tick 225141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 1225804 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 149920 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 1771035 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 143032 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 872 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 911 # Number of cache demand accesses
|
||||
|
|
@ -16,5 +16,122 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 946
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 47 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 47 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1655 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 868 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 787 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 1564 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 469 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 34 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 503 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.303927 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 134 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 192 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 48 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 56 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 39 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 51 3.08% 3.08% | 47 2.84% 5.92% | 34 2.05% 7.98% | 94 5.68% 13.66% | 74 4.47% 18.13% | 59 3.56% 21.69% | 55 3.32% 25.02% | 45 2.72% 27.73% | 53 3.20% 30.94% | 55 3.32% 34.26% | 62 3.75% 38.01% | 49 2.96% 40.97% | 52 3.14% 44.11% | 51 3.08% 47.19% | 44 2.66% 49.85% | 57 3.44% 53.29% | 49 2.96% 56.25% | 51 3.08% 59.34% | 46 2.78% 62.11% | 44 2.66% 64.77% | 46 2.78% 67.55% | 41 2.48% 70.03% | 54 3.26% 73.29% | 56 3.38% 76.68% | 46 2.78% 79.46% | 55 3.32% 82.78% | 50 3.02% 85.80% | 43 2.60% 88.40% | 43 2.60% 91.00% | 47 2.84% 93.84% | 62 3.75% 97.58% | 40 2.42% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1655 # Number of accesses per bank
|
||||
|
||||
system.ruby.l2_cntrl0.L1_GETS 95 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L1_GETX 816 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.L2_Replacement 817 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_Shared_Data 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Writeback_All_Tokens 905 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Persistent_GETX 163 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Persistent_GETS 24 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.Own_Lock_or_Unlock 186 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETS 91 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.L1_GETX 779 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 821 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.NP.Own_Lock_or_Unlock 158 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L1_GETS 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.L2_Replacement 32 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_Shared_Data 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I.Writeback_All_Tokens 31 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.S.Persistent_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.O.Writeback_All_Tokens 2 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETS 3 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L1_GETX 36 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.L2_Replacement 784 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.Persistent_GETX 23 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.M.Persistent_GETS 5 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.L2_Replacement 1 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Writeback_All_Tokens 51 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Persistent_GETX 139 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Persistent_GETS 19 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.I_L.Own_Lock_or_Unlock 28 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Load 53 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 47 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 893 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_Replacement 19950 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Shared 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_Owner 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data_All_Tokens 993 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ack_All_Tokens 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Own_Lock_or_Unlock 373 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Request_Timeout 509 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Use_TimeoutNoStarvers 906 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Load 48 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Ifetch 47 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Store 816 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Data_All_Tokens 87 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.NP.Own_Lock_or_Unlock 180 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.S.L1_Replacement 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_Replacement 89 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Own_Lock_or_Unlock 18 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 5 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 66 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_Replacement 814 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Own_Lock_or_Unlock 15 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_Replacement 468 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Own_Lock_or_Unlock 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers 91 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 11 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_Replacement 7711 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Own_Lock_or_Unlock 25 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers 815 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_Replacement 10210 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_Owner 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data_All_Tokens 814 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Own_Lock_or_Unlock 114 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Request_Timeout 443 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.Ack_All_Tokens 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.Own_Lock_or_Unlock 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.OM.Request_Timeout 6 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_Replacement 655 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_Shared 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data_All_Tokens 92 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Own_Lock_or_Unlock 19 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Request_Timeout 60 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 789 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 94 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Lockdown 187 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Unlockdown 186 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data_All_Tokens 799 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 72 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 868 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 787 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETX 768 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.GETS 86 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O.Lockdown 14 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETX 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETS 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Lockdown 166 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Data_All_Tokens 787 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 72 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.GETX 10 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.GETS 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Unlockdown 185 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L.Data_All_Tokens 12 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Memory_Data 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.O_W.Memory_Ack 787 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.GETX 9 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.Unlockdown 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_O_W.Memory_Data 13 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.L_NO_W.Memory_Data 7 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Lockdown 7 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_W.Memory_Data 847 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Feb/02/2013 08:11:05
|
||||
Real time: Jun/08/2013 13:29:50
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.52
|
||||
Virtual_time_in_minutes: 0.00866667
|
||||
Virtual_time_in_hours: 0.000144444
|
||||
Virtual_time_in_days: 6.01852e-06
|
||||
Virtual_time_in_seconds: 0.5
|
||||
Virtual_time_in_minutes: 0.00833333
|
||||
Virtual_time_in_hours: 0.000138889
|
||||
Virtual_time_in_days: 5.78704e-06
|
||||
|
||||
Ruby_current_time: 172201
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 172201
|
||||
|
||||
mbytes_resident: 49.1211
|
||||
mbytes_total: 265.684
|
||||
resident_ratio: 0.18493
|
||||
|
||||
ruby_cycles_executed: [ 172202 ]
|
||||
mbytes_resident: 51.9141
|
||||
mbytes_total: 139.598
|
||||
resident_ratio: 0.371939
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -69,7 +67,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -90,11 +87,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10236
|
||||
page_faults: 0
|
||||
page_reclaims: 13998
|
||||
page_faults: 36
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 96
|
||||
block_inputs: 4432
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -145,749 +142,3 @@ links_utilized_percent_switch_2: 2.61613
|
|||
outgoing_messages_switch_2_link_1_Writeback_Control: 918 7344 [ 0 0 843 0 0 75 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 845 6760 [ 0 0 0 0 0 845 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [52 ] 52
|
||||
Ifetch [53 ] 53
|
||||
Store [888 ] 888
|
||||
L2_Replacement [840 ] 840
|
||||
L1_to_L2 [16587 ] 16587
|
||||
Trigger_L2_to_L1D [41 ] 41
|
||||
Trigger_L2_to_L1I [9 ] 9
|
||||
Complete_L2_to_L1 [50 ] 50
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [850 ] 850
|
||||
Writeback_Ack [843 ] 843
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [850 ] 850
|
||||
Flush_line [5 ] 5
|
||||
Block_Ack [1 ] 1
|
||||
|
||||
- Transitions -
|
||||
I Load [46 ] 46
|
||||
I Ifetch [40 ] 40
|
||||
I Store [762 ] 762
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
I Trigger_L2_to_L1I [0 ] 0
|
||||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [4 ] 4
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S L2_Replacement [0 ] 0
|
||||
S L1_to_L2 [0 ] 0
|
||||
S Trigger_L2_to_L1D [0 ] 0
|
||||
S Trigger_L2_to_L1I [0 ] 0
|
||||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
S Flush_line [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O L2_Replacement [0 ] 0
|
||||
O L1_to_L2 [0 ] 0
|
||||
O Trigger_L2_to_L1D [0 ] 0
|
||||
O Trigger_L2_to_L1I [0 ] 0
|
||||
O Other_GETX [0 ] 0
|
||||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Store [0 ] 0
|
||||
M L2_Replacement [71 ] 71
|
||||
M L1_to_L2 [83 ] 83
|
||||
M Trigger_L2_to_L1D [11 ] 11
|
||||
M Trigger_L2_to_L1I [0 ] 0
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [5 ] 5
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [62 ] 62
|
||||
MM L2_Replacement [769 ] 769
|
||||
MM L1_to_L2 [809 ] 809
|
||||
MM Trigger_L2_to_L1D [30 ] 30
|
||||
MM Trigger_L2_to_L1I [9 ] 9
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
MM Flush_line [0 ] 0
|
||||
|
||||
IR Load [0 ] 0
|
||||
IR Ifetch [0 ] 0
|
||||
IR Store [0 ] 0
|
||||
IR L1_to_L2 [0 ] 0
|
||||
IR Flush_line [0 ] 0
|
||||
|
||||
SR Load [0 ] 0
|
||||
SR Ifetch [0 ] 0
|
||||
SR Store [0 ] 0
|
||||
SR L1_to_L2 [0 ] 0
|
||||
SR Flush_line [0 ] 0
|
||||
|
||||
OR Load [0 ] 0
|
||||
OR Ifetch [0 ] 0
|
||||
OR Store [0 ] 0
|
||||
OR L1_to_L2 [0 ] 0
|
||||
OR Flush_line [0 ] 0
|
||||
|
||||
MR Load [0 ] 0
|
||||
MR Ifetch [0 ] 0
|
||||
MR Store [11 ] 11
|
||||
MR L1_to_L2 [90 ] 90
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [0 ] 0
|
||||
MMR Ifetch [9 ] 9
|
||||
MMR Store [29 ] 29
|
||||
MMR L1_to_L2 [25 ] 25
|
||||
MMR Flush_line [1 ] 1
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [9996 ] 9996
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [761 ] 761
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM L2_Replacement [0 ] 0
|
||||
SM L1_to_L2 [0 ] 0
|
||||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
SM Flush_line [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM L2_Replacement [0 ] 0
|
||||
OM L1_to_L2 [0 ] 0
|
||||
OM Other_GETX [0 ] 0
|
||||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
OM All_acks_no_sharers [0 ] 0
|
||||
OM Flush_line [0 ] 0
|
||||
|
||||
ISM Load [0 ] 0
|
||||
ISM Ifetch [0 ] 0
|
||||
ISM Store [0 ] 0
|
||||
ISM L2_Replacement [0 ] 0
|
||||
ISM L1_to_L2 [0 ] 0
|
||||
ISM Ack [0 ] 0
|
||||
ISM All_acks_no_sharers [0 ] 0
|
||||
ISM Flush_line [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [306 ] 306
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [85 ] 85
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [3 ] 3
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [4592 ] 4592
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [761 ] 761
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [529 ] 529
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [85 ] 85
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
SS Store [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L1_to_L2 [0 ] 0
|
||||
SS Ack [0 ] 0
|
||||
SS Shared_Ack [0 ] 0
|
||||
SS All_acks [0 ] 0
|
||||
SS All_acks_no_sharers [0 ] 0
|
||||
SS Flush_line [0 ] 0
|
||||
|
||||
OI Load [0 ] 0
|
||||
OI Ifetch [0 ] 0
|
||||
OI Store [0 ] 0
|
||||
OI L2_Replacement [0 ] 0
|
||||
OI L1_to_L2 [0 ] 0
|
||||
OI Other_GETX [0 ] 0
|
||||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [1 ] 1
|
||||
MI Ifetch [3 ] 3
|
||||
MI Store [1 ] 1
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [838 ] 838
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
II Store [0 ] 0
|
||||
II L2_Replacement [0 ] 0
|
||||
II L1_to_L2 [0 ] 0
|
||||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
II Flush_line [0 ] 0
|
||||
|
||||
IT Load [0 ] 0
|
||||
IT Ifetch [0 ] 0
|
||||
IT Store [0 ] 0
|
||||
IT L2_Replacement [0 ] 0
|
||||
IT L1_to_L2 [0 ] 0
|
||||
IT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
ST Ifetch [0 ] 0
|
||||
ST Store [0 ] 0
|
||||
ST L2_Replacement [0 ] 0
|
||||
ST L1_to_L2 [0 ] 0
|
||||
ST Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
OT Ifetch [0 ] 0
|
||||
OT Store [0 ] 0
|
||||
OT L2_Replacement [0 ] 0
|
||||
OT L1_to_L2 [0 ] 0
|
||||
OT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [2 ] 2
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [54 ] 54
|
||||
MT Complete_L2_to_L1 [11 ] 11
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [18 ] 18
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [103 ] 103
|
||||
MMT Complete_L2_to_L1 [39 ] 39
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [5 ] 5
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
MM_F Ifetch [0 ] 0
|
||||
MM_F Store [0 ] 0
|
||||
MM_F L1_to_L2 [0 ] 0
|
||||
MM_F Other_GETX [0 ] 0
|
||||
MM_F Other_GETS [0 ] 0
|
||||
MM_F Merged_GETS [0 ] 0
|
||||
MM_F Other_GETS_No_Mig [0 ] 0
|
||||
MM_F NC_DMA_GETS [0 ] 0
|
||||
MM_F Invalidate [0 ] 0
|
||||
MM_F Ack [0 ] 0
|
||||
MM_F All_acks [0 ] 0
|
||||
MM_F All_acks_no_sharers [0 ] 0
|
||||
MM_F Flush_line [0 ] 0
|
||||
MM_F Block_Ack [1 ] 1
|
||||
|
||||
IM_F Load [0 ] 0
|
||||
IM_F Ifetch [0 ] 0
|
||||
IM_F Store [0 ] 0
|
||||
IM_F L2_Replacement [0 ] 0
|
||||
IM_F L1_to_L2 [0 ] 0
|
||||
IM_F Other_GETX [0 ] 0
|
||||
IM_F Other_GETS [0 ] 0
|
||||
IM_F Other_GETS_No_Mig [0 ] 0
|
||||
IM_F NC_DMA_GETS [0 ] 0
|
||||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [4 ] 4
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
ISM_F Ifetch [0 ] 0
|
||||
ISM_F Store [0 ] 0
|
||||
ISM_F L2_Replacement [0 ] 0
|
||||
ISM_F L1_to_L2 [0 ] 0
|
||||
ISM_F Ack [0 ] 0
|
||||
ISM_F All_acks_no_sharers [0 ] 0
|
||||
ISM_F Flush_line [0 ] 0
|
||||
|
||||
SM_F Load [0 ] 0
|
||||
SM_F Ifetch [0 ] 0
|
||||
SM_F Store [0 ] 0
|
||||
SM_F L2_Replacement [0 ] 0
|
||||
SM_F L1_to_L2 [0 ] 0
|
||||
SM_F Other_GETX [0 ] 0
|
||||
SM_F Other_GETS [0 ] 0
|
||||
SM_F Other_GETS_No_Mig [0 ] 0
|
||||
SM_F NC_DMA_GETS [0 ] 0
|
||||
SM_F Invalidate [0 ] 0
|
||||
SM_F Ack [0 ] 0
|
||||
SM_F Data [0 ] 0
|
||||
SM_F Exclusive_Data [0 ] 0
|
||||
SM_F Flush_line [0 ] 0
|
||||
|
||||
OM_F Load [0 ] 0
|
||||
OM_F Ifetch [0 ] 0
|
||||
OM_F Store [0 ] 0
|
||||
OM_F L2_Replacement [0 ] 0
|
||||
OM_F L1_to_L2 [0 ] 0
|
||||
OM_F Other_GETX [0 ] 0
|
||||
OM_F Other_GETS [0 ] 0
|
||||
OM_F Merged_GETS [0 ] 0
|
||||
OM_F Other_GETS_No_Mig [0 ] 0
|
||||
OM_F NC_DMA_GETS [0 ] 0
|
||||
OM_F Invalidate [0 ] 0
|
||||
OM_F Ack [0 ] 0
|
||||
OM_F All_acks [0 ] 0
|
||||
OM_F All_acks_no_sharers [0 ] 0
|
||||
OM_F Flush_line [0 ] 0
|
||||
|
||||
MM_WF Load [0 ] 0
|
||||
MM_WF Ifetch [0 ] 0
|
||||
MM_WF Store [0 ] 0
|
||||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [4 ] 4
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1617
|
||||
memory_reads: 850
|
||||
memory_writes: 767
|
||||
memory_refreshes: 1196
|
||||
memory_total_request_delays: 599
|
||||
memory_delays_per_request: 0.370439
|
||||
memory_delays_in_input_queue: 48
|
||||
memory_delays_behind_head_of_bank_queue: 1
|
||||
memory_delays_stalled_at_head_of_bank_queue: 550
|
||||
memory_stalls_for_bank_busy: 172
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 40
|
||||
memory_stalls_for_bus: 204
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 52
|
||||
memory_stalls_for_read_read_turnaround: 82
|
||||
accesses_per_bank: 60 50 58 80 69 77 71 48 48 38 42 44 39 57 47 44 42 45 53 54 55 41 48 56 29 45 43 51 47 51 42 43
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [761 ] 761
|
||||
GETS [87 ] 87
|
||||
PUT [913 ] 913
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [845 ] 845
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [75 ] 75
|
||||
Writeback_Exclusive_Dirty [767 ] 767
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [850 ] 850
|
||||
Memory_Ack [767 ] 767
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [0 ] 0
|
||||
All_acks_and_shared_data [0 ] 0
|
||||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [5 ] 5
|
||||
PUTF [5 ] 5
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
NX GETS [0 ] 0
|
||||
NX PUT [0 ] 0
|
||||
NX Pf_Replacement [0 ] 0
|
||||
NX DMA_READ [0 ] 0
|
||||
NX DMA_WRITE [0 ] 0
|
||||
NX GETF [0 ] 0
|
||||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [838 ] 838
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [1 ] 1
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
S PUT [0 ] 0
|
||||
S Pf_Replacement [0 ] 0
|
||||
S DMA_READ [0 ] 0
|
||||
S DMA_WRITE [0 ] 0
|
||||
S GETF [0 ] 0
|
||||
|
||||
O GETX [0 ] 0
|
||||
O GETS [0 ] 0
|
||||
O PUT [0 ] 0
|
||||
O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [761 ] 761
|
||||
E GETS [85 ] 85
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [4 ] 4
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
O_R PUT [0 ] 0
|
||||
O_R Pf_Replacement [0 ] 0
|
||||
O_R DMA_READ [0 ] 0
|
||||
O_R DMA_WRITE [0 ] 0
|
||||
O_R Ack [0 ] 0
|
||||
O_R All_acks_and_data_no_sharers [0 ] 0
|
||||
O_R GETF [0 ] 0
|
||||
|
||||
S_R GETX [0 ] 0
|
||||
S_R GETS [0 ] 0
|
||||
S_R PUT [0 ] 0
|
||||
S_R Pf_Replacement [0 ] 0
|
||||
S_R DMA_READ [0 ] 0
|
||||
S_R DMA_WRITE [0 ] 0
|
||||
S_R Ack [0 ] 0
|
||||
S_R Data [0 ] 0
|
||||
S_R All_acks_and_data_no_sharers [0 ] 0
|
||||
S_R GETF [0 ] 0
|
||||
|
||||
NO_R GETX [0 ] 0
|
||||
NO_R GETS [0 ] 0
|
||||
NO_R PUT [0 ] 0
|
||||
NO_R Pf_Replacement [0 ] 0
|
||||
NO_R DMA_READ [0 ] 0
|
||||
NO_R DMA_WRITE [0 ] 0
|
||||
NO_R Ack [0 ] 0
|
||||
NO_R Data [0 ] 0
|
||||
NO_R Exclusive_Data [0 ] 0
|
||||
NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_R GETF [0 ] 0
|
||||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [75 ] 75
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [845 ] 845
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
NO_B GETF [0 ] 0
|
||||
|
||||
NO_B_X GETX [0 ] 0
|
||||
NO_B_X GETS [0 ] 0
|
||||
NO_B_X PUT [0 ] 0
|
||||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
NO_B_X GETF [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
NO_B_S PUT [0 ] 0
|
||||
NO_B_S UnblockS [0 ] 0
|
||||
NO_B_S UnblockM [0 ] 0
|
||||
NO_B_S Pf_Replacement [0 ] 0
|
||||
NO_B_S DMA_READ [0 ] 0
|
||||
NO_B_S DMA_WRITE [0 ] 0
|
||||
NO_B_S GETF [0 ] 0
|
||||
|
||||
NO_B_S_W GETX [0 ] 0
|
||||
NO_B_S_W GETS [0 ] 0
|
||||
NO_B_S_W PUT [0 ] 0
|
||||
NO_B_S_W UnblockS [0 ] 0
|
||||
NO_B_S_W Pf_Replacement [0 ] 0
|
||||
NO_B_S_W DMA_READ [0 ] 0
|
||||
NO_B_S_W DMA_WRITE [0 ] 0
|
||||
NO_B_S_W All_Unblocks [0 ] 0
|
||||
NO_B_S_W GETF [0 ] 0
|
||||
|
||||
O_B GETX [0 ] 0
|
||||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
O_B GETF [0 ] 0
|
||||
|
||||
NO_B_W GETX [0 ] 0
|
||||
NO_B_W GETS [0 ] 0
|
||||
NO_B_W PUT [0 ] 0
|
||||
NO_B_W UnblockS [0 ] 0
|
||||
NO_B_W UnblockM [0 ] 0
|
||||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [846 ] 846
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
O_B_W PUT [0 ] 0
|
||||
O_B_W UnblockS [0 ] 0
|
||||
O_B_W Pf_Replacement [0 ] 0
|
||||
O_B_W DMA_READ [0 ] 0
|
||||
O_B_W DMA_WRITE [0 ] 0
|
||||
O_B_W Memory_Data [0 ] 0
|
||||
O_B_W GETF [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W PUT [0 ] 0
|
||||
NO_W Pf_Replacement [0 ] 0
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W Memory_Data [0 ] 0
|
||||
NO_W GETF [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W PUT [0 ] 0
|
||||
O_W Pf_Replacement [0 ] 0
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W GETF [0 ] 0
|
||||
|
||||
NO_DW_B_W GETX [0 ] 0
|
||||
NO_DW_B_W GETS [0 ] 0
|
||||
NO_DW_B_W PUT [0 ] 0
|
||||
NO_DW_B_W Pf_Replacement [0 ] 0
|
||||
NO_DW_B_W DMA_READ [0 ] 0
|
||||
NO_DW_B_W DMA_WRITE [0 ] 0
|
||||
NO_DW_B_W Ack [0 ] 0
|
||||
NO_DW_B_W Data [0 ] 0
|
||||
NO_DW_B_W Exclusive_Data [0 ] 0
|
||||
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DW_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_W GETX [0 ] 0
|
||||
NO_DR_B_W GETS [0 ] 0
|
||||
NO_DR_B_W PUT [0 ] 0
|
||||
NO_DR_B_W Pf_Replacement [0 ] 0
|
||||
NO_DR_B_W DMA_READ [0 ] 0
|
||||
NO_DR_B_W DMA_WRITE [0 ] 0
|
||||
NO_DR_B_W Memory_Data [0 ] 0
|
||||
NO_DR_B_W Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Data [0 ] 0
|
||||
NO_DR_B_W Data [0 ] 0
|
||||
NO_DR_B_W Exclusive_Data [0 ] 0
|
||||
NO_DR_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_D GETX [0 ] 0
|
||||
NO_DR_B_D GETS [0 ] 0
|
||||
NO_DR_B_D PUT [0 ] 0
|
||||
NO_DR_B_D Pf_Replacement [0 ] 0
|
||||
NO_DR_B_D DMA_READ [0 ] 0
|
||||
NO_DR_B_D DMA_WRITE [0 ] 0
|
||||
NO_DR_B_D Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Data [0 ] 0
|
||||
NO_DR_B_D Data [0 ] 0
|
||||
NO_DR_B_D Exclusive_Data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B_D GETF [0 ] 0
|
||||
|
||||
NO_DR_B GETX [0 ] 0
|
||||
NO_DR_B GETS [0 ] 0
|
||||
NO_DR_B PUT [0 ] 0
|
||||
NO_DR_B Pf_Replacement [0 ] 0
|
||||
NO_DR_B DMA_READ [0 ] 0
|
||||
NO_DR_B DMA_WRITE [0 ] 0
|
||||
NO_DR_B Ack [0 ] 0
|
||||
NO_DR_B Shared_Ack [0 ] 0
|
||||
NO_DR_B Shared_Data [0 ] 0
|
||||
NO_DR_B Data [0 ] 0
|
||||
NO_DR_B Exclusive_Data [0 ] 0
|
||||
NO_DR_B All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B GETF [0 ] 0
|
||||
|
||||
NO_DW_W GETX [0 ] 0
|
||||
NO_DW_W GETS [0 ] 0
|
||||
NO_DW_W PUT [0 ] 0
|
||||
NO_DW_W Pf_Replacement [0 ] 0
|
||||
NO_DW_W DMA_READ [0 ] 0
|
||||
NO_DW_W DMA_WRITE [0 ] 0
|
||||
NO_DW_W Memory_Ack [0 ] 0
|
||||
NO_DW_W GETF [0 ] 0
|
||||
|
||||
O_DR_B_W GETX [0 ] 0
|
||||
O_DR_B_W GETS [0 ] 0
|
||||
O_DR_B_W PUT [0 ] 0
|
||||
O_DR_B_W Pf_Replacement [0 ] 0
|
||||
O_DR_B_W DMA_READ [0 ] 0
|
||||
O_DR_B_W DMA_WRITE [0 ] 0
|
||||
O_DR_B_W Memory_Data [0 ] 0
|
||||
O_DR_B_W Ack [0 ] 0
|
||||
O_DR_B_W Shared_Ack [0 ] 0
|
||||
O_DR_B_W GETF [0 ] 0
|
||||
|
||||
O_DR_B GETX [0 ] 0
|
||||
O_DR_B GETS [0 ] 0
|
||||
O_DR_B PUT [0 ] 0
|
||||
O_DR_B Pf_Replacement [0 ] 0
|
||||
O_DR_B DMA_READ [0 ] 0
|
||||
O_DR_B DMA_WRITE [0 ] 0
|
||||
O_DR_B Ack [0 ] 0
|
||||
O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [0 ] 0
|
||||
WB GETS [1 ] 1
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [75 ] 75
|
||||
WB Writeback_Exclusive_Dirty [767 ] 767
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
WB GETF [0 ] 0
|
||||
|
||||
WB_O_W GETX [0 ] 0
|
||||
WB_O_W GETS [0 ] 0
|
||||
WB_O_W PUT [0 ] 0
|
||||
WB_O_W Pf_Replacement [0 ] 0
|
||||
WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [1 ] 1
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [767 ] 767
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
NO_F GETS [0 ] 0
|
||||
NO_F PUT [0 ] 0
|
||||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [5 ] 5
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
NO_F_W PUT [0 ] 0
|
||||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [4 ] 4
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000172 # Nu
|
|||
sim_ticks 172201 # Number of ticks simulated
|
||||
final_tick 172201 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 1283391 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 149864 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 1943490 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 142952 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 70 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 848 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses
|
||||
|
|
@ -16,8 +16,106 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 50
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 49 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 848 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 897 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1617 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 850 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 767 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 1196 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 550 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 48 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 1 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 599 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.370439 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 172 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 204 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 82 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 60 3.71% 3.71% | 50 3.09% 6.80% | 58 3.59% 10.39% | 80 4.95% 15.34% | 69 4.27% 19.60% | 77 4.76% 24.37% | 71 4.39% 28.76% | 48 2.97% 31.73% | 48 2.97% 34.69% | 38 2.35% 37.04% | 42 2.60% 39.64% | 44 2.72% 42.36% | 39 2.41% 44.77% | 57 3.53% 48.30% | 47 2.91% 51.21% | 44 2.72% 53.93% | 42 2.60% 56.52% | 45 2.78% 59.31% | 53 3.28% 62.59% | 54 3.34% 65.92% | 55 3.40% 69.33% | 41 2.54% 71.86% | 48 2.97% 74.83% | 56 3.46% 78.29% | 29 1.79% 80.09% | 45 2.78% 82.87% | 43 2.66% 85.53% | 51 3.15% 88.68% | 47 2.91% 91.59% | 51 3.15% 94.74% | 42 2.60% 97.34% | 43 2.66% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1617 # Number of accesses per bank
|
||||
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.Load 52 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 53 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 888 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L2_Replacement 840 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.L1_to_L2 16587 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1D 41 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Trigger_L2_to_L1I 9 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Complete_L2_to_L1 50 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Exclusive_Data 850 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 843 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.All_acks_no_sharers 850 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Flush_line 5 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Block_Ack 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 46 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 40 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 762 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Flush_line 4 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L2_Replacement 71 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.L1_to_L2 83 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 11 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Load 5 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Store 62 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L2_Replacement 769 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.L1_to_L2 809 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 30 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1I 9 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.Store 11 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MR.L1_to_L2 90 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Ifetch 9 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Store 29 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.L1_to_L2 25 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMR.Flush_line 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.L1_to_L2 9996 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Exclusive_Data 761 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.L1_to_L2 306 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 85 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.Store 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.L1_to_L2 4592 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 761 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.L1_to_L2 529 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Exclusive_Data 85 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Load 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Ifetch 3 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Store 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 838 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MT.Store 2 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MT.L1_to_L2 54 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 11 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMT.Store 18 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMT.L1_to_L2 103 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 39 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI_F.Writeback_Ack 5 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_F.Block_Ack 1 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM_F.Exclusive_Data 4 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MM_WF.All_acks_no_sharers 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 761 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETS 87 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUT 913 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.UnblockM 845 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 75 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 767 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 850 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 767 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETF 5 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTF 5 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.PUT 838 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO.GETF 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETX 761 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETS 85 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.E.GETF 4 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.PUT 75 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B.UnblockM 845 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_B_W.Memory_Data 846 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.GETS 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 75 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 767 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.GETS 1 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 767 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_F.PUTF 5 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.NO_F_W.Memory_Data 4 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Feb/02/2013 08:06:19
|
||||
Real time: Jun/08/2013 13:44:09
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.39
|
||||
Virtual_time_in_minutes: 0.0065
|
||||
Virtual_time_in_hours: 0.000108333
|
||||
Virtual_time_in_days: 4.51389e-06
|
||||
Virtual_time_in_seconds: 0.45
|
||||
Virtual_time_in_minutes: 0.0075
|
||||
Virtual_time_in_hours: 0.000125
|
||||
Virtual_time_in_days: 5.20833e-06
|
||||
|
||||
Ruby_current_time: 221941
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 221941
|
||||
|
||||
mbytes_resident: 49.5742
|
||||
mbytes_total: 265.59
|
||||
resident_ratio: 0.186701
|
||||
|
||||
ruby_cycles_executed: [ 221942 ]
|
||||
mbytes_resident: 50.1211
|
||||
mbytes_total: 138.504
|
||||
resident_ratio: 0.361931
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -63,7 +61,6 @@ Request vs. RubySystem State Profile
|
|||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
|
|
@ -84,11 +81,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9328
|
||||
page_reclaims: 9501
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 80
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -132,129 +129,3 @@ links_utilized_percent_switch_2: 2.06125
|
|||
outgoing_messages_switch_2_link_1_Control: 916 7328 [ 0 0 916 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 914 65808 [ 0 0 914 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [42 ] 42
|
||||
Ifetch [58 ] 58
|
||||
Store [855 ] 855
|
||||
Data [916 ] 916
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [914 ] 914
|
||||
Writeback_Ack [912 ] 912
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [42 ] 42
|
||||
I Ifetch [56 ] 56
|
||||
I Store [819 ] 819
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [2 ] 2
|
||||
M Store [36 ] 36
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [914 ] 914
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [912 ] 912
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [98 ] 98
|
||||
|
||||
IM Data [818 ] 818
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1830
|
||||
memory_reads: 916
|
||||
memory_writes: 914
|
||||
memory_refreshes: 1542
|
||||
memory_total_request_delays: 1930
|
||||
memory_delays_per_request: 1.05464
|
||||
memory_delays_in_input_queue: 182
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1745
|
||||
memory_stalls_for_bank_busy: 343
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 167
|
||||
memory_stalls_for_bus: 617
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 556
|
||||
memory_stalls_for_read_read_turnaround: 62
|
||||
accesses_per_bank: 64 60 44 96 107 64 62 38 55 54 54 36 48 34 66 48 56 54 60 70 56 62 44 62 48 58 64 72 46 46 36 66
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [916 ] 916
|
||||
GETS [0 ] 0
|
||||
PUTX [914 ] 914
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [916 ] 916
|
||||
Memory_Ack [914 ] 914
|
||||
|
||||
- Transitions -
|
||||
I GETX [916 ] 916
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [914 ] 914
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [916 ] 916
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [914 ] 914
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,51 @@ sim_seconds 0.000222 # Nu
|
|||
sim_ticks 221941 # Number of ticks simulated
|
||||
final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 2117650 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 149428 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 3023855 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 141832 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 38 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 917 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 955 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1830 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 916 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 914 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 1542 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1745 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 182 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1930 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 1.054645 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 343 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 617 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 556 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 62 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 167 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 64 3.50% 3.50% | 60 3.28% 6.78% | 44 2.40% 9.18% | 96 5.25% 14.43% | 107 5.85% 20.27% | 64 3.50% 23.77% | 62 3.39% 27.16% | 38 2.08% 29.23% | 55 3.01% 32.24% | 54 2.95% 35.19% | 54 2.95% 38.14% | 36 1.97% 40.11% | 48 2.62% 42.73% | 34 1.86% 44.59% | 66 3.61% 48.20% | 48 2.62% 50.82% | 56 3.06% 53.88% | 54 2.95% 56.83% | 60 3.28% 60.11% | 70 3.83% 63.93% | 56 3.06% 66.99% | 62 3.39% 70.38% | 44 2.40% 72.79% | 62 3.39% 76.17% | 48 2.62% 78.80% | 58 3.17% 81.97% | 64 3.50% 85.46% | 72 3.93% 89.40% | 46 2.51% 91.91% | 46 2.51% 94.43% | 36 1.97% 96.39% | 66 3.61% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1830 # Number of accesses per bank
|
||||
|
||||
system.ruby.l1_cntrl0.Load 42 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Ifetch 58 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Store 855 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Data 916 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Replacement 914 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.Writeback_Ack 912 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Load 42 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Ifetch 56 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.I.Store 819 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Ifetch 2 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Store 36 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.M.Replacement 914 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.MI.Writeback_Ack 912 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IS.Data 98 0.00% 0.00%
|
||||
system.ruby.l1_cntrl0.IM.Data 818 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.GETX 916 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.PUTX 914 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 916 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Ack 914 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.I.GETX 916 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.M.PUTX 914 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.IM.Memory_Data 916 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.MI.Memory_Ack 914 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue