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Stats: Update stats to reflect SimpleMemory bandwidth

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This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
This commit is contained in:
Andreas Hansson 2012-09-18 10:30:04 -04:00
parent 7c55464aac
commit d2b57a7473
27 changed files with 14963 additions and 14953 deletions
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2917
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
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tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.274137 # Number of seconds simulated
sim_ticks 274137499500 # Number of ticks simulated
final_tick 274137499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 274137453500 # Number of ticks simulated
final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167497 # Simulator instruction rate (inst/s)
host_op_rate 167497 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 76292716 # Simulator tick rate (ticks/s)
host_mem_usage 218988 # Number of bytes of host memory used
host_seconds 3593.23 # Real time elapsed on the host
host_inst_rate 134061 # Simulator instruction rate (inst/s)
host_op_rate 134061 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61063086 # Simulator tick rate (ticks/s)
host_mem_usage 219148 # Number of bytes of host memory used
host_seconds 4489.41 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@ -24,32 +24,32 @@ system.physmem.num_reads::total 26157 # Nu
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5910260 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6106600 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5910260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6314612 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114518785 # DTB read hits
system.cpu.dtb.read_hits 114518787 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114521416 # DTB read accesses
system.cpu.dtb.write_hits 39662429 # DTB write hits
system.cpu.dtb.read_accesses 114521418 # DTB read accesses
system.cpu.dtb.write_hits 39662426 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39664731 # DTB write accesses
system.cpu.dtb.data_hits 154181214 # DTB hits
system.cpu.dtb.write_accesses 39664728 # DTB write accesses
system.cpu.dtb.data_hits 154181213 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154186147 # DTB accesses
system.cpu.dtb.data_accesses 154186146 # DTB accesses
system.cpu.itb.fetch_hits 25086764 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 548275000 # number of cpu cycles simulated
system.cpu.numCycles 548274908 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups
@ -80,13 +80,13 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu
system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541561070 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005415916 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 255070177 # Number of Registers Read Through Forwarding Logic
system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155050348 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken).
@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 412334459 # Nu
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 539843930 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 672410 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59138192 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489136808 # Number of cycles cpu stages are processed.
system.cpu.activity 89.213772 # Percentage of cycles cpu is active
system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed.
system.cpu.activity 89.213788 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
@ -120,28 +120,28 @@ system.cpu.cpi_total 0.910972 # CP
system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 209383014 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338891986 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.810585 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 237433241 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310841759 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 56.694498 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 206489440 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341785560 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.338345 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 436702963 # Number of cycles 0 instructions are processed.
system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.349649 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 201266098 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347008902 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.291031 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 728.512372 # Cycle average of tags in use
system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use
system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 728.512372 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits
@ -220,12 +220,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801
system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4093.836595 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use
system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4093.836595 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits
@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 1559322 # n
system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses
system.cpu.dcache.overall_misses::total 1559322 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7771987500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228669000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 30228669000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 38000656500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 38000656500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 38000656500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 38000656500 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
@ -268,19 +268,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.010128
system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24369.986763 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24369.986763 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 28255500 # number of cycles access was blocked
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7934.709351 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136800000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136800000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820778500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7820778500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820778500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7820778500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@ -318,24 +318,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 917 # number of replacements
system.cpu.l2cache.tagsinuse 22837.818259 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21635.297134 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 719.415397 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 483.105728 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy
@ -365,16 +365,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 841 #
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 260244500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215316500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1215316500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1430177000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1475561000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1430177000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1475561000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses)
@ -400,21 +400,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 3459500 # number of cycles access was blocked
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 116 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 26157
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954428500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954428500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119789500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1154935500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119789500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1154935500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses
@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1052
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
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1018
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
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168
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.389171 # Number of seconds simulated
sim_ticks 389171398000 # Number of ticks simulated
final_tick 389171398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 389171400000 # Number of ticks simulated
final_tick 389171400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 172352 # Simulator instruction rate (inst/s)
host_op_rate 172895 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47869738 # Simulator tick rate (ticks/s)
host_mem_usage 232600 # Number of bytes of host memory used
host_seconds 8129.80 # Real time elapsed on the host
host_inst_rate 248197 # Simulator instruction rate (inst/s)
host_op_rate 248980 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 68935275 # Simulator tick rate (ticks/s)
host_mem_usage 223264 # Number of bytes of host memory used
host_seconds 5645.46 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory
@ -35,7 +35,7 @@ system.physmem.bw_total::cpu.inst 201783 # To
system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 778342797 # number of cpu cycles simulated
system.cpu.numCycles 778342801 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups
@ -52,16 +52,16 @@ system.cpu.fetch.Branches 98197174 # Nu
system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 264316799 # Number of cycles fetch has spent blocked
system.cpu.fetch.BlockedCycles 264316803 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 778298464 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 778298468 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 447887260 57.55% 57.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 447887264 57.55% 57.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total)
@ -73,24 +73,24 @@ system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 778298464 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 778298468 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 217730423 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 214714894 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 285147826 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 43019383 # Number of cycles decode is unblocking
system.cpu.decode.IdleCycles 217730424 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 214714897 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 285147825 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 43019384 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 241679768 # Number of cycles rename is idle
system.cpu.rename.IdleCycles 241679770 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 51960575 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializeStallCycles 51960576 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 127037199 # Number of cycles rename is unblocking
system.cpu.rename.UnblockCycles 127037200 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 73402474 # Number of times rename has blocked due to LSQ full
system.cpu.rename.LSQFullEvents 73402475 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made
@ -104,7 +104,7 @@ system.cpu.rename.skidInsts 273063750 # co
system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 82754828 # Number of conflicting stores.
system.cpu.memDep0.conflictingStores 82754827 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued
@ -112,23 +112,23 @@ system.cpu.iq.iqSquashedInstsIssued 54636 # Nu
system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 778298464 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 778298468 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 147064057 18.90% 18.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 186545297 23.97% 42.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 210910023 27.10% 69.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 147064058 18.90% 18.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 186545303 23.97% 42.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 210910021 27.10% 69.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 70782480 9.09% 95.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 70782478 9.09% 95.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7762488 1.00% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7762489 1.00% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 778298464 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 778298468 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available
@ -159,7 +159,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1139490 70.19% 87.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1139492 70.19% 87.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
@ -199,15 +199,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued
system.cpu.iq.rate 1.876768 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1623524 # FU busy when requested
system.cpu.iq.fu_busy_cnt 1623526 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3683829696 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 3683829702 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1453371390 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 1453371392 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
@ -245,8 +245,8 @@ system.cpu.iew.exec_stores 170572268 # Nu
system.cpu.iew.exec_rate 1.869642 # Inst execution rate
system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1154316777 # num instructions producing a value
system.cpu.iew.wb_consumers 1205166277 # num instructions consuming a value
system.cpu.iew.wb_producers 1154316776 # num instructions producing a value
system.cpu.iew.wb_consumers 1205166275 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back
@ -254,23 +254,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 760613137 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 760613141 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 276879553 36.40% 68.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43195227 5.68% 73.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 276879555 36.40% 68.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43195229 5.68% 73.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19686775 2.59% 83.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13341138 1.75% 85.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19686776 2.59% 83.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13341139 1.75% 85.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10352977 1.36% 90.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 70115497 9.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10352976 1.36% 90.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 70115496 9.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 760613137 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 760613141 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -281,9 +281,9 @@ system.cpu.commit.branches 86248928 # Nu
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
system.cpu.commit.bw_lim_events 70115497 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 70115496 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2304117867 # The number of ROB reads
system.cpu.rob.rob_reads 2304117872 # The number of ROB reads
system.cpu.rob.rob_writes 3245080355 # The number of ROB writes
system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling
@ -415,14 +415,14 @@ system.cpu.dcache.overall_misses::cpu.data 2771932 #
system.cpu.dcache.overall_misses::total 2771932 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11940266500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11940266500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531206941 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 57531206941 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531211441 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 57531211441 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 69471473441 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 69471473441 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 69471473441 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 69471473441 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 69471477941 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 69471477941 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 69471477941 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 69471477941 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 201522884 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 201522884 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
@ -445,14 +445,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.007525
system.cpu.dcache.overall_miss_rate::total 0.007525 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13262.541930 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13262.541930 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.524956 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.524956 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.527361 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.527361 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25062.473914 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25062.473914 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.475537 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25062.475537 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.475537 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25062.475537 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
@ -483,14 +483,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 461980
system.cpu.dcache.overall_mshr_misses::total 461980 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 927311500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 927311500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914389505 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914389505 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914391005 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914391005 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 47000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 47000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841701005 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6841701005 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841701005 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6841701005 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841702505 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6841702505 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841702505 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6841702505 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001570 # mshr miss rate for WriteReq accesses
@ -503,24 +503,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254
system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4637.577767 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.577767 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.938086 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.938086 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.943810 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.943810 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6714.285714 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6714.285714 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.520986 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.520986 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.520986 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.520986 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2682 # number of replacements
system.cpu.l2cache.tagsinuse 22381.194058 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 22381.194051 # Cycle average of tags in use
system.cpu.l2cache.total_refs 541474 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24308 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.275547 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20744.863113 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 994.979192 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 641.351753 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 20744.863109 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 994.979191 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 641.351751 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.633083 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.030364 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019573 # Average percentage of cache occupancy
@ -552,14 +552,14 @@ system.cpu.l2cache.overall_misses::total 27465 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42694000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 151831500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 194525500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842839500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 842839500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842840000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 842840000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42694000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 994671000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1037365000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 994671500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1037365500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42694000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 994671000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1037365000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 994671500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1037365500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1363 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 199948 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 201311 # number of ReadReq accesses(hits+misses)
@ -587,14 +587,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.059275 #
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34795.436023 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.836528 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34356.322854 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.065541 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.065541 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37770.435099 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.577712 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37770.453304 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37770.435099 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.577712 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37770.453304 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked

144
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.064346 # Number of seconds simulated
sim_ticks 64346039000 # Number of ticks simulated
final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 64346040000 # Number of ticks simulated
final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 77016 # Simulator instruction rate (inst/s)
host_op_rate 135613 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31367260 # Simulator tick rate (ticks/s)
host_mem_usage 410996 # Number of bytes of host memory used
host_seconds 2051.38 # Real time elapsed on the host
host_inst_rate 132449 # Simulator instruction rate (inst/s)
host_op_rate 233222 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53944275 # Simulator tick rate (ticks/s)
host_mem_usage 365660 # Number of bytes of host memory used
host_seconds 1192.82 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192462 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
@ -24,7 +24,7 @@ system.physmem.num_reads::total 30652 # Nu
system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory
system.physmem.num_writes::total 319 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s)
@ -32,10 +32,10 @@ system.physmem.bw_write::writebacks 317284 # Wr
system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 128692079 # number of cpu cycles simulated
system.cpu.numCycles 128692081 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups
@ -287,7 +287,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 426345169 # The number of ROB reads
system.cpu.rob.rob_writes 653150724 # The number of ROB writes
system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
@ -301,12 +301,12 @@ system.cpu.fp_regfile_reads 165 # nu
system.cpu.fp_regfile_writes 88 # number of floating regfile writes
system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads
system.cpu.icache.replacements 92 # number of replacements
system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use
system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use
system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits
@ -321,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 1385 # n
system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses
system.cpu.icache.overall_misses::total 1385 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses
@ -339,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051
system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37151.985560 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37151.985560 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37151.985560 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37151.985560 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -365,24 +365,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1078
system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39433000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 39433000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39433000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 39433000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39433000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 39433000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39438000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 39438000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39438000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 39438000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39438000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 39438000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36584.415584 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36584.415584 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2072148 # number of replacements
system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use
@ -493,14 +493,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866
system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1466 # number of replacements
system.cpu.l2cache.tagsinuse 19909.538266 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 19909.538394 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19409.012511 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 268.281429 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 232.244325 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 19409.012644 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 268.281425 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 232.244324 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy
@ -533,17 +533,17 @@ system.cpu.l2cache.demand_misses::total 30652 # nu
system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses
system.cpu.l2cache.overall_misses::total 30652 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37875000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37880000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 58841500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 58846500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 37875000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 37880000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1047724000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 37875000 # number of overall miss cycles
system.cpu.l2cache.demand_miss_latency::total 1047729000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 37880000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1047724000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1047729000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses)
@ -572,17 +572,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014756 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35468.164794 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -606,19 +606,19 @@ system.cpu.l2cache.demand_mshr_misses::total 30652
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses
@ -632,19 +632,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1108
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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1027
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
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tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.646278 # Number of seconds simulated
sim_ticks 646278131000 # Number of ticks simulated
final_tick 646278131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 646278143000 # Number of ticks simulated
final_tick 646278143000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 212773 # Simulator instruction rate (inst/s)
host_op_rate 212773 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 75429257 # Simulator tick rate (ticks/s)
host_mem_usage 229040 # Number of bytes of host memory used
host_seconds 8568.00 # Real time elapsed on the host
host_inst_rate 208687 # Simulator instruction rate (inst/s)
host_op_rate 208687 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 73980757 # Simulator tick rate (ticks/s)
host_mem_usage 229204 # Number of bytes of host memory used
host_seconds 8735.76 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory
@ -24,16 +24,16 @@ system.physmem.num_reads::total 1479012 # Nu
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 146167855 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 146464445 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 146167852 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 146464443 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 146167855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 153089259 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 146167852 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 153089256 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 1292556263 # number of cpu cycles simulated
system.cpu.numCycles 1292556287 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups
@ -78,22 +78,22 @@ system.cpu.BPredUnit.BTBHits 262010178 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 421195056 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 421195062 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed
system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 162914777 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 98034183 # Number of cycles fetch has spent blocked
system.cpu.fetch.SquashCycles 162914776 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 98034186 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9273 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingTrapStallCycles 9284 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1292428853 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 1292428872 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 654074173 50.61% 50.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 654074192 50.61% 50.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total)
@ -105,65 +105,65 @@ system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1292428853 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1292428872 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 452871359 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 80658875 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 614115226 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9960098 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 134823295 # Number of cycles decode is squashing
system.cpu.decode.IdleCycles 452871377 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 80658879 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 614115225 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9960097 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 134823294 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3231646724 # Number of instructions handled by decode
system.cpu.decode.DecodedInsts 3231646719 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 134823295 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 482927881 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 33597057 # Number of cycles rename is blocking
system.cpu.rename.SquashCycles 134823294 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 482927898 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 33597059 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 592678256 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 48376043 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3142025534 # Number of instructions processed by rename
system.cpu.rename.RunCycles 592678255 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 48376045 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3142025529 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 42577596 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2088048295 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3654580538 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3537192552 # Number of integer rename lookups
system.cpu.rename.LSQFullEvents 42577598 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2088048291 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3654580534 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3537192548 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 703079225 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 703079221 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 143016933 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 739120184 # Number of loads inserted to the mem dependence unit.
system.cpu.rename.skidInsts 143016934 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 739120183 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2647443518 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 2647443516 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2196739038 # Number of instructions issued
system.cpu.iq.iqInstsIssued 2196739037 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 824288888 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 711675230 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedInstsExamined 824288886 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 711675229 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1292428853 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 1292428872 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 470829214 36.43% 36.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 470829232 36.43% 36.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 252835920 19.56% 72.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 120249082 9.30% 82.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 106312850 8.23% 90.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 252835921 19.56% 72.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 120249084 9.30% 82.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 106312849 8.23% 90.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 21017975 1.63% 98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 17286985 1.34% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 21017973 1.63% 98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 17286986 1.34% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1292428853 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1292428872 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available
@ -199,7 +199,7 @@ system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1257954368 57.26% 57.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1257954367 57.26% 57.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued
@ -232,21 +232,21 @@ system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Ty
system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2196739038 # Type of FU issued
system.cpu.iq.FU_type_0::total 2196739037 # Type of FU issued
system.cpu.iq.rate 1.699531 # Inst issue rate
system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5585448848 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3387972541 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_reads 5585448865 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3387972537 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2153745376 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 2153745375 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 228050158 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 228050157 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed
@ -255,12 +255,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 134823295 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 4267154 # Number of cycles IEW is blocking
system.cpu.iew.iewSquashCycles 134823294 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 4267155 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3006059050 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2702145 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 739120184 # Number of dispatched load instructions
system.cpu.iew.iewDispatchedInsts 3006059047 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2702146 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 739120183 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall
@ -271,41 +271,41 @@ system.cpu.iew.predictedNotTakenIncorrect 31610 # N
system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 90815737 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecSquashedInsts 90815736 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 358615413 # number of nop insts executed
system.cpu.iew.exec_nop 358615412 # number of nop insts executed
system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed
system.cpu.iew.exec_branches 282350798 # Number of branches executed
system.cpu.iew.exec_stores 292282128 # Number of stores executed
system.cpu.iew.exec_rate 1.629270 # Inst execution rate
system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1185212781 # num instructions producing a value
system.cpu.iew.wb_consumers 1754721969 # num instructions consuming a value
system.cpu.iew.wb_producers 1185212780 # num instructions producing a value
system.cpu.iew.wb_consumers 1754721967 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 980398498 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 980398495 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1157605558 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 1157605578 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 541345046 46.76% 46.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 227581474 19.66% 66.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 119272187 10.30% 76.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 56742029 4.90% 81.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 51019589 4.41% 86.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24162951 2.09% 88.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 18255182 1.58% 89.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 541345066 46.76% 46.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 227581476 19.66% 66.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 119272186 10.30% 76.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 56742028 4.90% 81.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 51019590 4.41% 86.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24162950 2.09% 88.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 18255180 1.58% 89.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 103621766 8.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 103621768 8.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1157605558 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1157605578 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -316,12 +316,12 @@ system.cpu.commit.branches 266706457 # Nu
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
system.cpu.commit.bw_lim_events 103621766 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 103621768 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 4037733484 # The number of ROB reads
system.cpu.rob.rob_writes 6113598013 # The number of ROB writes
system.cpu.timesIdled 3574 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 127410 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 4037733499 # The number of ROB reads
system.cpu.rob.rob_writes 6113598006 # The number of ROB writes
system.cpu.timesIdled 3575 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 127415 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
@ -356,12 +356,12 @@ system.cpu.icache.demand_misses::cpu.inst 11347 # n
system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses
system.cpu.icache.overall_misses::total 11347 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 204563500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 204563500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 204563500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 204563500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 204563500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 204563500 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 204562000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 204562000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 204562000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 204562000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 204562000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 204562000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses
@ -374,12 +374,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000028
system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.980964 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18027.980964 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18027.980964 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18027.980964 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.848771 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18027.848771 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18027.848771 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18027.848771 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -446,14 +446,14 @@ system.cpu.dcache.demand_misses::cpu.data 2543931 # n
system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses
system.cpu.dcache.overall_misses::total 2543931 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609230000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 76609230000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362374985 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 30362374985 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 106971604985 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 106971604985 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 106971604985 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 106971604985 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609210500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 76609210500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362476485 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 30362476485 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 106971686985 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 106971686985 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 106971686985 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 106971686985 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
@ -472,14 +472,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003798
system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.875316 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.875316 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.193322 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.193322 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42049.727365 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 42049.727365 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.865203 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.865203 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.358194 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.358194 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42049.759598 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 42049.759598 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
@ -506,14 +506,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1532162
system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266374000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266374000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176553000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176553000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 53442927000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 53442927000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266349000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266349000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176578500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176578500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 53442927500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 53442927500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
@ -522,24 +522,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288
system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.940516 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.940516 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44360.928401 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44360.928401 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.923399 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.923399 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.284511 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.284511 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480672 # number of replacements
system.cpu.l2cache.tagsinuse 32700.801266 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 32700.801233 # Cycle average of tags in use
system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 3222.422706 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 46.121130 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 29432.257430 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 3222.422931 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 46.121134 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 29432.257169 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.098341 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001408 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.898201 # Average percentage of cache occupancy
@ -569,16 +569,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2995 #
system.cpu.l2cache.overall_misses::cpu.data 1476017 # number of overall misses
system.cpu.l2cache.overall_misses::total 1479012 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106968000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399950500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 48506918500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813587500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2813587500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399927000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 48506895000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813613000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2813613000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 106968000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 51213538000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 51320506000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 51213540000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 51320508000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 106968000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 51213538000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 51320506000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 51213540000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 51320508000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10134 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460549 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1470683 # number of ReadReq accesses(hits+misses)
@ -604,16 +604,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295540
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963356 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.958968 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35715.525876 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.594752 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.498073 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.552099 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.552099 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.578075 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.481432 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.933527 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.933527 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34699.181616 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34699.182968 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34699.181616 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34699.182968 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 107500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked
@ -636,16 +636,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995
system.cpu.l2cache.overall_mshr_misses::cpu.data 1476017 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1479012 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97365000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717529000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814894000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612258000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612258000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717505000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814870000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612284000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612284000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97365000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329787000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 46427152000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329789000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 46427154000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97365000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329787000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 46427152000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329789000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 46427154000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964817 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960206 # mshr miss rate for ReadReq accesses
@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295540
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.958968 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.755946 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.906338 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.071858 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.071858 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.738915 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.889342 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.460765 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.460765 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1162
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
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262
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.047910 # Number of seconds simulated
sim_ticks 47910283500 # Number of ticks simulated
final_tick 47910283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.047911 # Number of seconds simulated
sim_ticks 47910588500 # Number of ticks simulated
final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 137428 # Simulator instruction rate (inst/s)
host_op_rate 137428 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 74532010 # Simulator tick rate (ticks/s)
host_mem_usage 227148 # Number of bytes of host memory used
host_seconds 642.82 # Real time elapsed on the host
host_inst_rate 102205 # Simulator instruction rate (inst/s)
host_op_rate 102205 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55429613 # Simulator tick rate (ticks/s)
host_mem_usage 227308 # Number of bytes of host memory used
host_seconds 864.35 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160515 # Nu
system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10756104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 214420773 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 225176877 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10756104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10756104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 154922899 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 154922899 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 154922899 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10756104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 214420773 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 380099775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 95820568 # number of cpu cycles simulated
system.cpu.numCycles 95821178 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups
@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 44775821 # Nu
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 78582823 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 467369 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 25529650 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 70290918 # Number of cycles cpu stages are processed.
system.cpu.activity 73.356816 # Percentage of cycles cpu is active
system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed.
system.cpu.activity 73.356346 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
@ -114,34 +114,34 @@ system.cpu.committedInsts 88340673 # Nu
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 1.084671 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.084671 # CPI: Total CPI of All Threads
system.cpu.ipc 0.921939 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads
system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.921939 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 42393437 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 53427131 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 55.757477 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 53162471 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42658097 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 44.518727 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 52693934 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43126634 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.007700 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 73699390 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22121178 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.086043 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 49718373 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46102195 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 48.113047 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 85335 # number of replacements
system.cpu.icache.tagsinuse 1885.674809 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use
system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1885.674809 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits
@ -156,12 +156,12 @@ system.cpu.icache.demand_misses::cpu.inst 118639 # n
system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses
system.cpu.icache.overall_misses::total 118639 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081821000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2081821000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2081821000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2081821000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2081821000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2081821000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses
@ -174,12 +174,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009509
system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17547.526530 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17547.526530 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -200,32 +200,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 87381
system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364843500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1364843500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364843500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1364843500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364843500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1364843500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200251 # number of replacements
system.cpu.dcache.tagsinuse 4073.238674 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use
system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4073.238674 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits
@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 764068 # n
system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses
system.cpu.dcache.overall_misses::total 764068 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4228645500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 42086848500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 42086848500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 46315494000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46315494000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46315494000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46315494000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
@ -268,20 +268,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.021899
system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60616.979117 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60616.979117 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6945858000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks
@ -304,12 +304,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204347
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7868977000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7868977000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9805822000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9805822000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9805822000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9805822000 # number of overall MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
@ -320,24 +320,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54805.523053 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54805.523053 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 136141 # number of replacements
system.cpu.l2cache.tagsinuse 28773.047265 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 28773.050902 # Cycle average of tags in use
system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 25287.688081 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1723.908362 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1761.450821 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 25287.699561 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1723.905670 # Average occupied blocks per requestor
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@ -367,14 +367,14 @@ system.cpu.l2cache.overall_misses::total 168567 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 427362500 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6840080000 # number of ReadExReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 8381082500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8808445000 # number of overall miss cycles
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@ -402,14 +402,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.577822 #
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52186.973475 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52186.973475 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52195.226177 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52195.226177 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52248.444239 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52254.860085 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52248.444239 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52254.860085 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 168567
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5254733000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5254733000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255819000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255819000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6436171500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6765325500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6437257500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6766411500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6436171500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6765325500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6437257500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6766411500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses
@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1096
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
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1144
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
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356
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.996061 # Number of seconds simulated
sim_ticks 996061088500 # Number of ticks simulated
final_tick 996061088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.996063 # Number of seconds simulated
sim_ticks 996062814500 # Number of ticks simulated
final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139633 # Simulator instruction rate (inst/s)
host_op_rate 139633 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 76428343 # Simulator tick rate (ticks/s)
host_mem_usage 218940 # Number of bytes of host memory used
host_seconds 13032.61 # Real time elapsed on the host
host_inst_rate 142352 # Simulator instruction rate (inst/s)
host_op_rate 142352 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 77916645 # Simulator tick rate (ticks/s)
host_mem_usage 219096 # Number of bytes of host memory used
host_seconds 12783.70 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
@ -24,32 +24,32 @@ system.physmem.num_reads::total 2150541 # Nu
system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 138123705 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 138178898 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 67370390 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 67370390 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 67370390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 138123705 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 205549288 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444620723 # DTB read hits
system.cpu.dtb.read_hits 444620890 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449517801 # DTB read accesses
system.cpu.dtb.read_accesses 449517968 # DTB read accesses
system.cpu.dtb.write_hits 160920434 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162621738 # DTB write accesses
system.cpu.dtb.data_hits 605541157 # DTB hits
system.cpu.dtb.data_hits 605541324 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612139539 # DTB accesses
system.cpu.dtb.data_accesses 612139706 # DTB accesses
system.cpu.itb.fetch_hits 232151959 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1992122178 # number of cpu cycles simulated
system.cpu.numCycles 1992125630 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups
@ -80,9 +80,9 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu
system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1669698374 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3045900991 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File
@ -93,16 +93,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 12122106
system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139625101 # Number of Instructions Executed.
system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1749883167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7972682 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 415150633 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576971545 # Number of cycles cpu stages are processed.
system.cpu.activity 79.160383 # Percentage of cycles cpu is active
system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed.
system.cpu.activity 79.160246 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
@ -114,34 +114,34 @@ system.cpu.committedInsts 1819780127 # Nu
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.094705 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.094705 # CPI: Total CPI of All Threads
system.cpu.ipc 0.913488 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads
system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.913488 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 801357098 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1190765080 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 59.773697 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1059714238 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 932407940 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.804757 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1018188148 # Number of cycles 0 instructions are processed.
system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.889272 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1582467246 # Number of cycles 0 instructions are processed.
system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.563745 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 969329070 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022793108 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 51.341887 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 666.783228 # Cycle average of tags in use
system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use
system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 666.783228 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits
@ -219,39 +219,39 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107309 # number of replacements
system.cpu.dcache.tagsinuse 4082.354199 # Cycle average of tags in use
system.cpu.dcache.total_refs 595073835 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111405 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.310875 # Average number of references to valid blocks.
system.cpu.dcache.replacements 9107311 # number of replacements
system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use
system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4082.354199 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437271435 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437271435 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157802400 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157802400 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 595073835 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 595073835 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595073835 # number of overall hits
system.cpu.dcache.overall_hits::total 595073835 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324228 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324228 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2926102 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2926102 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10250330 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10250330 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10250330 # number of overall misses
system.cpu.dcache.overall_misses::total 10250330 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 166496556500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 166496556500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 130053734500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 296550291000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 296550291000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 296550291000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 296550291000 # number of overall miss cycles
system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits
system.cpu.dcache.overall_hits::total 595073825 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses
system.cpu.dcache.overall_misses::total 10250340 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
@ -268,48 +268,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016934
system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28930.804277 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28930.804277 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 76478500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8150814500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14619 # number of cycles access was blocked
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5231.445379 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3389633 # number of writebacks
system.cpu.dcache.writebacks::total 3389633 # number of writebacks
system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks
system.cpu.dcache.writebacks::total 3389635 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 1036977 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1138925 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1138925 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1138925 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111405 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111405 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111405 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111405 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938235500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938235500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71711487500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 71711487500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212649723000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 212649723000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212649723000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 212649723000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
@ -318,38 +318,38 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.368800 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.368800 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37960.160127 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37960.160127 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2133758 # number of replacements
system.cpu.l2cache.tagsinuse 30551.127244 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8448350 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.905038 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 184402684000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14423.839124 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 34.322166 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16092.965953 # Average occupied blocks per requestor
system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3389633 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3389633 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits
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system.cpu.l2cache.overall_hits::total 6961723 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits
system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses
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@ -362,29 +362,29 @@ system.cpu.l2cache.overall_misses::cpu.inst 859 #
system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses
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system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 113406761500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 113452921500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 113463033500 # number of overall miss cycles
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system.cpu.l2cache.Writeback_accesses::writebacks 3389633 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 3389635 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses
@ -397,21 +397,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1
system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52485.997375 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52486.786477 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53219.435113 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53219.435113 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52487.387313 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52488.175538 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53288.373287 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53288.373287 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52781.692374 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52755.525935 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 3381000 # number of cycles access was blocked
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52781.692374 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 3730000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 111 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 142 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30459.459459 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26267.605634 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
@ -429,16 +429,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 859
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses
@ -451,16 +451,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
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tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
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tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 1.207291 # Nu
sim_ticks 1207290627000 # Number of ticks simulated
final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1000042 # Simulator instruction rate (inst/s)
host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19638848032 # Simulator tick rate (ticks/s)
host_mem_usage 383956 # Number of bytes of host memory used
host_seconds 61.47 # Real time elapsed on the host
host_inst_rate 965295 # Simulator instruction rate (inst/s)
host_op_rate 1230212 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 18956490102 # Simulator tick rate (ticks/s)
host_mem_usage 382720 # Number of bytes of host memory used
host_seconds 63.69 # Real time elapsed on the host
sim_insts 61477134 # Number of instructions simulated
sim_ops 78349023 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
@ -89,20 +89,20 @@ system.physmem.bw_total::cpu1.inst 267624 # To
system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 69267 # number of replacements
system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use
system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use
system.l2c.total_refs 1645693 # Total number of references to valid blocks.
system.l2c.sampled_refs 134464 # Sample count of references to valid blocks.
system.l2c.avg_refs 12.238912 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor
system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
@ -189,40 +189,40 @@ system.l2c.overall_misses::cpu1.data 75979 # nu
system.l2c.overall_misses::total 161841 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 189491500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1161637500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 30055000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 27347000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 57402000 # number of UpgradeReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6038000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 9730000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3494564965 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3764669994 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7259234959 # number of ReadExReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 298918500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3904253465 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 263122000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3954161494 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8420872459 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 298918500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3904253465 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 263122000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3954161494 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8420872459 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses)
@ -299,40 +299,40 @@ system.l2c.overall_miss_rate::cpu1.data 0.278223 # mi
system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52072.686928 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.243197 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7630.301339 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 6925.916988 # average UpgradeReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 9231.499051 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52025.219547 # average ReadExReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 9229.601518 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52025.212380 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52031.762403 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52032.102242 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52031.762403 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52032.102242 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -387,53 +387,53 @@ system.l2c.overall_mshr_misses::cpu1.data 75979 # n
system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229974000 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202602000 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143675000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 332230000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22768000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19442000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143713000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 332263000 # number of UpgradeReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::total 6478749000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu0.inst 229995000 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu1.data 3042449000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6478749000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448668498 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448669498 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365734497 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167083883995 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365762499 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167083912997 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843793500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 31972096500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843801500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 31972104500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576971498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576972498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 199055980495 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses
@ -472,40 +472,40 @@ system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223
system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835 # average ReadExReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
@ -586,8 +586,8 @@ system.cpu0.num_fp_register_writes 840 # nu
system.cpu0.num_mem_refs 13404188 # number of memory refs
system.cpu0.num_load_insts 7413537 # Number of load instructions
system.cpu0.num_store_insts 5990651 # Number of store instructions
system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles
system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles
system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles
system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles
system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
@ -613,12 +613,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 408647 #
system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses
system.cpu0.icache.overall_misses::total 408647 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6096214000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6096214000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6096214000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6096214000 # number of overall miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses
@ -631,12 +631,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817
system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -651,12 +651,12 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647
system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses
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system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
@ -667,24 +667,24 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817
system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 330734 # number of replacements
system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use
system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use
system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits
@ -711,18 +711,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 369775 #
system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses
system.cpu0.dcache.overall_misses::total 369775 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses)
@ -747,18 +747,18 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988
system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -781,26 +781,26 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775
system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses
@ -813,20 +813,20 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@ -894,8 +894,8 @@ system.cpu1.num_fp_register_writes 2260 # nu
system.cpu1.num_mem_refs 14689113 # number of memory refs
system.cpu1.num_load_insts 8640454 # Number of load instructions
system.cpu1.num_store_insts 6048659 # Number of store instructions
system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles
system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles
system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles
system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles
system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
@ -921,12 +921,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 455583 #
system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses
system.cpu1.icache.overall_misses::total 455583 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses
@ -939,12 +939,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718
system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -959,12 +959,12 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583
system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
@ -975,24 +975,24 @@ system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718
system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 292605 # number of replacements
system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use
system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use
system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor
system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits
@ -1019,18 +1019,18 @@ system.cpu1.dcache.demand_misses::cpu1.data 321159 #
system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses
system.cpu1.dcache.overall_misses::total 321159 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses)
@ -1055,18 +1055,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529
system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1089,24 +1089,24 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159
system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses
@ -1119,18 +1119,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@ -1152,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency

1124
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
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42
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
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@ -1,12 +1,12 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.019665 # Number of seconds simulated
sim_ticks 19665440 # Number of ticks simulated
final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.006104 # Number of seconds simulated
sim_ticks 6103915 # Number of ticks simulated
final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 178903 # Simulator tick rate (ticks/s)
host_mem_usage 378856 # Number of bytes of host memory used
host_seconds 109.92 # Real time elapsed on the host
host_tick_rate 78453 # Simulator tick rate (ticks/s)
host_mem_usage 374396 # Number of bytes of host memory used
host_seconds 77.80 # Real time elapsed on the host
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu0.num_reads 99534 # number of read accesses completed
system.cpu0.num_writes 53920 # number of write accesses completed
system.cpu0.num_reads 99027 # number of read accesses completed
system.cpu0.num_writes 53493 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu1.num_reads 99604 # number of read accesses completed
system.cpu1.num_writes 53779 # number of write accesses completed
system.cpu1.num_reads 98254 # number of read accesses completed
system.cpu1.num_writes 52787 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
system.cpu2.num_reads 99103 # number of read accesses completed
system.cpu2.num_writes 53314 # number of write accesses completed
system.cpu2.num_reads 99047 # number of read accesses completed
system.cpu2.num_writes 53306 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
system.cpu3.num_reads 99223 # number of read accesses completed
system.cpu3.num_writes 53188 # number of write accesses completed
system.cpu3.num_reads 98414 # number of read accesses completed
system.cpu3.num_writes 53420 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
system.cpu4.num_reads 100000 # number of read accesses completed
system.cpu4.num_writes 53373 # number of write accesses completed
system.cpu4.num_writes 53741 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
system.cpu5.num_reads 99316 # number of read accesses completed
system.cpu5.num_writes 53693 # number of write accesses completed
system.cpu5.num_reads 98111 # number of read accesses completed
system.cpu5.num_writes 53002 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
system.cpu6.num_reads 99832 # number of read accesses completed
system.cpu6.num_writes 53341 # number of write accesses completed
system.cpu6.num_reads 99154 # number of read accesses completed
system.cpu6.num_writes 52587 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
system.cpu7.num_reads 99257 # number of read accesses completed
system.cpu7.num_writes 53656 # number of write accesses completed
system.cpu7.num_reads 99215 # number of read accesses completed
system.cpu7.num_writes 53364 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
---------- End Simulation Statistics ----------

2854
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
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