d2b57a7473
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
708 lines
80 KiB
Plaintext
708 lines
80 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.479223 # Number of seconds simulated
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sim_ticks 479223482000 # Number of ticks simulated
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final_tick 479223482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 194014 # Simulator instruction rate (inst/s)
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host_op_rate 216437 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 60195599 # Simulator tick rate (ticks/s)
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host_mem_usage 234776 # Number of bytes of host memory used
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host_seconds 7961.11 # Real time elapsed on the host
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sim_insts 1544563028 # Number of instructions simulated
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sim_ops 1723073840 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 48448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 156331072 # Number of bytes read from this memory
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system.physmem.bytes_read::total 156379520 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 48448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 48448 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 71949824 # Number of bytes written to this memory
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system.physmem.bytes_written::total 71949824 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 757 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2442673 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2443430 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1124216 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1124216 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 101097 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 326217470 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 326318567 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 101097 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 101097 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 150138352 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 150138352 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 150138352 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 101097 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 326217470 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 476456920 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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system.cpu.numCycles 958446965 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 302424004 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 248121310 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 16111337 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 166375993 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 157791713 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 18325977 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 236 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 295072409 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2170601008 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 302424004 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 176117690 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 431730569 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 85674794 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 155376778 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 133 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 285867319 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 5539236 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 950955907 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.537748 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.221191 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 519225507 54.60% 54.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 23584051 2.48% 57.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 38809935 4.08% 61.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 47901977 5.04% 66.20% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 41256448 4.34% 70.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 47147738 4.96% 75.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 39135623 4.12% 79.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 18358633 1.93% 81.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 175535995 18.46% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 950955907 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.315535 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.264706 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 327119471 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 132830999 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 402990203 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 19239879 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 68775355 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 46282380 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 697 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 2359573845 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2428 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 68775355 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 349888082 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 63823546 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 14916 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 397833782 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 70620226 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2300864153 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 28671 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 5550118 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 56484879 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2275806889 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 10620956453 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 10620952653 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 3800 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 569486951 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 5312 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 5309 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 155780896 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 627644360 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 219694213 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 87145300 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 68089448 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2199982180 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 1528 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2020409598 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 4999430 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 472571343 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1103696346 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 1357 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 950955907 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.124609 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.914480 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 272613444 28.67% 28.67% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 148967706 15.67% 44.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 160979511 16.93% 61.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 117706760 12.38% 73.64% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 124599704 13.10% 86.74% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 74507798 7.84% 94.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 38341084 4.03% 98.61% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 10540920 1.11% 99.72% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 2698980 0.28% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 950955907 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 849524 3.40% 3.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 4750 0.02% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.42% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 18987433 76.01% 79.43% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 5139841 20.57% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1236587791 61.20% 61.20% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 931138 0.05% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 12 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 588900248 29.15% 90.40% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 193990319 9.60% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2020409598 # Type of FU issued
|
|
system.cpu.iq.rate 2.108004 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 24981548 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.012365 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5021755668 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2672741554 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1961287360 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 160 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2045390937 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 63645440 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 141717590 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 292895 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 189897 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 44847167 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1141778 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 68775355 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 28059003 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1485687 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2199992043 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 5558489 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 627644360 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 219694213 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1465 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 343629 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 56102 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 189897 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 8602375 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 10226115 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 18828490 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1990642810 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 574277068 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 29766788 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 8335 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 765299887 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 238409980 # Number of branches executed
|
|
system.cpu.iew.exec_stores 191022819 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.076946 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1970153008 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1961287520 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1296694675 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2069023421 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.046318 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.626718 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 476993558 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 16110924 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 882180553 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.953199 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.727625 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 391561558 44.39% 44.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 194873977 22.09% 66.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 73868669 8.37% 74.85% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 35208101 3.99% 78.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 19136047 2.17% 81.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 30738627 3.48% 84.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19218397 2.18% 86.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 11310881 1.28% 87.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106264296 12.05% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 882180553 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563046 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 660773816 # Number of memory references committed
|
|
system.cpu.commit.loads 485926770 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462364 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 106264296 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 2975983074 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4469074827 # The number of ROB writes
|
|
system.cpu.timesIdled 802305 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 7491058 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563028 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.620530 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.620530 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.611527 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.611527 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 9971495260 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1941105565 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 174 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 178 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2911260843 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
|
|
system.cpu.icache.replacements 26 # number of replacements
|
|
system.cpu.icache.tagsinuse 632.958434 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 285866178 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 790 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 361855.921519 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 632.958434 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.309062 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.309062 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 285866178 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 285866178 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 285866178 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 285866178 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 285866178 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 285866178 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1141 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40467500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 40467500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 40467500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 40467500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 40467500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 40467500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 285867319 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 285867319 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 285867319 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 285867319 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 285867319 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 285867319 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35466.695881 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 35466.695881 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35466.695881 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 35466.695881 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35466.695881 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 35466.695881 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 790 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 790 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 790 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28839000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 28839000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28839000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 28839000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28839000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 28839000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36505.063291 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36505.063291 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 36505.063291 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 36505.063291 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 9619162 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4087.804839 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 661851236 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 9623258 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 68.776212 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 3371932000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4087.804839 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.997999 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.997999 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 494456426 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 494456426 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 167394662 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 167394662 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 86 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 86 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 661851088 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 661851088 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 661851088 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 661851088 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 10788938 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 10788938 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5191385 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5191385 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 15980323 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 15980323 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 15980323 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 15980323 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 258868265000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 258868265000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 196333546730 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 196333546730 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 455201811730 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 455201811730 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 455201811730 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 455201811730 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 505245364 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 505245364 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 89 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 89 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 677831411 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 677831411 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 677831411 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 677831411 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021354 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.021354 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030080 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.030080 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033708 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033708 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.023576 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.023576 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.023576 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.023576 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23993.859729 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 23993.859729 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37819.107373 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 37819.107373 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 28485.144620 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 28485.144620 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 2522668245 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 141500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 425263 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5932.019115 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 23583.333333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3474615 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3474615 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059553 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 3059553 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297512 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3297512 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 6357065 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 6357065 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 6357065 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 6357065 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729385 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7729385 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893873 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1893873 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9623258 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9623258 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9623258 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9623258 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124446584000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 124446584000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91535944039 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91535944039 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215982528039 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 215982528039 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215982528039 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 215982528039 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015298 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015298 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.014197 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.014197 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16100.450941 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16100.450941 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48332.672803 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48332.672803 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22443.805210 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22443.805210 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22443.805210 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22443.805210 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 2427846 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 31166.187056 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 8746719 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 2457559 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 3.559108 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 81046147000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 14021.182815 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 15.161406 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 17129.842834 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.427893 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.000463 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.522761 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.951117 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6117484 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6117516 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3474615 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3474615 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1063094 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1063094 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7180578 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7180610 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7180578 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7180610 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 758 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1611900 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1612658 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 830780 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 830780 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 758 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2442680 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 2443438 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 758 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2442680 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 2443438 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27469500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58027341500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 58054811000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 32645843411 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 32645843411 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 27469500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 90673184911 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 90700654411 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 27469500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 90673184911 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 90700654411 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 790 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7729384 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7730174 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3474615 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3474615 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893874 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1893874 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 790 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9623258 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9624048 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 790 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9623258 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9624048 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.959494 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208542 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.208619 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438667 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.438667 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.959494 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.253831 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.253889 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.959494 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.253831 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.253889 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36239.445910 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35999.343322 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35999.456177 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39295.413239 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39295.413239 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 37120.096524 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 37120.096524 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 30034731 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 3559 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8439.092723 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1124216 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1124216 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611893 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1612650 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830780 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 830780 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2442673 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 2443430 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2442673 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 2443430 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25045000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52994170500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53019215500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30019129886 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30019129886 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25045000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83013300386 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 83038345386 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25045000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83013300386 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 83038345386 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208541 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208618 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438667 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438667 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.253888 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.253888 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33084.544254 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32876.977876 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32877.075311 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36133.669426 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36133.669426 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency
|
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
|
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---------- End Simulation Statistics ----------
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