stats: updates due to changes to ticksToCycles()
This commit is contained in:
Nilay Vaish
parent
9fb93e5cd2
commit
2823982a3c
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,7 +1,9 @@
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=true
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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@ -13,15 +15,16 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/dist/m5/system/binaries/console
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console=/scratch/nilay/GEM5/system/binaries/console
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eventq_index=0
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init_param=0
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kernel=/dist/m5/system/binaries/vmlinux
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/dist/m5/system/binaries/ts_osfpal
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
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type=Bridge
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clk_domain=system.clk_domain
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delay=50000
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eventq_index=0
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ranges=8796093022208:18446744073709551615
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req_size=16
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resp_size=16
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@ -48,6 +52,7 @@ slave=system.membus.master[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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eventq_index=0
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voltage_domain=system.voltage_domain
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[system.cpu]
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@ -79,6 +84,8 @@ do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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@ -143,6 +150,7 @@ BTBTagSize=16
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RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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eventq_index=0
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globalCtrBits=2
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globalPredictorSize=8192
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instShiftAmt=2
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@ -158,6 +166,7 @@ children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -180,26 +189,31 @@ type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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size=32768
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[system.cpu.dtb]
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type=AlphaTLB
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eventq_index=0
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size=64
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
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eventq_index=0
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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children=opList
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count=6
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eventq_index=0
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opList=system.cpu.fuPool.FUList0.opList
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[system.cpu.fuPool.FUList0.opList]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=IntAlu
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opLat=1
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@ -208,16 +222,19 @@ opLat=1
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type=FUDesc
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children=opList0 opList1
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count=2
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eventq_index=0
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opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
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[system.cpu.fuPool.FUList1.opList0]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=IntMult
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opLat=3
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[system.cpu.fuPool.FUList1.opList1]
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type=OpDesc
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eventq_index=0
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issueLat=19
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opClass=IntDiv
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opLat=20
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@ -226,22 +243,26 @@ opLat=20
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type=FUDesc
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children=opList0 opList1 opList2
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count=4
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eventq_index=0
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opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
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[system.cpu.fuPool.FUList2.opList0]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatAdd
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opLat=2
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[system.cpu.fuPool.FUList2.opList1]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatCmp
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opLat=2
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[system.cpu.fuPool.FUList2.opList2]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatCvt
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opLat=2
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@ -250,22 +271,26 @@ opLat=2
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type=FUDesc
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children=opList0 opList1 opList2
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count=2
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eventq_index=0
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opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
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[system.cpu.fuPool.FUList3.opList0]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatMult
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opLat=4
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[system.cpu.fuPool.FUList3.opList1]
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type=OpDesc
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eventq_index=0
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issueLat=12
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opClass=FloatDiv
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opLat=12
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[system.cpu.fuPool.FUList3.opList2]
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type=OpDesc
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eventq_index=0
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issueLat=24
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opClass=FloatSqrt
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opLat=24
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@ -274,10 +299,12 @@ opLat=24
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type=FUDesc
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children=opList
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count=0
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eventq_index=0
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opList=system.cpu.fuPool.FUList4.opList
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[system.cpu.fuPool.FUList4.opList]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=MemRead
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opLat=1
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@ -286,124 +313,145 @@ opLat=1
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type=FUDesc
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children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
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count=4
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eventq_index=0
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opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
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[system.cpu.fuPool.FUList5.opList00]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdAdd
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opLat=1
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[system.cpu.fuPool.FUList5.opList01]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdAddAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList02]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdAlu
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opLat=1
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[system.cpu.fuPool.FUList5.opList03]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdCmp
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opLat=1
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[system.cpu.fuPool.FUList5.opList04]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdCvt
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opLat=1
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[system.cpu.fuPool.FUList5.opList05]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdMisc
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opLat=1
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[system.cpu.fuPool.FUList5.opList06]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdMult
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opLat=1
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[system.cpu.fuPool.FUList5.opList07]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdMultAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList08]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdShift
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opLat=1
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[system.cpu.fuPool.FUList5.opList09]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdShiftAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList10]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdSqrt
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opLat=1
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[system.cpu.fuPool.FUList5.opList11]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatAdd
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opLat=1
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[system.cpu.fuPool.FUList5.opList12]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatAlu
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opLat=1
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[system.cpu.fuPool.FUList5.opList13]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatCmp
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opLat=1
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[system.cpu.fuPool.FUList5.opList14]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatCvt
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opLat=1
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[system.cpu.fuPool.FUList5.opList15]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatDiv
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opLat=1
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[system.cpu.fuPool.FUList5.opList16]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatMisc
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opLat=1
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[system.cpu.fuPool.FUList5.opList17]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatMult
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opLat=1
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[system.cpu.fuPool.FUList5.opList18]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatMultAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList19]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=SimdFloatSqrt
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opLat=1
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@ -412,10 +460,12 @@ opLat=1
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type=FUDesc
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children=opList
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count=0
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eventq_index=0
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opList=system.cpu.fuPool.FUList6.opList
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[system.cpu.fuPool.FUList6.opList]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=MemWrite
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opLat=1
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@ -424,16 +474,19 @@ opLat=1
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type=FUDesc
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children=opList0 opList1
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count=4
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eventq_index=0
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opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
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[system.cpu.fuPool.FUList7.opList0]
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type=OpDesc
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eventq_index=0
|
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList7.opList1]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=MemWrite
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opLat=1
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@ -442,10 +495,12 @@ opLat=1
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type=FUDesc
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children=opList
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count=1
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eventq_index=0
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opList=system.cpu.fuPool.FUList8.opList
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[system.cpu.fuPool.FUList8.opList]
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type=OpDesc
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||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
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opLat=3
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||||
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@ -456,6 +511,7 @@ children=tags
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addr_ranges=0:18446744073709551615
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assoc=1
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clk_domain=system.cpu_clk_domain
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eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
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||||
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@ -478,17 +534,21 @@ type=LRU
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|||
assoc=1
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||||
block_size=64
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clk_domain=system.cpu_clk_domain
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||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
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||||
type=AlphaInterrupts
|
||||
eventq_index=0
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||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
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[system.cpu.itb]
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type=AlphaTLB
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||||
eventq_index=0
|
||||
size=48
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||||
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||||
[system.cpu.l2cache]
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@ -497,6 +557,7 @@ children=tags
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|||
addr_ranges=0:18446744073709551615
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||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
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@ -519,12 +580,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
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||||
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@ -534,10 +597,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
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|||
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[system.cpu.tracer]
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||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
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||||
|
||||
[system.disk0]
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||||
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@ -545,19 +610,22 @@ type=IdeDisk
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|||
children=image
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||||
delay=1000000
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||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk0.image
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||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -565,28 +633,33 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -600,6 +673,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -622,6 +696,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -629,6 +704,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -640,6 +716,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -666,6 +743,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -677,29 +755,35 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -708,6 +792,7 @@ port=3456
|
|||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
|
|
@ -716,6 +801,7 @@ type=AlphaBackdoor
|
|||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -726,6 +812,7 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -754,6 +841,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
|
|
@ -763,8 +851,40 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
|
|
@ -781,6 +901,7 @@ dma_read_delay=0
|
|||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
|
|
@ -804,6 +925,7 @@ pio=system.iobus.master[27]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -821,6 +943,7 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -838,6 +961,7 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -855,6 +979,7 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -872,6 +997,7 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -889,6 +1015,7 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -906,6 +1033,7 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -923,6 +1051,7 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -940,6 +1069,7 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -957,6 +1087,7 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -974,6 +1105,7 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -991,6 +1123,7 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -1008,6 +1141,7 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -1025,6 +1159,7 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -1042,6 +1177,7 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -1059,6 +1195,7 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -1076,6 +1213,7 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -1093,6 +1231,7 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -1110,6 +1249,7 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -1128,6 +1268,7 @@ pio=system.iobus.master[6]
|
|||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1155,6 +1296,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
|
|
@ -1164,8 +1306,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -1177,6 +1351,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
io_shift=0
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
|
|
@ -1191,6 +1366,7 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -1203,6 +1379,7 @@ pio=system.iobus.master[22]
|
|||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1213,6 +1390,7 @@ pio=system.iobus.master[1]
|
|||
type=PciConfigAll
|
||||
bus=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1223,6 +1401,7 @@ pio=system.iobus.default
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1232,5 +1411,6 @@ pio=system.iobus.master[23]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -13,15 +15,16 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/dist/m5/system/binaries/console
|
||||
console=/scratch/nilay/GEM5/system/binaries/console
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
|
@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -48,6 +52,7 @@ slave=system.membus.master[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -60,6 +65,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -93,6 +99,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -115,11 +122,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
|
|
@ -128,6 +137,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -150,21 +160,26 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -176,6 +191,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=Null
|
||||
|
|
@ -196,17 +212,21 @@ workload=
|
|||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -237,6 +257,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu2.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -299,6 +321,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -310,21 +333,25 @@ predType=tournament
|
|||
|
||||
[system.cpu2.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu2.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -333,16 +360,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu2.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu2.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -351,22 +381,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu2.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu2.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu2.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -375,22 +409,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu2.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu2.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu2.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -399,10 +437,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -411,124 +451,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -537,10 +598,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -549,16 +612,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -567,27 +633,33 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu2.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
|
|
@ -595,19 +667,22 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -615,28 +690,33 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -650,6 +730,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -672,6 +753,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -681,6 +763,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -703,6 +786,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -710,6 +794,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -721,6 +806,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -747,6 +833,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -758,29 +845,35 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -789,6 +882,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -799,6 +893,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
|
|||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
|
|
@ -807,6 +902,7 @@ type=AlphaBackdoor
|
|||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -817,6 +913,7 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -845,6 +942,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
|
|
@ -854,8 +952,40 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
|
|
@ -872,6 +1002,7 @@ dma_read_delay=0
|
|||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
|
|
@ -895,6 +1026,7 @@ pio=system.iobus.master[27]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -912,6 +1044,7 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -929,6 +1062,7 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -946,6 +1080,7 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -963,6 +1098,7 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -980,6 +1116,7 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -997,6 +1134,7 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -1014,6 +1152,7 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -1031,6 +1170,7 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -1048,6 +1188,7 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -1065,6 +1206,7 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -1082,6 +1224,7 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -1099,6 +1242,7 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -1116,6 +1260,7 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -1133,6 +1278,7 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -1150,6 +1296,7 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -1167,6 +1314,7 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -1184,6 +1332,7 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -1201,6 +1350,7 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -1219,6 +1369,7 @@ pio=system.iobus.master[6]
|
|||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1246,6 +1397,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
|
|
@ -1255,8 +1407,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -1268,6 +1452,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
io_shift=0
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
|
|
@ -1282,6 +1467,7 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -1294,6 +1480,7 @@ pio=system.iobus.master[22]
|
|||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1304,6 +1491,7 @@ pio=system.iobus.master[1]
|
|||
type=PciConfigAll
|
||||
bus=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1314,6 +1502,7 @@ pio=system.iobus.default
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1323,5 +1512,6 @@ pio=system.iobus.master[23]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -105,6 +113,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -169,6 +179,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -188,6 +199,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.checker.dtb
|
||||
eventq_index=0
|
||||
exitOnError=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -212,18 +224,21 @@ workload=
|
|||
[system.cpu.checker.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.checker.dtb.walker
|
||||
|
||||
[system.cpu.checker.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.checker.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -242,18 +257,21 @@ midr=890224640
|
|||
[system.cpu.checker.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.checker.itb.walker
|
||||
|
||||
[system.cpu.checker.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.checker.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -261,6 +279,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -283,18 +302,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -303,15 +325,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -320,16 +345,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -338,22 +366,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -362,22 +394,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -386,10 +422,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -398,124 +436,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -524,10 +583,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -536,16 +597,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -554,10 +618,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -568,6 +634,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -590,14 +657,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -616,12 +686,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -632,6 +704,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -654,12 +727,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -669,19 +744,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -694,6 +773,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -716,6 +796,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -723,6 +804,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -734,6 +816,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -760,6 +843,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -771,19 +855,23 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -793,6 +881,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -802,6 +891,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -830,6 +920,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -839,8 +930,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -852,6 +975,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -867,6 +991,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -881,6 +1007,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -890,6 +1017,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -911,8 +1039,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -921,6 +1051,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -931,6 +1062,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -941,6 +1073,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -951,6 +1084,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -965,6 +1099,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -978,6 +1113,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -995,6 +1131,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -1007,6 +1144,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -1018,6 +1156,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -1028,6 +1167,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -1040,6 +1180,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1053,6 +1194,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1063,6 +1205,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1073,6 +1216,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1083,6 +1227,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1095,6 +1240,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -1109,6 +1255,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -1121,6 +1268,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -1135,6 +1283,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1145,6 +1294,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1155,6 +1305,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1165,6 +1316,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1173,6 +1325,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -1180,11 +1333,13 @@ port=3456
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -105,6 +113,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -169,6 +179,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -184,6 +195,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -206,18 +218,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -226,15 +241,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -243,16 +261,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -261,22 +282,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -285,22 +310,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -309,10 +338,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -321,124 +352,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -447,10 +499,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -459,16 +513,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -477,10 +534,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -491,6 +550,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -513,14 +573,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -539,12 +602,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -555,6 +620,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -577,12 +643,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -592,19 +660,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -617,6 +689,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -639,6 +712,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -646,6 +720,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -657,6 +732,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -683,6 +759,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -694,19 +771,23 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -716,6 +797,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -725,6 +807,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -753,6 +836,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -762,8 +846,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -775,6 +891,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -790,6 +907,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -804,6 +923,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -813,6 +933,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -834,8 +955,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -844,6 +967,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -854,6 +978,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -864,6 +989,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -874,6 +1000,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -888,6 +1015,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -901,6 +1029,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -918,6 +1047,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -930,6 +1060,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -941,6 +1072,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -951,6 +1083,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -963,6 +1096,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -976,6 +1110,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -986,6 +1121,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -996,6 +1132,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1006,6 +1143,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1018,6 +1156,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -1032,6 +1171,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -1044,6 +1184,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -1058,6 +1199,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1068,6 +1210,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1078,6 +1221,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1088,6 +1232,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1096,6 +1241,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -1103,11 +1249,13 @@ port=3456
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -119,6 +128,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -141,18 +151,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -163,6 +176,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -185,14 +199,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -211,18 +228,21 @@ midr=890224640
|
|||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -234,6 +254,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=Null
|
||||
|
|
@ -255,17 +276,20 @@ workload=
|
|||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -284,17 +308,20 @@ midr=890224640
|
|||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -325,6 +352,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu2.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -387,6 +416,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -399,12 +429,14 @@ predType=tournament
|
|||
[system.cpu2.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu2.dtb.walker
|
||||
|
||||
[system.cpu2.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
|
|
@ -412,15 +444,18 @@ sys=system
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -429,16 +464,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu2.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu2.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -447,22 +485,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu2.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu2.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu2.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -471,22 +513,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu2.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu2.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu2.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -495,10 +541,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -507,124 +555,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -633,10 +702,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -645,16 +716,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -663,16 +737,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu2.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu2.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -691,30 +768,36 @@ midr=890224640
|
|||
[system.cpu2.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu2.itb.walker
|
||||
|
||||
[system.cpu2.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -727,6 +810,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -749,6 +833,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -758,6 +843,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -780,6 +866,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -787,6 +874,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -798,6 +886,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -824,6 +913,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -835,19 +925,23 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -857,6 +951,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -866,6 +961,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -894,6 +990,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -903,8 +1000,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -916,6 +1045,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -931,6 +1061,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -945,6 +1077,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -954,6 +1087,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -975,8 +1109,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -985,6 +1121,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -995,6 +1132,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -1005,6 +1143,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -1015,6 +1154,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -1029,6 +1169,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -1042,6 +1183,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -1059,6 +1201,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -1071,6 +1214,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -1082,6 +1226,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -1092,6 +1237,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -1104,6 +1250,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1117,6 +1264,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1127,6 +1275,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1137,6 +1286,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1147,6 +1297,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1159,6 +1310,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -1173,6 +1325,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -1185,6 +1338,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -1199,6 +1353,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1209,6 +1364,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1219,6 +1375,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1229,6 +1386,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1237,6 +1395,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -1245,6 +1404,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -1254,11 +1414,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
|
|
@ -112,6 +121,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -134,18 +144,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -156,6 +169,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -178,14 +192,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -204,18 +221,21 @@ midr=890224640
|
|||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -227,6 +247,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=Null
|
||||
|
|
@ -248,17 +269,20 @@ workload=
|
|||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -277,30 +301,36 @@ midr=890224640
|
|||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -313,6 +343,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -335,6 +366,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -344,6 +376,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -366,6 +399,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -373,6 +407,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -384,6 +419,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -410,6 +446,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -421,19 +458,23 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -443,6 +484,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -452,6 +494,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -480,6 +523,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -489,8 +533,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -502,6 +578,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -517,6 +594,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -531,6 +610,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -540,6 +620,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -561,8 +642,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -571,6 +654,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -581,6 +665,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -591,6 +676,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -601,6 +687,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -615,6 +702,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -628,6 +716,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -645,6 +734,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -657,6 +747,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -668,6 +759,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -678,6 +770,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -690,6 +783,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -703,6 +797,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -713,6 +808,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -723,6 +819,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -733,6 +830,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -745,6 +843,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -759,6 +858,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -771,6 +871,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -785,6 +886,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -795,6 +897,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -805,6 +908,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -815,6 +919,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -823,6 +928,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -831,6 +937,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -840,11 +947,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,9 +625,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
|
|
@ -133,6 +140,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -148,6 +156,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -170,18 +179,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -207,16 +222,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -225,22 +243,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -249,22 +271,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -273,10 +299,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -285,124 +313,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -411,10 +460,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -423,16 +474,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -441,10 +495,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -455,6 +511,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -477,12 +534,14 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -493,16 +552,19 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -513,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -535,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -559,9 +625,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -573,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -597,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -608,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.065614 # Nu
|
|||
sim_ticks 65613727000 # Number of ticks simulated
|
||||
final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 90206 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 158838 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37463203 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 416624 # Number of bytes of host memory used
|
||||
host_seconds 1751.42 # Real time elapsed on the host
|
||||
host_inst_rate 72100 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 126957 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29943715 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 436724 # Number of bytes of host memory used
|
||||
host_seconds 2191.24 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory
|
||||
|
|
@ -296,9 +296,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440
|
|||
system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1957440 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 33859770 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted
|
||||
|
|
@ -373,24 +373,24 @@ system.cpu.memDep0.insertedLoads 101555761 # Nu
|
|||
system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -427,12 +427,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued
|
||||
|
|
@ -461,27 +461,27 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued
|
||||
system.cpu.iq.rate 2.288206 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
|
|
@ -491,35 +491,35 @@ system.cpu.iew.iewIdleCycles 0 # Nu
|
|||
system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations
|
||||
system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 30820824 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 32925944 # Number of stores executed
|
||||
system.cpu.iew.exec_stores 32925943 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.277516 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 218260008 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value
|
||||
system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 218260006 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle
|
||||
|
|
@ -551,8 +551,8 @@ system.cpu.commit.int_insts 278169481 # Nu
|
|||
system.cpu.commit.function_calls 4237596 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 415950983 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 627545403 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 415950981 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 627545399 # The number of ROB writes
|
||||
system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
|
||||
|
|
@ -562,13 +562,13 @@ system.cpu.cpi 0.830614 # CP
|
|||
system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 483744134 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 234595253 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 483744129 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 234595251 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 141 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 77 # number of floating regfile writes
|
||||
system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution
|
||||
|
|
@ -611,12 +611,12 @@ system.cpu.icache.demand_misses::cpu.inst 1305 # n
|
|||
system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1305 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses
|
||||
|
|
@ -629,12 +629,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051
|
|||
system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -655,24 +655,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1011
|
|||
system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 479 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use
|
||||
|
|
@ -711,17 +711,17 @@ system.cpu.l2cache.demand_misses::total 30419 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30419 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -746,17 +746,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014641 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -814,21 +814,21 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586
|
|||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2072514 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 71413624 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 71413623 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses
|
||||
|
|
@ -845,14 +845,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 34178695748
|
|||
system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,9 +625,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
|
|
@ -133,6 +140,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -148,6 +156,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -170,18 +179,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -207,16 +222,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -225,22 +243,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -249,22 +271,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -273,10 +299,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -285,124 +313,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -411,10 +460,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -423,16 +474,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -441,10 +495,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -455,6 +511,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -477,12 +534,14 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -493,16 +552,19 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -513,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -535,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -559,9 +625,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -573,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -597,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -608,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,17 +518,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -482,6 +541,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -504,12 +564,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -528,7 +591,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -542,11 +606,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -566,6 +632,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -577,17 +644,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.077516 # Nu
|
|||
sim_ticks 77516381000 # Number of ticks simulated
|
||||
final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 185827 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 185827 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38353496 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262456 # Number of bytes of host memory used
|
||||
host_seconds 2021.10 # Real time elapsed on the host
|
||||
host_inst_rate 154118 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154118 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31808931 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282024 # Number of bytes of host memory used
|
||||
host_seconds 2436.94 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory
|
||||
|
|
@ -210,14 +210,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% #
|
|||
system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 59913750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 59914250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 102712500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -248,15 +248,15 @@ system.membus.data_through_bus 476608 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 50307165 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 50307155 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -295,23 +295,23 @@ system.cpu.workload.num_syscalls 215 # Nu
|
|||
system.cpu.numCycles 155032764 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -319,24 +319,24 @@ system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Nu
|
|||
system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode
|
||||
system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle
|
||||
system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running
|
||||
|
|
@ -360,28 +360,28 @@ system.cpu.memDep0.conflictingLoads 8938676 # Nu
|
|||
system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
|
||||
|
|
@ -412,12 +412,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued
|
||||
|
|
@ -446,21 +446,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued
|
||||
system.cpu.iq.rate 2.592749 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -473,11 +473,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions
|
||||
|
|
@ -489,17 +489,17 @@ system.cpu.iew.predictedNotTakenIncorrect 408580 # N
|
|||
system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 24803859 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 46575028 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 78467483 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.569736 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 193564450 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value
|
||||
system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 193564452 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back
|
||||
|
|
@ -507,13 +507,13 @@ system.cpu.iew.wb_penalized_rate 0 # fr
|
|||
system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle
|
||||
|
|
@ -523,7 +523,7 @@ system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -536,10 +536,10 @@ system.cpu.commit.int_insts 316365839 # Nu
|
|||
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 557859409 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 557859413 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 871404727 # The number of ROB writes
|
||||
system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
|
||||
|
|
@ -548,7 +548,7 @@ system.cpu.cpi_total 0.412788 # CP
|
|||
system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 398219851 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 170183529 # number of integer regfile writes
|
||||
system.cpu.int_regfile_writes 170183531 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
||||
|
|
@ -575,31 +575,31 @@ system.cpu.toL2Bus.respLayer1.occupancy 6675000 # La
|
|||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 2141 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 50291613 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5620 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 50291612 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5621 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 330634250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 330634250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 330634250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses
|
||||
|
|
@ -612,12 +612,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000112
|
|||
system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.250667 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58821.250667 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58821.250667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58821.250667 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
|
|
@ -626,36 +626,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1552 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1552 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1552 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1552 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1552 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1552 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.485377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use
|
||||
|
|
@ -694,17 +694,17 @@ system.cpu.l2cache.demand_misses::total 7447 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7447 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238916500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238915500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 66414500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 305331000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 305330000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 225828500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 225828500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 238916500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 238915500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 292243000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 531159500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 238916500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 531158500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 238915500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 292243000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 531159500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 531158500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -729,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902557 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849349 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.954328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.902557 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.931713 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.642361 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.588603 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.356961 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71325.298778 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71325.164496 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71325.298778 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71325.164496 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,7 +625,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,17 +518,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -482,6 +541,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -504,12 +564,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -528,7 +591,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -542,11 +606,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -566,6 +632,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -577,17 +644,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.631518 # Nu
|
|||
sim_ticks 631518097500 # Number of ticks simulated
|
||||
final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 141288 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 141288 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48943367 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266484 # Number of bytes of host memory used
|
||||
host_seconds 12903.04 # Real time elapsed on the host
|
||||
host_inst_rate 116160 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 116160 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 40238771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286040 # Number of bytes of host memory used
|
||||
host_seconds 15694.27 # Real time elapsed on the host
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_ops 1823043370 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory
|
||||
|
|
@ -273,8 +273,8 @@ system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # By
|
|||
system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2888041500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 14116019000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 2888040000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 14116017500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst
|
||||
|
|
@ -310,9 +310,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34753664 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1230653000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1230652000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4488013000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 388926557 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted
|
||||
|
|
@ -339,10 +339,10 @@ system.cpu.dtb.data_hits 805300436 # DT
|
|||
system.cpu.dtb.data_misses 641311 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 805941747 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 394923337 # ITB hits
|
||||
system.cpu.itb.fetch_hits 394923336 # ITB hits
|
||||
system.cpu.itb.fetch_misses 673 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 394924010 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 394924009 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -359,62 +359,62 @@ system.cpu.workload.num_syscalls 39 # Nu
|
|||
system.cpu.numCycles 1263036196 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 410109211 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 3275361916 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 410109214 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 3275361918 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 157942219 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 157942220 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 394923337 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 11250821 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1248398015 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 394923336 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 11250823 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1248398019 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 618119320 49.51% 49.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 618119324 49.51% 49.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 41223037 3.30% 80.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 41223036 3.30% 80.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 233409830 18.70% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 233409831 18.70% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1248398015 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1248398019 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 438388188 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 62722157 # Number of cycles decode is blocked
|
||||
system.cpu.decode.IdleCycles 438388192 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 62722156 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 131631452 # Number of cycles decode is squashing
|
||||
system.cpu.decode.SquashCycles 131631453 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 131631452 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 467678490 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 27888697 # Number of cycles rename is blocking
|
||||
system.cpu.rename.SquashCycles 131631453 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 467678494 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 27888696 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 3095577928 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 3095577926 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 2054701915 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 3579840201 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 3494452831 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 2054701913 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 3579840200 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 3494452830 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 669732845 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 669732843 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer
|
||||
|
|
@ -422,30 +422,30 @@ system.cpu.memDep0.insertedLoads 743928173 # Nu
|
|||
system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2623617017 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 2623617019 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 2160251370 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 2160251371 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 800506396 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsExamined 800506398 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1248398015 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 1248398019 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 451794383 36.19% 36.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 196881070 15.77% 51.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 451794387 36.19% 36.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 196881068 15.77% 51.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 120660417 9.67% 81.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 104720930 8.39% 90.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 79314006 6.35% 96.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 120660419 9.67% 81.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 104720933 8.39% 90.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 79314003 6.35% 96.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1248398015 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1248398019 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available
|
||||
|
|
@ -481,7 +481,7 @@ system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1234386708 57.14% 57.14% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1234386709 57.14% 57.14% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued
|
||||
|
|
@ -514,17 +514,17 @@ system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Ty
|
|||
system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 2160251370 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 2160251371 # Type of FU issued
|
||||
system.cpu.iq.rate 1.710364 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 5472576315 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3336085104 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1990052080 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5472576321 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3336085108 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1990052081 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 2119632114 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 2119632115 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -537,11 +537,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 131631452 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 131631453 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2987064962 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 734569 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispatchedInsts 2987064964 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 734565 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions
|
||||
|
|
@ -553,31 +553,31 @@ system.cpu.iew.predictedNotTakenIncorrect 30372 # N
|
|||
system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 94121182 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 94121183 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 363447857 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 277625839 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 283075035 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.635844 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 2066015512 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 2063661876 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1180966909 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1753315236 # num instructions consuming a value
|
||||
system.cpu.iew.wb_sent 2066015513 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 2063661877 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1180966911 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1753315239 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 961121272 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 961121274 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1116766563 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 1116766566 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 497624739 44.56% 44.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 228755329 20.48% 65.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 119853189 10.73% 75.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 497624741 44.56% 44.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 228755331 20.48% 65.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 119853188 10.73% 75.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle
|
||||
|
|
@ -587,7 +587,7 @@ system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1116766563 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1116766566 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -600,10 +600,10 @@ system.cpu.commit.int_insts 1778941351 # Nu
|
|||
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3980018807 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 6071851296 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 3980018812 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 6071851301 # The number of ROB writes
|
||||
system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 14638181 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 14638177 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
||||
|
|
@ -612,7 +612,7 @@ system.cpu.cpi_total 0.692817 # CP
|
|||
system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1496658984 # number of integer regfile writes
|
||||
system.cpu.int_regfile_writes 1496658985 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
|
|
@ -639,54 +639,54 @@ system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # La
|
|||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 8311 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 394910394 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 394910393 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 39396.487829 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 39396.487729 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 394910394 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 394910394 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 394910394 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 394910394 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 394910394 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 394910394 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 394910393 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 394910393 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 394910393 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12943 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 383675499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 383675499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 383675499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 383675499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 383675499 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 383675499 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 394923337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 394923337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 394923337 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 394923337 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 394923337 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 394923337 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 383664999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 383664999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 383664999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 383664999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 383664999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 383664999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 394923336 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 394923336 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 394923336 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 394923336 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 394923336 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 394923336 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29643.475160 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 29643.475160 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 29643.475160 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 29643.475160 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29642.663911 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 29642.663911 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 29642.663911 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 29642.663911 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 707 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 54.307692 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 54.384615 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -702,24 +702,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10025
|
|||
system.cpu.icache.demand_mshr_misses::total 10025 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10025 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10025 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281680749 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281680749 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281680749 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281680749 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281680749 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281680749 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281678249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281678249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281678249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281678249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281678249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281678249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.830324 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.830324 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.580948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.580948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 443340 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use
|
||||
|
|
@ -758,17 +758,17 @@ system.cpu.l2cache.demand_misses::total 476119 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2752 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 473367 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 476119 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198914750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198912250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29323124000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29522038750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29522036250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5227072250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5227072250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 198914750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 198912250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 34550196250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34749111000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 198914750 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34749108500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 198912250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 34550196250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34749111000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34749108500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10025 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460252 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1470277 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.308784 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274514 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.309008 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.308784 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72280.069041 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72279.160610 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.110212 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.104103 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72984.088012 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72984.082761 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72984.088012 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72984.082761 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -825,17 +825,17 @@ system.cpu.l2cache.demand_mshr_misses::total 476119
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 473367 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 476119 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164199250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164196250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24183867000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348066250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348063250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4422430250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4422430250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164199250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164196250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28606297250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 28770496500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164199250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 28770493500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164196250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28606297250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 28770496500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 28770493500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278360 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -847,17 +847,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.308784
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.308784 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59665.425145 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59664.335029 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.032688 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.025358 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1527796 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use
|
||||
|
|
@ -888,10 +888,10 @@ system.cpu.dcache.demand_misses::cpu.data 2987711 # n
|
|||
system.cpu.dcache.demand_misses::total 2987711 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2987711 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2987711 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391156750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 77391156750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191877602 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 46191877602 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391157750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 77391157750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191876602 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 46191876602 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles
|
||||
|
|
@ -918,10 +918,10 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004453
|
|||
system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.415618 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.415618 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.019744 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.019744 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,7 +625,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -56,6 +60,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBuffSize=4
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -90,6 +95,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -105,6 +111,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -127,11 +134,13 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
|
|
@ -140,6 +149,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -162,17 +172,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -181,6 +195,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -203,12 +218,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -227,7 +245,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -241,11 +260,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -265,6 +286,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -276,17 +298,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.043690 # Nu
|
|||
sim_ticks 43690025000 # Number of ticks simulated
|
||||
final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 111109 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 111109 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 54950396 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264576 # Number of bytes of host memory used
|
||||
host_seconds 795.08 # Real time elapsed on the host
|
||||
host_inst_rate 91247 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 91247 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45127446 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 283120 # Number of bytes of host memory used
|
||||
host_seconds 968.15 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
|
||||
|
|
@ -327,9 +327,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17888768 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1218630500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1521664000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 18742723 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted
|
||||
|
|
@ -395,7 +395,7 @@ system.cpu.execution_unit.executions 44777932 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 77196543 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed
|
||||
|
|
@ -577,14 +577,14 @@ system.cpu.l2cache.overall_misses::total 165515 # nu
|
|||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 13452980750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 13452980250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15496302750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 16046428500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15496302250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 16046428000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15496302750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 16046428500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15496302250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 16046428000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -612,14 +612,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.569244 #
|
|||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.814042 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.814042 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 96948.485032 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 96948.485032 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -700,14 +700,14 @@ system.cpu.dcache.demand_misses::cpu.data 1135132 # n
|
|||
system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135132 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666734 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5098666734 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765880 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 85921765880 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 91020432614 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 91020432614 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 91020432614 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 91020432614 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -724,14 +724,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032535
|
|||
system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.377950 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.377950 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634839 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634839 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 80184.888290 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 80184.888290 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked
|
||||
|
|
@ -760,12 +760,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204346
|
|||
system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723509265 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723509265 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161452281 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16161452281 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161452281 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 16161452281 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -776,12 +776,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.925373 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.925373 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,17 +518,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -482,6 +541,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -504,12 +564,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -528,7 +591,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -542,11 +606,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -566,6 +632,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -577,17 +644,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,7 +625,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -56,6 +60,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBuffSize=4
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -90,6 +95,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -105,6 +111,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -127,11 +134,13 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
|
|
@ -140,6 +149,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -162,17 +172,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -181,6 +195,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -203,12 +218,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -227,7 +245,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -241,11 +260,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -265,6 +286,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -276,17 +298,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.009838 # Nu
|
|||
sim_ticks 1009838214500 # Number of ticks simulated
|
||||
final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 108402 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 108402 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 60154913 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 256492 # Number of bytes of host memory used
|
||||
host_seconds 16787.29 # Real time elapsed on the host
|
||||
host_inst_rate 87394 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 87394 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48496748 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275936 # Number of bytes of host memory used
|
||||
host_seconds 20822.81 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
|
|
@ -95,10 +95,10 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 1018055 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 1662262 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 204907 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 70584 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 21383 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 1662258 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 204908 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 70586 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 21384 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -128,27 +128,27 @@ system.physmem.rdQLenPdf::29 0 # Wh
|
|||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 45757 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 45743 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 45700 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 45756 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 45744 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 45699 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 45684 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 45673 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 45686 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 45671 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 45794 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 45985 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 45793 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 45986 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 46504 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 47344 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 47566 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 46502 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 47345 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 47567 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 47072 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 47073 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see
|
||||
|
|
@ -159,19 +159,19 @@ system.physmem.wrQLenPdf::28 1 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1862401 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 102.289945 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 79.389421 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 186.671108 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 1500565 80.57% 80.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 201454 10.82% 91.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 59784 3.21% 94.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 29274 1.57% 96.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 16603 0.89% 97.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 10401 0.56% 97.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 7224 0.39% 98.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 6892 0.37% 98.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 4048 0.22% 98.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::samples 1862398 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 102.290110 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 79.389553 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 186.671437 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 1500560 80.57% 80.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 201450 10.82% 91.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 59792 3.21% 94.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 29273 1.57% 96.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 16605 0.89% 97.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 10399 0.56% 97.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 7221 0.39% 98.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 6896 0.37% 98.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 4046 0.22% 98.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation
|
||||
|
|
@ -180,10 +180,10 @@ system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # By
|
|||
system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 1308 0.07% 99.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 968 0.05% 99.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 1341 0.07% 99.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 595 0.03% 99.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 1307 0.07% 99.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 969 0.05% 99.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 1340 0.07% 99.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 596 0.03% 99.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation
|
||||
|
|
@ -283,15 +283,15 @@ system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% #
|
|||
system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1862401 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 23049370500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 84969994250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::total 1862398 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 23048924250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 84969451750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 52124943750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 11765.07 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 26606.09 # Average bank access latency per DRAM burst
|
||||
system.physmem.totBankLat 52124847500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 11764.84 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 26606.04 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 43371.16 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 43370.88 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -302,8 +302,8 @@ system.physmem.busUtilRead 0.97 # Da
|
|||
system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 771404 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 343365 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHits 771409 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 343363 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 339128.71 # Average gap between requests
|
||||
|
|
@ -321,39 +321,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1
|
|||
system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575552 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11787413500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 11785228500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 18365913000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 326538195 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252572806 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 326538257 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 220428693 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135446272 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 220428800 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135446379 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 61.446752 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 61.446771 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444831815 # DTB read hits
|
||||
system.cpu.dtb.read_hits 444831817 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449728893 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 449728895 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160846718 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162548022 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605678533 # DTB hits
|
||||
system.cpu.dtb.data_hits 605678535 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 612276915 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 231928866 # ITB hits
|
||||
system.cpu.dtb.data_accesses 612276917 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 231928870 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 231928888 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 231928892 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -370,8 +370,8 @@ system.cpu.workload.num_syscalls 29 # Nu
|
|||
system.cpu.numCycles 2019676430 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 172263192 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154275003 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.branch_predictor.predictedTaken 172263299 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154274958 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File
|
||||
|
|
@ -389,12 +389,12 @@ system.cpu.execution_unit.executions 1139356886 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 1742059065 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 1742060649 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7515569 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 447943127 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571733303 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 77.821045 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7515544 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 447943086 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571733344 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 77.821047 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 444595663 # Number of Load instructions committed
|
||||
system.cpu.comStores 160728502 # Number of Store instructions committed
|
||||
system.cpu.comBranches 214632552 # Number of Branches instructions committed
|
||||
|
|
@ -412,66 +412,66 @@ system.cpu.cpi_total 1.109846 # CP
|
|||
system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 833031471 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186644959 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 58.754211 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1085876245 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933800185 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.235138 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1047285366 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972391064 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.idleCycles 833031386 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186645044 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 58.754216 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1085876271 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933800159 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.235137 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1047285367 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972391063 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1610051905 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409624525 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.idleCycles 1610051904 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409624526 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 998329603 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021346827 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.idleCycles 998329594 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021346836 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 231927727 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 231927731 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269997.353900 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269997.358556 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 231927727 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 231927727 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 231927727 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 231927727 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 231927727 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 231927727 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 231927731 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 231927731 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 231927731 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1139 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 82717000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 82717000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 82717000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 82717000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 82717000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 82717000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 231928866 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 231928866 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 231928866 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 231928866 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 231928866 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 231928866 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 82716500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 82716500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 82716500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 82716500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 82716500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 82716500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 231928870 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 231928870 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 231928870 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 231928870 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 231928870 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 231928870 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.475856 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 72622.475856 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 72622.475856 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 72622.475856 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 72622.036874 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 72622.036874 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -492,24 +492,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859
|
|||
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 65136750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 65136750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 65136750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 65136250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 65136250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 65136250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75828.579744 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75828.579744 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution
|
||||
|
|
@ -529,17 +529,17 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # La
|
|||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13991720500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13991718500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 1926957 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30919.698652 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30919.698369 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14931.952178 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086514 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy
|
||||
|
|
@ -565,17 +565,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98167461500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 98231735250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71142206750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 71142206750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 64273750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 169309668250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 169373942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 64273750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 169309668250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 169373942000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98166669000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 98230942250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71141350250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 71141350250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 64273250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 169308019250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 169372292500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 64273250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 169308019250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 169372292500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -600,17 +600,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215060 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.923166 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83367.057654 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.830055 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91056.663224 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91056.663224 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 86429.034622 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 86429.034622 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.341094 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83366.384636 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.157104 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91055.566968 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91055.566968 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 86428.192906 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 86428.192906 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -632,17 +632,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53492750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83392423000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445915750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355655750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355655750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53492750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144748078750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 144801571500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53492750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144748078750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 144801571500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53491750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83391618000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445109750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355946750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355946750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53491750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144747564750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 144801056500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53491750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144747564750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 144801056500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -654,21 +654,21 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62273.282887 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70819.605905 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70813.375982 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.615477 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.615477 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62272.118743 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70818.922272 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70812.691999 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.987935 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.987935 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9107351 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 593283203 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 593283202 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit.
|
||||
|
|
@ -677,28 +677,28 @@ system.cpu.dcache.tags.occ_percent::cpu.data 0.996669
|
|||
system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156014426 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156014426 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593283203 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593283203 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593283203 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593283203 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156014425 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593283202 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593283202 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593283202 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593283202 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4714076 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4714076 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 12040962 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 12040962 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 12040962 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 12040962 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066802000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 183066802000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 258282974250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 258282974250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 441349776250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 441349776250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 441349776250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 441349776250 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4714077 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4714077 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 12040963 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 12040963 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 12040963 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 12040963 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 183066004000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 258278135000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 441344139000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 441344139000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 441344139000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 441344139000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -715,19 +715,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.019892
|
|||
system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.621723 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.621723 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54789.734881 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54789.734881 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 36654.029491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 36654.029491 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 12098438 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 36653.558274 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 36653.558274 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 12098433 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 422645 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 422647 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625532 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625385 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -735,12 +735,12 @@ system.cpu.dcache.writebacks::writebacks 3693280 # nu
|
|||
system.cpu.dcache.writebacks::total 3693280 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824895 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2824895 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2929515 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2929515 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2929515 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2929515 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824896 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2824896 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2929516 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2929516 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2929516 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2929516 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses
|
||||
|
|
@ -749,14 +749,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111447
|
|||
system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165960748500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 165960748500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84277565500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84277565500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250238314000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 250238314000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250238314000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 250238314000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84276720000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84276720000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 250236677500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 250236677500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -765,14 +765,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22979.041273 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22979.041273 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.635773 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.635773 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,17 +518,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -482,6 +541,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -504,12 +564,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -528,7 +591,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -542,11 +606,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -566,6 +632,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -577,17 +644,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,7 +625,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -56,6 +60,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBuffSize=4
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -90,6 +95,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -105,6 +111,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -127,11 +134,13 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
|
|
@ -140,6 +149,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -162,17 +172,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -181,6 +195,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -203,12 +218,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -227,7 +245,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -241,11 +260,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -265,6 +286,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -276,17 +298,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.041680 # Nu
|
|||
sim_ticks 41680207000 # Number of ticks simulated
|
||||
final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 118687 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 118687 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53827332 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260144 # Number of bytes of host memory used
|
||||
host_seconds 774.33 # Real time elapsed on the host
|
||||
host_inst_rate 93645 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93645 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42470141 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279708 # Number of bytes of host memory used
|
||||
host_seconds 981.40 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -203,14 +203,14 @@ system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% #
|
|||
system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 34068750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 34070750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 67663750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -239,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 13412627 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
|
||||
|
|
@ -310,9 +310,9 @@ system.cpu.contextSwitches 1 # Nu
|
|||
system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.699835 # Percentage of cycles cpu is active
|
||||
system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.699836 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -342,9 +342,9 @@ system.cpu.stage2.utilization 59.802183 # Pe
|
|||
system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
||||
|
|
@ -366,12 +366,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n
|
|||
system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11399 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses
|
||||
|
|
@ -384,12 +384,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145
|
|||
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -410,24 +410,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520
|
|||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
|
||||
|
|
@ -486,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -521,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -554,14 +554,14 @@ system.cpu.l2cache.overall_mshr_misses::total 4938
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -576,22 +576,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits
|
||||
|
|
@ -610,14 +610,14 @@ system.cpu.dcache.demand_misses::cpu.data 8851 # n
|
|||
system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8851 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -634,19 +634,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -670,12 +670,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -686,12 +686,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,17 +518,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -482,6 +541,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -504,12 +564,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -528,7 +591,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -542,11 +606,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -566,6 +632,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -577,17 +644,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.023462 # Nu
|
|||
sim_ticks 23461709500 # Number of ticks simulated
|
||||
final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 165875 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 165875 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46230980 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261164 # Number of bytes of host memory used
|
||||
host_seconds 507.49 # Real time elapsed on the host
|
||||
host_inst_rate 127245 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 127245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35464472 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280732 # Number of bytes of host memory used
|
||||
host_seconds 661.56 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
|
||||
|
|
@ -204,14 +204,14 @@ system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% #
|
|||
system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 37518250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 37518750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 70743750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -240,17 +240,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 334592 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 14847721 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -289,93 +289,93 @@ system.cpu.workload.num_syscalls 389 # Nu
|
|||
system.cpu.numCycles 46923420 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running
|
||||
system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing
|
||||
system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode
|
||||
system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle
|
||||
system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 749 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available
|
||||
|
|
@ -411,7 +411,7 @@ system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued
|
||||
|
|
@ -444,36 +444,36 @@ system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Ty
|
|||
system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued
|
||||
system.cpu.iq.rate 2.057929 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall
|
||||
|
|
@ -483,41 +483,41 @@ system.cpu.iew.predictedNotTakenIncorrect 494157 # N
|
|||
system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 10234972 # number of nop insts executed
|
||||
system.cpu.iew.exec_nop 10234970 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 12022158 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 7069522 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.031772 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 64474348 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 64474346 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -528,12 +528,12 @@ system.cpu.commit.branches 10240685 # Nu
|
|||
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 153322231 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 234879486 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 153322226 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 234879469 # The number of ROB writes
|
||||
system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
||||
|
|
@ -542,7 +542,7 @@ system.cpu.cpi_total 0.557420 # CP
|
|||
system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 129048096 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 70519804 # number of integer regfile writes
|
||||
system.cpu.int_regfile_writes 70519803 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 714547 # number of misc regfile reads
|
||||
|
|
@ -568,32 +568,32 @@ system.cpu.toL2Bus.respLayer0.utilization 0.1 # L
|
|||
system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 9576 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 14719875 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14285 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 413142250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 413142250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 413142250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 413142250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 413142250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 14719872 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14288 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 413271500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses
|
||||
|
|
@ -606,12 +606,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000970
|
|||
system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28921.403570 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28921.403570 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28921.403570 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28921.403570 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28924.377100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28924.377100 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked
|
||||
|
|
@ -620,45 +620,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2775 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 2775 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 2775 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 2775 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2775 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2775 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2778 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 2778 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 2778 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 2778 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2778 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2778 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303669750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 303669750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303669750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 303669750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303669750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 303669750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303668250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 303668250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303668250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 303668250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303668250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 303668250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26383.123371 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26383.123371 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2409.583503 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2409.583505 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447961 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447963 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy
|
||||
|
|
@ -688,17 +688,17 @@ system.cpu.l2cache.demand_misses::total 5228 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5228 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207669750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34561250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 242231000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124309250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 124309250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 207669750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 158870500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 366540250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 207669750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 158870500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 366540250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207668250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34560750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 242229000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124310250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 124310250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 207668250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 158871000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 366539250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 207668250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 158871000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 366539250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -723,17 +723,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380025 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.603527 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74970.173536 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68757.025263 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.651026 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.651026 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70110.988906 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70110.988906 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -753,17 +753,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168835250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103389750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103389750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168835250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 301083250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168835250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132248000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 301083250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -775,25 +775,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.879817 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56115.100766 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.149560 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.149560 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 159 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152637 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits
|
||||
|
|
@ -816,16 +816,16 @@ system.cpu.dcache.demand_misses::cpu.data 9208 # n
|
|||
system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9208 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 58289750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 505815795 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 505815795 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 564105545 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 564105545 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 564105545 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 564105545 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -846,16 +846,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000328
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked
|
||||
|
|
@ -884,16 +884,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246
|
|||
system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126440497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 126440497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -904,16 +904,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,18 +173,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -202,16 +216,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -220,22 +237,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -244,22 +265,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -268,10 +293,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -280,124 +307,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -406,10 +454,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -418,16 +468,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -436,10 +489,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -450,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -472,14 +528,17 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -498,12 +557,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -514,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -536,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -560,7 +625,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -574,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -609,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.074220 # Nu
|
|||
sim_ticks 74219948500 # Number of ticks simulated
|
||||
final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 110839 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 121359 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 47744278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278976 # Number of bytes of host memory used
|
||||
host_seconds 1554.53 # Real time elapsed on the host
|
||||
host_inst_rate 84730 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 92772 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36497737 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298520 # Number of bytes of host memory used
|
||||
host_seconds 2033.55 # Real time elapsed on the host
|
||||
sim_insts 172303021 # Number of instructions simulated
|
||||
sim_ops 188656503 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory
|
||||
|
|
@ -197,14 +197,14 @@ system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% #
|
|||
system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 25205500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 25203500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 56540000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -233,18 +233,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 242752 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 94784279 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 94784274 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
|
|
@ -292,95 +292,95 @@ system.cpu.workload.num_syscalls 400 # Nu
|
|||
system.cpu.numCycles 148439898 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched
|
||||
system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running
|
||||
system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch
|
||||
system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle
|
||||
system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename
|
||||
system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups
|
||||
system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available
|
||||
|
|
@ -416,7 +416,7 @@ system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
|
||||
|
|
@ -449,21 +449,21 @@ system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Ty
|
|||
system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued
|
||||
system.cpu.iq.rate 1.680523 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed
|
||||
|
|
@ -472,12 +472,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall
|
||||
|
|
@ -488,7 +488,7 @@ system.cpu.iew.predictedNotTakenIncorrect 3760086 # N
|
|||
system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 17196 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed
|
||||
|
|
@ -497,23 +497,23 @@ system.cpu.iew.exec_stores 13648456 # Nu
|
|||
system.cpu.iew.exec_rate 1.636760 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 148474079 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 148474078 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle
|
||||
|
|
@ -522,7 +522,7 @@ system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -535,10 +535,10 @@ system.cpu.commit.int_insts 150106217 # Nu
|
|||
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 448787441 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 679451137 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 448787434 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 679451113 # The number of ROB writes
|
||||
system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated
|
||||
|
|
@ -574,49 +574,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3047739 # La
|
|||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 2394 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 36845555 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 36845557 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5337 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
|
||||
|
|
@ -637,33 +637,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4126
|
|||
system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy
|
||||
|
|
@ -693,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 3809 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3809 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -728,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.637170 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -767,17 +767,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3794
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -789,17 +789,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 57 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use
|
||||
|
|
@ -832,16 +832,16 @@ system.cpu.dcache.demand_misses::cpu.data 9625 # n
|
|||
system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9625 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -864,16 +864,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
||||
|
|
@ -902,14 +902,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1852
|
|||
system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -918,14 +918,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
|
|
@ -133,6 +140,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -148,6 +156,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -170,18 +179,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -207,16 +222,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -225,22 +243,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -249,22 +271,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -273,10 +299,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -285,124 +313,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -411,10 +460,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -423,16 +474,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -441,10 +495,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -455,6 +511,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -477,12 +534,14 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -493,16 +552,19 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -513,6 +575,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -535,12 +598,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -559,7 +625,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -573,11 +640,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -597,6 +666,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -608,17 +678,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.144463 # Nu
|
|||
sim_ticks 144463317000 # Number of ticks simulated
|
||||
final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 66822 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 111999 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 73091533 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308580 # Number of bytes of host memory used
|
||||
host_seconds 1976.47 # Real time elapsed on the host
|
||||
host_inst_rate 55445 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 92931 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 60647702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 328672 # Number of bytes of host memory used
|
||||
host_seconds 2382.01 # Real time elapsed on the host
|
||||
sim_insts 132071192 # Number of instructions simulated
|
||||
sim_ops 221363384 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory
|
||||
|
|
@ -207,14 +207,14 @@ system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # By
|
|||
system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 28805000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 28783000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 82293750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -247,12 +247,12 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656
|
|||
system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 342656 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 18648234 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 18648233 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits
|
||||
|
|
@ -264,90 +264,90 @@ system.cpu.workload.num_syscalls 400 # Nu
|
|||
system.cpu.numCycles 289221873 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running
|
||||
system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking
|
||||
system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename
|
||||
system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups
|
||||
system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available
|
||||
|
|
@ -383,7 +383,7 @@ system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued
|
||||
|
|
@ -412,26 +412,26 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued
|
||||
system.cpu.iq.rate 0.900700 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued
|
||||
system.cpu.iq.rate 0.900699 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
|
|
@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 14265860 # Number of branches executed
|
||||
system.cpu.iew.exec_branches 14265859 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 22347175 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.894581 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 205928299 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -500,12 +500,12 @@ system.cpu.commit.branches 12326938 # Nu
|
|||
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 797818 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 571692691 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 659422929 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 571692690 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 659422914 # The number of ROB writes
|
||||
system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
|
||||
|
|
@ -513,13 +513,13 @@ system.cpu.cpi 2.189894 # CP
|
|||
system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 451224157 # number of integer regfile reads
|
||||
system.cpu.int_regfile_reads 451224153 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 233957254 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes
|
||||
system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads
|
||||
system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution
|
||||
|
|
@ -545,49 +545,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3467413 # La
|
|||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4653 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22344301 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 8911 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22344300 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 8910 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked
|
||||
|
|
@ -596,45 +596,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy
|
||||
|
|
@ -666,17 +666,17 @@ system.cpu.l2cache.demand_misses::total 5355 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5355 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -705,17 +705,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.620870 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -737,19 +737,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5355
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -763,37 +763,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 57 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 66102125 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 66102126 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses
|
||||
|
|
@ -810,14 +810,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 176670730
|
|||
system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -13,15 +15,16 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/dist/m5/system/binaries/console
|
||||
console=/scratch/nilay/GEM5/system/binaries/console
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
|
@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -48,6 +52,7 @@ slave=system.membus.master[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -60,6 +65,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -93,6 +99,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -115,11 +122,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
|
|
@ -128,6 +137,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -150,21 +160,26 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -176,6 +191,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -209,6 +225,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -231,11 +248,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
|
|
@ -244,6 +263,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -266,25 +286,31 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
|
|
@ -292,19 +318,22 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -312,28 +341,33 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -347,6 +381,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -369,6 +404,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -378,6 +414,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -400,6 +437,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -407,6 +445,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -418,6 +457,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -433,51 +473,34 @@ warn_access=
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -486,6 +509,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -496,6 +520,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache
|
|||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
|
|
@ -504,6 +529,7 @@ type=AlphaBackdoor
|
|||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -514,6 +540,7 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -542,6 +569,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
|
|
@ -551,8 +579,40 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
|
|
@ -569,6 +629,7 @@ dma_read_delay=0
|
|||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
|
|
@ -592,6 +653,7 @@ pio=system.iobus.master[27]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -609,6 +671,7 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -626,6 +689,7 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -643,6 +707,7 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -660,6 +725,7 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -677,6 +743,7 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -694,6 +761,7 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -711,6 +779,7 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -728,6 +797,7 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -745,6 +815,7 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -762,6 +833,7 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -779,6 +851,7 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -796,6 +869,7 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -813,6 +887,7 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -830,6 +905,7 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -847,6 +923,7 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -864,6 +941,7 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -881,6 +959,7 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -898,6 +977,7 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -916,6 +996,7 @@ pio=system.iobus.master[6]
|
|||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -943,6 +1024,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
|
|
@ -952,8 +1034,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -965,6 +1079,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
io_shift=0
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
|
|
@ -979,6 +1094,7 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -991,6 +1107,7 @@ pio=system.iobus.master[22]
|
|||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1001,6 +1118,7 @@ pio=system.iobus.master[1]
|
|||
type=PciConfigAll
|
||||
bus=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1011,6 +1129,7 @@ pio=system.iobus.default
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1020,5 +1139,6 @@ pio=system.iobus.master[23]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu
|
|||
sim_ticks 1870335522500 # Number of ticks simulated
|
||||
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2234616 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2234615 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66179117761 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308940 # Number of bytes of host memory used
|
||||
host_seconds 28.26 # Real time elapsed on the host
|
||||
host_inst_rate 1806360 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1806359 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53496127424 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 353980 # Number of bytes of host memory used
|
||||
host_seconds 34.96 # Real time elapsed on the host
|
||||
sim_insts 63154034 # Number of instructions simulated
|
||||
sim_ops 63154034 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory
|
||||
|
|
@ -267,7 +267,7 @@ system.cpu0.itb.data_hits 0 # DT
|
|||
system.cpu0.itb.data_misses 0 # DTB misses
|
||||
system.cpu0.itb.data_acv 0 # DTB access violations
|
||||
system.cpu0.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 3740671046 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 57222076 # Number of instructions committed
|
||||
|
|
@ -285,8 +285,8 @@ system.cpu0.num_fp_register_writes 150835 # nu
|
|||
system.cpu0.num_mem_refs 15135515 # number of memory refs
|
||||
system.cpu0.num_load_insts 9184477 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5951038 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
|
||||
system.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -13,15 +15,16 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/dist/m5/system/binaries/console
|
||||
console=/scratch/nilay/GEM5/system/binaries/console
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
|
@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -48,6 +52,7 @@ slave=system.membus.master[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -60,6 +65,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -93,6 +99,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -115,11 +122,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
|
|
@ -128,6 +137,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -150,17 +160,21 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -169,6 +183,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -191,12 +206,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -206,10 +223,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
|
|
@ -217,19 +236,22 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -237,28 +259,33 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -272,6 +299,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -294,6 +322,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -301,6 +330,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -312,6 +342,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -327,51 +358,34 @@ warn_access=
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -380,6 +394,7 @@ port=3456
|
|||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
|
|
@ -388,6 +403,7 @@ type=AlphaBackdoor
|
|||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -398,6 +414,7 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -426,6 +443,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
|
|
@ -435,8 +453,40 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
|
|
@ -453,6 +503,7 @@ dma_read_delay=0
|
|||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
|
|
@ -476,6 +527,7 @@ pio=system.iobus.master[27]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -493,6 +545,7 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -510,6 +563,7 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -527,6 +581,7 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -544,6 +599,7 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -561,6 +617,7 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -578,6 +635,7 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -595,6 +653,7 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -612,6 +671,7 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -629,6 +689,7 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -646,6 +707,7 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -663,6 +725,7 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -680,6 +743,7 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -697,6 +761,7 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -714,6 +779,7 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -731,6 +797,7 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -748,6 +815,7 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -765,6 +833,7 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -782,6 +851,7 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -800,6 +870,7 @@ pio=system.iobus.master[6]
|
|||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -827,6 +898,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
|
|
@ -836,8 +908,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -849,6 +953,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
io_shift=0
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
|
|
@ -863,6 +968,7 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -875,6 +981,7 @@ pio=system.iobus.master[22]
|
|||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -885,6 +992,7 @@ pio=system.iobus.master[1]
|
|||
type=PciConfigAll
|
||||
bus=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
|
|
@ -895,6 +1003,7 @@ pio=system.iobus.default
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -904,5 +1013,6 @@ pio=system.iobus.master[23]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
|
|||
sim_ticks 1829332258000 # Number of ticks simulated
|
||||
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1630624 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1630623 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49684114233 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305868 # Number of bytes of host memory used
|
||||
host_seconds 36.82 # Real time elapsed on the host
|
||||
host_inst_rate 1538182 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1538181 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46867449524 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 350908 # Number of bytes of host memory used
|
||||
host_seconds 39.03 # Real time elapsed on the host
|
||||
sim_insts 60038305 # Number of instructions simulated
|
||||
sim_ops 60038305 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
|
||||
|
|
@ -129,7 +129,7 @@ system.cpu.itb.data_hits 0 # DT
|
|||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3658664517 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038305 # Number of instructions committed
|
||||
|
|
@ -147,8 +147,8 @@ system.cpu.num_fp_register_writes 166520 # nu
|
|||
system.cpu.num_mem_refs 16115709 # number of memory refs
|
||||
system.cpu.num_load_insts 9747513 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368196 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -13,15 +15,16 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/dist/m5/system/binaries/console
|
||||
console=/scratch/nilay/GEM5/system/binaries/console
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
|
@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -48,6 +52,7 @@ slave=system.membus.master[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -60,6 +65,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
|
|
@ -86,6 +92,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -108,11 +115,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
|
|
@ -121,6 +130,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -143,21 +153,26 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -169,6 +184,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
|
|
@ -195,6 +211,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -217,11 +234,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
|
|
@ -230,6 +249,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -252,25 +272,31 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
|
|
@ -278,19 +304,22 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -298,28 +327,33 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -333,6 +367,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -355,6 +390,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -364,6 +400,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -386,6 +423,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -393,6 +431,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -404,6 +443,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -430,6 +470,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -441,29 +482,35 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -472,6 +519,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -482,6 +530,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache
|
|||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
|
|
@ -490,6 +539,7 @@ type=AlphaBackdoor
|
|||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -500,6 +550,7 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -528,6 +579,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
|
|
@ -537,8 +589,40 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
|
|
@ -555,6 +639,7 @@ dma_read_delay=0
|
|||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
|
|
@ -578,6 +663,7 @@ pio=system.iobus.master[27]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -595,6 +681,7 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -612,6 +699,7 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -629,6 +717,7 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -646,6 +735,7 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -663,6 +753,7 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -680,6 +771,7 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -697,6 +789,7 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -714,6 +807,7 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -731,6 +825,7 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -748,6 +843,7 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -765,6 +861,7 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -782,6 +879,7 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -799,6 +897,7 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -816,6 +915,7 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -833,6 +933,7 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -850,6 +951,7 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -867,6 +969,7 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -884,6 +987,7 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -902,6 +1006,7 @@ pio=system.iobus.master[6]
|
|||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -929,6 +1034,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
|
|
@ -938,8 +1044,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -951,6 +1089,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
io_shift=0
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
|
|
@ -965,6 +1104,7 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -977,6 +1117,7 @@ pio=system.iobus.master[22]
|
|||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -987,6 +1128,7 @@ pio=system.iobus.master[1]
|
|||
type=PciConfigAll
|
||||
bus=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
|
|
@ -997,6 +1139,7 @@ pio=system.iobus.default
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1006,5 +1149,6 @@ pio=system.iobus.master[23]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -119,6 +128,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -141,18 +151,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -163,6 +176,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -185,14 +199,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -211,18 +228,21 @@ midr=890224640
|
|||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -234,6 +254,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -267,6 +288,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -289,18 +311,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
|
@ -311,6 +336,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -333,14 +359,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -359,31 +388,37 @@ midr=890224640
|
|||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -396,6 +431,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -418,6 +454,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -427,6 +464,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -449,6 +487,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -456,6 +495,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -467,6 +507,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -482,41 +523,22 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -526,6 +548,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -535,6 +558,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -563,6 +587,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -572,8 +597,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -585,6 +642,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -600,6 +658,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -614,6 +674,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -623,6 +684,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -644,8 +706,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -654,6 +718,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -664,6 +729,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -674,6 +740,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -684,6 +751,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -698,6 +766,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -711,6 +780,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -728,6 +798,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -740,6 +811,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -751,6 +823,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -761,6 +834,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -773,6 +847,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -786,6 +861,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -796,6 +872,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -806,6 +883,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -816,6 +894,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -828,6 +907,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -842,6 +922,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -854,6 +935,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -868,6 +950,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -878,6 +961,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -888,6 +972,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -898,6 +983,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -906,6 +992,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -914,6 +1001,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -923,11 +1011,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu
|
|||
sim_ticks 912096763500 # Number of ticks simulated
|
||||
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1640213 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2111770 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24275992963 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 394600 # Number of bytes of host memory used
|
||||
host_seconds 37.57 # Real time elapsed on the host
|
||||
host_inst_rate 1031681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1328287 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15269405009 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 443324 # Number of bytes of host memory used
|
||||
host_seconds 59.73 # Real time elapsed on the host
|
||||
sim_insts 61625970 # Number of instructions simulated
|
||||
sim_ops 79343340 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
|
||||
|
|
@ -316,7 +316,7 @@ system.cpu0.itb.inst_accesses 30240979 # IT
|
|||
system.cpu0.itb.hits 30238804 # DTB hits
|
||||
system.cpu0.itb.misses 2175 # DTB misses
|
||||
system.cpu0.itb.accesses 30240979 # DTB accesses
|
||||
system.cpu0.numCycles 1823633059 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 1823671407 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 29750005 # Number of instructions committed
|
||||
|
|
@ -334,8 +334,8 @@ system.cpu0.num_fp_register_writes 916 # nu
|
|||
system.cpu0.num_mem_refs 14626951 # number of memory refs
|
||||
system.cpu0.num_load_insts 8357226 # Number of load instructions
|
||||
system.cpu0.num_store_insts 6269725 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles
|
||||
system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -492,7 +492,7 @@ system.cpu1.itb.inst_accesses 32414506 # IT
|
|||
system.cpu1.itb.hits 32412306 # DTB hits
|
||||
system.cpu1.itb.misses 2200 # DTB misses
|
||||
system.cpu1.itb.accesses 32414506 # DTB accesses
|
||||
system.cpu1.numCycles 1824154149 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 1824193528 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 31875965 # Number of instructions committed
|
||||
|
|
@ -510,8 +510,8 @@ system.cpu1.num_fp_register_writes 1416 # nu
|
|||
system.cpu1.num_mem_refs 13370713 # number of memory refs
|
||||
system.cpu1.num_load_insts 7642673 # Number of load instructions
|
||||
system.cpu1.num_store_insts 5728040 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles
|
||||
system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -119,6 +128,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -141,18 +151,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -163,6 +176,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -185,14 +199,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -211,12 +228,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -227,6 +246,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -249,12 +269,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -264,19 +286,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -289,6 +315,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -311,6 +338,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -318,6 +346,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -329,6 +358,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -344,41 +374,22 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -388,6 +399,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -397,6 +409,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -425,6 +438,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -434,8 +448,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -447,6 +493,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -462,6 +509,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -476,6 +525,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -485,6 +535,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -506,8 +557,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -516,6 +569,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -526,6 +580,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -536,6 +591,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -546,6 +602,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -560,6 +617,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -573,6 +631,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -590,6 +649,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -602,6 +662,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -613,6 +674,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -623,6 +685,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -635,6 +698,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -648,6 +712,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -658,6 +723,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -668,6 +734,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -678,6 +745,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -690,6 +758,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -704,6 +773,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -716,6 +786,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -730,6 +801,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -740,6 +812,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -750,6 +823,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -760,6 +834,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -768,6 +843,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -775,11 +851,13 @@ port=3456
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1754227 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2255827 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 67743178392 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 394608 # Number of bytes of host memory used
|
||||
host_seconds 34.44 # Real time elapsed on the host
|
||||
host_inst_rate 993135 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1277110 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38352024586 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 443324 # Number of bytes of host memory used
|
||||
host_seconds 60.83 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
|
|
@ -114,7 +114,7 @@ system.cpu.itb.inst_accesses 61436311 # IT
|
|||
system.cpu.itb.hits 61431840 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 61436311 # DTB accesses
|
||||
system.cpu.numCycles 4665543516 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4665620529 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60408639 # Number of instructions committed
|
||||
|
|
@ -132,8 +132,8 @@ system.cpu.num_fp_register_writes 2780 # nu
|
|||
system.cpu.num_mem_refs 27361637 # number of memory refs
|
||||
system.cpu.num_load_insts 15639527 # Number of load instructions
|
||||
system.cpu.num_store_insts 11722110 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
|
|
@ -112,6 +121,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -134,18 +144,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -156,6 +169,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -178,14 +192,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -204,18 +221,21 @@ midr=890224640
|
|||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -227,6 +247,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
|
|
@ -253,6 +274,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -275,18 +297,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
|
@ -297,6 +322,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -319,14 +345,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -345,31 +374,37 @@ midr=890224640
|
|||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -382,6 +417,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -404,6 +440,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -413,6 +450,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -435,6 +473,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -442,6 +481,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -453,6 +493,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -479,6 +520,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -490,19 +532,23 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -512,6 +558,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -521,6 +568,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -549,6 +597,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -558,8 +607,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -571,6 +652,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -586,6 +668,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -600,6 +684,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -609,6 +694,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -630,8 +716,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -640,6 +728,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -650,6 +739,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -660,6 +750,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -670,6 +761,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -684,6 +776,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -697,6 +790,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -714,6 +808,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -726,6 +821,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -737,6 +833,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -747,6 +844,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -759,6 +857,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -772,6 +871,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -782,6 +882,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -792,6 +893,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -802,6 +904,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -814,6 +917,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -828,6 +932,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -840,6 +945,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -854,6 +960,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -864,6 +971,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -874,6 +982,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -884,6 +993,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -892,6 +1002,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -900,6 +1011,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -909,11 +1021,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -112,6 +121,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -134,18 +144,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -156,6 +169,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -178,14 +192,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -204,12 +221,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
|
@ -220,6 +239,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -242,12 +262,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -257,19 +279,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -282,6 +308,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -304,6 +331,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -311,6 +339,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -322,6 +351,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -348,6 +378,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -359,19 +390,23 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -381,6 +416,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -390,6 +426,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -418,6 +455,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -427,8 +465,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -440,6 +510,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -455,6 +526,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -469,6 +542,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -478,6 +552,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -499,8 +574,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -509,6 +586,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -519,6 +597,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -529,6 +608,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -539,6 +619,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -553,6 +634,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -566,6 +648,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -583,6 +666,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -595,6 +679,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -606,6 +691,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -616,6 +702,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -628,6 +715,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -641,6 +729,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -651,6 +740,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -661,6 +751,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -671,6 +762,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -683,6 +775,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -697,6 +790,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -709,6 +803,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -723,6 +818,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -733,6 +829,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -743,6 +840,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -753,6 +851,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -761,6 +860,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -768,11 +868,13 @@ port=3456
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
dtb_filename=
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -45,6 +48,7 @@ system_port=system.membus.slave[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -56,24 +60,28 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -86,6 +94,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -119,6 +128,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -141,18 +151,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -163,6 +176,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -185,14 +199,17 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -211,18 +228,21 @@ midr=890224640
|
|||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -234,6 +254,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -262,17 +283,20 @@ workload=
|
|||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
|
@ -291,30 +315,36 @@ midr=890224640
|
|||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -327,6 +357,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -349,6 +380,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -358,6 +390,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -380,6 +413,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
|
|
@ -387,6 +421,7 @@ size=4194304
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -398,6 +433,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -413,41 +449,22 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
|
|
@ -457,6 +474,7 @@ system=system
|
|||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -466,6 +484,7 @@ pio=system.membus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -494,6 +513,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
|
|
@ -503,8 +523,40 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -516,6 +568,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
io_shift=1
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
|
|
@ -531,6 +584,8 @@ pio=system.iobus.master[7]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -545,6 +600,7 @@ pio=system.iobus.master[4]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -554,6 +610,7 @@ pio=system.iobus.master[9]
|
|||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -575,8 +632,10 @@ cpu_addr=520093952
|
|||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
msix_addr=0
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
|
@ -585,6 +644,7 @@ pio=system.membus.master[2]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -595,6 +655,7 @@ pio=system.iobus.master[16]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -605,6 +666,7 @@ pio=system.iobus.master[17]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -615,6 +677,7 @@ pio=system.iobus.master[18]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -629,6 +692,7 @@ pio=system.iobus.master[5]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -642,6 +706,7 @@ pio=system.iobus.master[6]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -659,6 +724,7 @@ pio=system.membus.master[3]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
|
|
@ -671,6 +737,7 @@ pio=system.membus.master[5]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -682,6 +749,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -692,6 +760,7 @@ port=system.membus.master[1]
|
|||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -704,6 +773,7 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -717,6 +787,7 @@ pio=system.iobus.master[23]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -727,6 +798,7 @@ pio=system.iobus.master[20]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -737,6 +809,7 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -747,6 +820,7 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -759,6 +833,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
|
|
@ -773,6 +848,7 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
|
|
@ -785,6 +861,7 @@ pio=system.iobus.master[3]
|
|||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
|
|
@ -799,6 +876,7 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -809,6 +887,7 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -819,6 +898,7 @@ pio=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -829,6 +909,7 @@ pio=system.iobus.master[12]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -837,6 +918,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -845,6 +927,7 @@ port=3456
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -854,11 +937,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa
|
|||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
eventq_index=0
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,13 +4,25 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1464492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1883246 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56554479678 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 398712 # Number of bytes of host memory used
|
||||
host_seconds 41.25 # Real time elapsed on the host
|
||||
host_inst_rate 840369 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1080663 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32452660609 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 444352 # Number of bytes of host memory used
|
||||
host_seconds 71.88 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
|
|
@ -62,18 +74,6 @@ system.physmem.bw_total::cpu0.data 3386724 # To
|
|||
system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55969561 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566366 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -286,7 +286,7 @@ system.cpu0.itb.inst_accesses 32546956 # IT
|
|||
system.cpu0.itb.hits 32543253 # DTB hits
|
||||
system.cpu0.itb.misses 3703 # DTB misses
|
||||
system.cpu0.itb.accesses 32546956 # DTB accesses
|
||||
system.cpu0.numCycles 4633589665 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 4633633401 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 31998091 # Number of instructions committed
|
||||
|
|
@ -304,8 +304,8 @@ system.cpu0.num_fp_register_writes 1428 # nu
|
|||
system.cpu0.num_mem_refs 15013057 # number of memory refs
|
||||
system.cpu0.num_load_insts 8304661 # Number of load instructions
|
||||
system.cpu0.num_store_insts 6708396 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles
|
||||
system.cpu0.num_idle_cycles 4555668120.247687 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 77965280.752313 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -496,7 +496,7 @@ system.cpu1.itb.inst_accesses 28889355 # IT
|
|||
system.cpu1.itb.hits 28886892 # DTB hits
|
||||
system.cpu1.itb.misses 2463 # DTB misses
|
||||
system.cpu1.itb.accesses 28889355 # DTB accesses
|
||||
system.cpu1.numCycles 4279954879 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 4279988156 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 28410548 # Number of instructions committed
|
||||
|
|
@ -514,8 +514,8 @@ system.cpu1.num_fp_register_writes 1352 # nu
|
|||
system.cpu1.num_mem_refs 12348580 # number of memory refs
|
||||
system.cpu1.num_load_insts 7334866 # Number of load instructions
|
||||
system.cpu1.num_store_insts 5013714 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles
|
||||
system.cpu1.num_idle_cycles 4217686174.280304 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 62301981.719696 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
|||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
e820_table=system.e820_table
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
|
|
@ -38,6 +41,7 @@ system_port=system.membus.slave[1]
|
|||
[system.acpi_description_table_pointer]
|
||||
type=X86ACPIRSDP
|
||||
children=xsdt
|
||||
eventq_index=0
|
||||
oem_id=
|
||||
revision=2
|
||||
rsdt=Null
|
||||
|
|
@ -48,6 +52,7 @@ type=X86ACPIXSDT
|
|||
creator_id=
|
||||
creator_revision=0
|
||||
entries=
|
||||
eventq_index=0
|
||||
oem_id=
|
||||
oem_revision=0
|
||||
oem_table_id=
|
||||
|
|
@ -56,6 +61,7 @@ oem_table_id=
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -66,6 +72,7 @@ slave=system.iobus.master[0]
|
|||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -75,6 +82,7 @@ slave=system.membus.master[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -87,6 +95,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
|
@ -118,6 +127,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -125,6 +135,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,18 +158,21 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.dtb_walker_cache.cpu_side
|
||||
|
|
@ -169,6 +183,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -191,6 +206,7 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=1024
|
||||
|
||||
|
|
@ -200,6 +216,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -222,12 +239,14 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -238,16 +257,19 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.itb_walker_cache.cpu_side
|
||||
|
|
@ -258,6 +280,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -280,6 +303,7 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=1024
|
||||
|
||||
|
|
@ -289,6 +313,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -311,12 +336,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -326,44 +353,52 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.e820_table]
|
||||
type=X86E820Table
|
||||
children=entries0 entries1 entries2 entries3
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
|
||||
eventq_index=0
|
||||
|
||||
[system.e820_table.entries0]
|
||||
type=X86E820Entry
|
||||
addr=0
|
||||
eventq_index=0
|
||||
range_type=1
|
||||
size=654336
|
||||
|
||||
[system.e820_table.entries1]
|
||||
type=X86E820Entry
|
||||
addr=654336
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
size=394240
|
||||
|
||||
[system.e820_table.entries2]
|
||||
type=X86E820Entry
|
||||
addr=1048576
|
||||
eventq_index=0
|
||||
range_type=1
|
||||
size=133169152
|
||||
|
||||
[system.e820_table.entries3]
|
||||
type=X86E820Entry
|
||||
addr=4294901760
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
size=65536
|
||||
|
||||
[system.intel_mp_pointer]
|
||||
type=X86IntelMPFloatingPointer
|
||||
default_config=0
|
||||
eventq_index=0
|
||||
imcr_present=true
|
||||
spec_rev=4
|
||||
|
||||
|
|
@ -371,6 +406,7 @@ spec_rev=4
|
|||
type=X86IntelMPConfigTable
|
||||
children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
|
||||
base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
|
||||
eventq_index=0
|
||||
ext_entries=system.intel_mp_table.ext_entries
|
||||
local_apic=4276092928
|
||||
oem_id=
|
||||
|
|
@ -383,6 +419,7 @@ spec_rev=4
|
|||
type=X86IntelMPProcessor
|
||||
bootstrap=true
|
||||
enable=true
|
||||
eventq_index=0
|
||||
family=0
|
||||
feature_flags=0
|
||||
local_apic_id=0
|
||||
|
|
@ -394,6 +431,7 @@ stepping=0
|
|||
type=X86IntelMPIOAPIC
|
||||
address=4273995776
|
||||
enable=true
|
||||
eventq_index=0
|
||||
id=1
|
||||
version=17
|
||||
|
||||
|
|
@ -401,16 +439,19 @@ version=17
|
|||
type=X86IntelMPBus
|
||||
bus_id=0
|
||||
bus_type=ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries03]
|
||||
type=X86IntelMPBus
|
||||
bus_id=1
|
||||
bus_type=PCI
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries04]
|
||||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=16
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=1
|
||||
|
|
@ -421,6 +462,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -431,6 +473,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=2
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -441,6 +484,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -451,6 +495,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=1
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -461,6 +506,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -471,6 +517,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=3
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -481,6 +528,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -491,6 +539,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=4
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -501,6 +550,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -511,6 +561,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=5
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -521,6 +572,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -531,6 +583,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=6
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -541,6 +594,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -551,6 +605,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=7
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -561,6 +616,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -571,6 +627,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=8
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -581,6 +638,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -591,6 +649,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=9
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -601,6 +660,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -611,6 +671,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=10
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -621,6 +682,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -631,6 +693,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=11
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -641,6 +704,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -651,6 +715,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=12
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -661,6 +726,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -671,6 +737,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=13
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -681,6 +748,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=0
|
||||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -691,6 +759,7 @@ trigger=ConformTrigger
|
|||
type=X86IntelMPIOIntAssignment
|
||||
dest_io_apic_id=1
|
||||
dest_io_apic_intin=14
|
||||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
|
|
@ -700,16 +769,19 @@ trigger=ConformTrigger
|
|||
[system.intel_mp_table.ext_entries]
|
||||
type=X86IntelMPBusHierarchy
|
||||
bus_id=0
|
||||
eventq_index=0
|
||||
parent_bus=1
|
||||
subtractive_decode=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -723,6 +795,7 @@ children=tags
|
|||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -745,6 +818,7 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
|
|
@ -752,6 +826,7 @@ size=1024
|
|||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -763,6 +838,7 @@ slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side sy
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -779,13 +855,15 @@ pio=system.membus.default
|
|||
|
||||
[system.pc]
|
||||
type=Pc
|
||||
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
|
||||
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.pc.behind_pci]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854779128
|
||||
pio_latency=100000
|
||||
|
|
@ -804,6 +882,7 @@ pio=system.iobus.master[12]
|
|||
type=Uart8250
|
||||
children=terminal
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=9223372036854776824
|
||||
pio_latency=100000
|
||||
platform=system.pc
|
||||
|
|
@ -813,13 +892,7 @@ pio=system.iobus.master[13]
|
|||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
|
|
@ -828,6 +901,7 @@ port=3456
|
|||
[system.pc.fake_com_2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776568
|
||||
pio_latency=100000
|
||||
|
|
@ -845,6 +919,7 @@ pio=system.iobus.master[14]
|
|||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776808
|
||||
pio_latency=100000
|
||||
|
|
@ -862,6 +937,7 @@ pio=system.iobus.master[15]
|
|||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776552
|
||||
pio_latency=100000
|
||||
|
|
@ -879,6 +955,7 @@ pio=system.iobus.master[16]
|
|||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776818
|
||||
pio_latency=100000
|
||||
|
|
@ -896,6 +973,7 @@ pio=system.iobus.master[17]
|
|||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854775936
|
||||
pio_latency=100000
|
||||
|
|
@ -914,6 +992,7 @@ pio=system.iobus.master[11]
|
|||
type=PciConfigAll
|
||||
bus=0
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.pc
|
||||
|
|
@ -926,6 +1005,7 @@ type=SouthBridge
|
|||
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
|
||||
cmos=system.pc.south_bridge.cmos
|
||||
dma1=system.pc.south_bridge.dma1
|
||||
eventq_index=0
|
||||
io_apic=system.pc.south_bridge.io_apic
|
||||
keyboard=system.pc.south_bridge.keyboard
|
||||
pic1=system.pc.south_bridge.pic1
|
||||
|
|
@ -938,6 +1018,7 @@ speaker=system.pc.south_bridge.speaker
|
|||
type=Cmos
|
||||
children=int_pin
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||
pio_addr=9223372036854775920
|
||||
pio_latency=100000
|
||||
|
|
@ -947,10 +1028,12 @@ pio=system.iobus.master[1]
|
|||
|
||||
[system.pc.south_bridge.cmos.int_pin]
|
||||
type=X86IntSourcePin
|
||||
eventq_index=0
|
||||
|
||||
[system.pc.south_bridge.dma1]
|
||||
type=I8237
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
pio_addr=9223372036854775808
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -979,6 +1062,7 @@ BAR5LegacyIO=false
|
|||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CapabilityPtr=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
|
|
@ -988,8 +1072,40 @@ HeaderType=0
|
|||
InterruptLine=14
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
MSICAPMsgAddr=0
|
||||
MSICAPMsgCtrl=0
|
||||
MSICAPMsgData=0
|
||||
MSICAPMsgUpperAddr=0
|
||||
MSICAPNextCapability=0
|
||||
MSICAPPendingBits=0
|
||||
MSIXCAPBaseOffset=0
|
||||
MSIXCAPCapId=0
|
||||
MSIXCAPNextCapability=0
|
||||
MSIXMsgCtrl=0
|
||||
MSIXPbaOffset=0
|
||||
MSIXTableOffset=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
PMCAPBaseOffset=0
|
||||
PMCAPCapId=0
|
||||
PMCAPCapabilities=0
|
||||
PMCAPCtrlStatus=0
|
||||
PMCAPNextCapability=0
|
||||
PXCAPBaseOffset=0
|
||||
PXCAPCapId=0
|
||||
PXCAPCapabilities=0
|
||||
PXCAPDevCap2=0
|
||||
PXCAPDevCapabilities=0
|
||||
PXCAPDevCtrl=0
|
||||
PXCAPDevCtrl2=0
|
||||
PXCAPDevStatus=0
|
||||
PXCAPLinkCap=0
|
||||
PXCAPLinkCtrl=0
|
||||
PXCAPLinkStatus=0
|
||||
PXCAPNextCapability=0
|
||||
ProgIF=128
|
||||
Revision=0
|
||||
Status=640
|
||||
|
|
@ -1001,6 +1117,7 @@ clk_domain=system.clk_domain
|
|||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
|
||||
eventq_index=0
|
||||
io_shift=0
|
||||
pci_bus=0
|
||||
pci_dev=4
|
||||
|
|
@ -1017,19 +1134,22 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.pc.south_bridge.ide.disks0.image
|
||||
|
||||
[system.pc.south_bridge.ide.disks0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.pc.south_bridge.ide.disks0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1037,102 +1157,120 @@ type=IdeDisk
|
|||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
eventq_index=0
|
||||
image=system.pc.south_bridge.ide.disks1.image
|
||||
|
||||
[system.pc.south_bridge.ide.disks1.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.pc.south_bridge.ide.disks1.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines0.sink
|
||||
source=system.pc.south_bridge.pic1.output
|
||||
|
||||
[system.pc.south_bridge.int_lines0.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
eventq_index=0
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines1]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines1.sink
|
||||
source=system.pc.south_bridge.pic2.output
|
||||
|
||||
[system.pc.south_bridge.int_lines1.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic1
|
||||
eventq_index=0
|
||||
number=2
|
||||
|
||||
[system.pc.south_bridge.int_lines2]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines2.sink
|
||||
source=system.pc.south_bridge.cmos.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines2.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic2
|
||||
eventq_index=0
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines3]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines3.sink
|
||||
source=system.pc.south_bridge.pit.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines3.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic1
|
||||
eventq_index=0
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines4]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines4.sink
|
||||
source=system.pc.south_bridge.pit.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines4.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
eventq_index=0
|
||||
number=2
|
||||
|
||||
[system.pc.south_bridge.int_lines5]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines5.sink
|
||||
source=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines5.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
eventq_index=0
|
||||
number=1
|
||||
|
||||
[system.pc.south_bridge.int_lines6]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
eventq_index=0
|
||||
sink=system.pc.south_bridge.int_lines6.sink
|
||||
source=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines6.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
eventq_index=0
|
||||
number=12
|
||||
|
||||
[system.pc.south_bridge.io_apic]
|
||||
type=I82094AA
|
||||
apic_id=1
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
external_int_pic=system.pc.south_bridge.pic1
|
||||
int_latency=1000
|
||||
pio_addr=4273995776
|
||||
|
|
@ -1147,6 +1285,7 @@ children=keyboard_int_pin mouse_int_pin
|
|||
clk_domain=system.clk_domain
|
||||
command_port=9223372036854775908
|
||||
data_port=9223372036854775904
|
||||
eventq_index=0
|
||||
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||
pio_addr=0
|
||||
|
|
@ -1156,14 +1295,17 @@ pio=system.iobus.master[5]
|
|||
|
||||
[system.pc.south_bridge.keyboard.keyboard_int_pin]
|
||||
type=X86IntSourcePin
|
||||
eventq_index=0
|
||||
|
||||
[system.pc.south_bridge.keyboard.mouse_int_pin]
|
||||
type=X86IntSourcePin
|
||||
eventq_index=0
|
||||
|
||||
[system.pc.south_bridge.pic1]
|
||||
type=I8259
|
||||
children=output
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
mode=I8259Master
|
||||
output=system.pc.south_bridge.pic1.output
|
||||
pio_addr=9223372036854775840
|
||||
|
|
@ -1174,11 +1316,13 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.pc.south_bridge.pic1.output]
|
||||
type=X86IntSourcePin
|
||||
eventq_index=0
|
||||
|
||||
[system.pc.south_bridge.pic2]
|
||||
type=I8259
|
||||
children=output
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
mode=I8259Slave
|
||||
output=system.pc.south_bridge.pic2.output
|
||||
pio_addr=9223372036854775968
|
||||
|
|
@ -1189,11 +1333,13 @@ pio=system.iobus.master[7]
|
|||
|
||||
[system.pc.south_bridge.pic2.output]
|
||||
type=X86IntSourcePin
|
||||
eventq_index=0
|
||||
|
||||
[system.pc.south_bridge.pit]
|
||||
type=I8254
|
||||
children=int_pin
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
int_pin=system.pc.south_bridge.pit.int_pin
|
||||
pio_addr=9223372036854775872
|
||||
pio_latency=100000
|
||||
|
|
@ -1202,10 +1348,12 @@ pio=system.iobus.master[8]
|
|||
|
||||
[system.pc.south_bridge.pit.int_pin]
|
||||
type=X86IntSourcePin
|
||||
eventq_index=0
|
||||
|
||||
[system.pc.south_bridge.speaker]
|
||||
type=PcSpeaker
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
i8254=system.pc.south_bridge.pit
|
||||
pio_addr=9223372036854775905
|
||||
pio_latency=100000
|
||||
|
|
@ -1213,41 +1361,22 @@ system=system
|
|||
pio=system.iobus.master[9]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.smbios_table]
|
||||
type=X86SMBiosSMBiosTable
|
||||
children=structures
|
||||
eventq_index=0
|
||||
major_version=2
|
||||
minor_version=5
|
||||
structures=system.smbios_table.structures
|
||||
|
|
@ -1258,6 +1387,7 @@ characteristic_ext_bytes=
|
|||
characteristics=
|
||||
emb_cont_firmware_major=0
|
||||
emb_cont_firmware_minor=0
|
||||
eventq_index=0
|
||||
major=0
|
||||
minor=0
|
||||
release_date=06/08/2008
|
||||
|
|
@ -1268,5 +1398,6 @@ version=
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112126 # Nu
|
|||
sim_ticks 5112126264500 # Number of ticks simulated
|
||||
final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1904189 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3898708 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48689346278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 587596 # Number of bytes of host memory used
|
||||
host_seconds 104.99 # Real time elapsed on the host
|
||||
host_inst_rate 1049292 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2148359 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26829969216 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 634884 # Number of bytes of host memory used
|
||||
host_seconds 190.54 # Real time elapsed on the host
|
||||
sim_insts 199929810 # Number of instructions simulated
|
||||
sim_ops 409343850 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
|
||||
|
|
@ -107,7 +107,7 @@ system.pc.south_bridge.ide.disks1.dma_write_bytes 4096
|
|||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iobus.throughput 2555207 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 13062542 # Total data (bytes)
|
||||
system.cpu.numCycles 10224252551 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224253904 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199929810 # Number of instructions committed
|
||||
|
|
@ -127,8 +127,8 @@ system.cpu.num_cc_register_writes 157233555 # nu
|
|||
system.cpu.num_mem_refs 35660913 # number of memory refs
|
||||
system.cpu.num_load_insts 27238816 # Number of load instructions
|
||||
system.cpu.num_store_insts 8422097 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770516920.735764 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453735630.264235 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,17 +518,21 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -482,6 +541,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -504,12 +564,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -528,7 +591,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
eventq_index=0
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -542,11 +606,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -566,6 +632,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -577,17 +644,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 21065000 # Number of ticks simulated
|
||||
final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31290 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31288 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 103426086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226120 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_inst_rate 36663 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36659 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 121177991 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273132 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
|
||||
|
|
@ -214,8 +214,8 @@ system.membus.reqLayer0.occupancy 619000 # La
|
|||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.6 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2884 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 2883 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1697 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 756 # Number of BTB hits
|
||||
|
|
@ -259,11 +259,11 @@ system.cpu.workload.num_syscalls 17 # Nu
|
|||
system.cpu.numCycles 42131 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.icacheStallCycles 8531 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 16553 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2883 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 2963 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
|
|
@ -271,24 +271,24 @@ system.cpu.fetch.PendingTrapStallCycles 747 # Nu
|
|||
system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.095282 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.492986 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 12150 80.39% 80.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 318 2.10% 82.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 234 1.55% 84.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 255 1.69% 87.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 240 1.59% 88.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 264 1.75% 90.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 183 1.21% 91.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1255 8.30% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.068429 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.392894 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2764 # Number of cycles decode is running
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=MipsTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,19 +518,23 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=MipsInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=MipsISA
|
||||
eventq_index=0
|
||||
num_threads=1
|
||||
num_vpes=1
|
||||
|
||||
[system.cpu.itb]
|
||||
type=MipsTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -484,6 +543,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -506,12 +566,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -521,6 +583,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -530,7 +593,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
eventq_index=0
|
||||
executable=tests/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -544,11 +608,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -568,6 +634,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -579,17 +646,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 21898500 # Number of ticks simulated
|
||||
final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 64871 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64859 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 275425114 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 255508 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 34889 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 34885 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 148144968 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274956 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 5156 # Number of instructions simulated
|
||||
sim_ops 5156 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
|
||||
|
|
@ -208,9 +208,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2174 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted
|
||||
|
|
@ -272,31 +272,31 @@ system.cpu.fetch.rateDist::max_value 8 # Nu
|
|||
system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle
|
||||
system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 3026 # Number of cycles decode is running
|
||||
system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2899 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer
|
||||
|
|
@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 868 # Nu
|
|||
system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
|
||||
|
|
@ -538,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n
|
|||
system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 451 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
|
||||
|
|
@ -556,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517
|
|||
system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -582,32 +582,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338
|
|||
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy
|
||||
|
|
@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 477 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -64,6 +68,8 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -128,6 +134,7 @@ BTBTagSize=16
|
|||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
|
|
@ -143,6 +150,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -165,26 +173,31 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
|
@ -193,16 +206,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
|
@ -211,22 +227,26 @@ opLat=20
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
|
@ -235,22 +255,26 @@ opLat=2
|
|||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
|
@ -259,10 +283,12 @@ opLat=24
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
|
@ -271,124 +297,145 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
|
@ -397,10 +444,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -409,16 +458,19 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
|
@ -427,10 +479,12 @@ opLat=1
|
|||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
|
@ -441,6 +495,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -463,20 +518,25 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa0]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa1]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
eventq_index=0
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
|
@ -485,6 +545,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -507,12 +568,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -522,6 +585,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload0]
|
||||
type=LiveProcess
|
||||
|
|
@ -531,7 +595,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
eventq_index=0
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -550,7 +615,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
eventq_index=0
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -564,11 +630,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -588,6 +656,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
|
|
@ -599,17 +668,21 @@ static_backend_latency=10000
|
|||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
|
|||
sim_ticks 24229500 # Number of ticks simulated
|
||||
final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 81251 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 81244 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 154440285 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227736 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 38113 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38111 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72448291 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273720 # Number of bytes of host memory used
|
||||
host_seconds 0.33 # Real time elapsed on the host
|
||||
sim_insts 12745 # Number of instructions simulated
|
||||
sim_ops 12745 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
|
||||
|
|
@ -219,34 +219,34 @@ system.membus.reqLayer0.utilization 5.1 # La
|
|||
system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 37.4 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 6676 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 4747 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 873 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 18.390562 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 4588 # DTB read hits
|
||||
system.cpu.dtb.read_hits 4587 # DTB read hits
|
||||
system.cpu.dtb.read_misses 111 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 4699 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 4698 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 2013 # DTB write hits
|
||||
system.cpu.dtb.write_misses 87 # DTB write misses
|
||||
system.cpu.dtb.write_misses 86 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 2100 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 6601 # DTB hits
|
||||
system.cpu.dtb.data_misses 198 # DTB misses
|
||||
system.cpu.dtb.write_accesses 2099 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 6600 # DTB hits
|
||||
system.cpu.dtb.data_misses 197 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 6799 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 5373 # ITB hits
|
||||
system.cpu.dtb.data_accesses 6797 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 5374 # ITB hits
|
||||
system.cpu.itb.fetch_misses 57 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 5430 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 5431 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -265,50 +265,50 @@ system.cpu.numCycles 48460 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Insts 37128 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 6222 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched
|
||||
system.cpu.fetch.CacheLines 5374 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 29555 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.256234 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.686456 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 23333 78.95% 78.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 457 1.55% 87.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 520 1.76% 89.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 3045 10.30% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 29555 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 5338 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing
|
||||
system.cpu.fetch.rate 0.766158 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 40476 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9889 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 5340 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 489 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 2737 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking
|
||||
system.cpu.rename.SquashCycles 2737 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 41177 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 6164 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 5023 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.UnblockCycles 2245 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 30189 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made
|
||||
|
|
@ -318,31 +318,31 @@ system.cpu.rename.CommittedMaps 9140 # Nu
|
|||
system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 6114 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep1.insertedLoads 3034 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads.
|
||||
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsAdded 26322 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 29555 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.731721 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.328495 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 20216 68.40% 68.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3350 11.33% 79.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2622 8.87% 88.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1591 5.38% 93.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 1010 3.42% 97.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle
|
||||
|
|
@ -350,7 +350,7 @@ system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 29555 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available
|
||||
|
|
@ -421,36 +421,36 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 10800 # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IntAlu 7138 65.93% 65.95% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.96% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.96% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::MemRead 2586 23.89% 89.87% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -463,9 +463,9 @@ system.cpu.iq.fu_busy_cnt::total 185 # FU
|
|||
system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 73081 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 18684 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
||||
|
|
@ -483,34 +483,34 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 #
|
|||
system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread1.squashedLoads 1851 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread1.cacheBlocked 407 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 2737 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 6004 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 20163 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecLoadInsts::1 2365 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecLoadInsts::total 4716 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
||||
|
|
@ -518,47 +518,47 @@ system.cpu.iew.exec_nop::0 109 # nu
|
|||
system.cpu.iew.exec_nop::1 90 # number of nop insts executed
|
||||
system.cpu.iew.exec_nop::total 199 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs::1 3412 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs::total 6829 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches::0 1584 # Number of branches executed
|
||||
system.cpu.iew.exec_branches::1 1595 # Number of branches executed
|
||||
system.cpu.iew.exec_branches::total 3179 # Number of branches executed
|
||||
system.cpu.iew.exec_stores::0 1066 # Number of stores executed
|
||||
system.cpu.iew.exec_stores::1 1048 # Number of stores executed
|
||||
system.cpu.iew.exec_stores::total 2114 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.416096 # Inst execution rate
|
||||
system.cpu.iew.exec_stores::1 1047 # Number of stores executed
|
||||
system.cpu.iew.exec_stores::total 2113 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.416075 # Inst execution rate
|
||||
system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_count::1 9371 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_count::total 18704 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers::0 4798 # num instructions producing a value
|
||||
system.cpu.iew.wb_producers::1 4829 # num instructions producing a value
|
||||
system.cpu.iew.wb_producers::total 9627 # num instructions producing a value
|
||||
system.cpu.iew.wb_producers::1 4830 # num instructions producing a value
|
||||
system.cpu.iew.wb_producers::total 9628 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers::1 6320 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers::total 12567 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate::1 0.193376 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate::total 0.385968 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back
|
||||
system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back
|
||||
system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back
|
||||
system.cpu.iew.wb_fanout::1 0.764241 # average fanout of values written-back
|
||||
system.cpu.iew.wb_fanout::total 0.766134 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 29488 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.433363 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.196034 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 23747 80.53% 80.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle
|
||||
|
|
@ -570,7 +570,7 @@ system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 29488 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts::0 6390 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
||||
|
|
@ -605,10 +605,10 @@ system.cpu.commit.bw_lim_events 211 # nu
|
|||
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 132694 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 55968 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 132697 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 55969 # The number of ROB writes
|
||||
system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 18905 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts::0 6373 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
|
||||
system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated
|
||||
|
|
@ -620,8 +620,8 @@ system.cpu.cpi_total 3.802275 # CP
|
|||
system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 25291 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 14128 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 25289 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 14129 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
||||
|
|
@ -649,19 +649,19 @@ system.cpu.icache.tags.replacements::0 6 # nu
|
|||
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.icache.tags.replacements::total 6 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 4320 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.900958 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4319 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4320 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4320 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4320 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4320 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4320 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4320 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses
|
||||
|
|
@ -674,18 +674,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 69934495
|
|||
system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5369 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5369 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5369 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5369 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5369 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5369 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195381 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.195381 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.195381 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.195381 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.195381 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.195381 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency
|
||||
|
|
@ -718,12 +718,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746
|
|||
system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116617 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.116617 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.116617 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bu
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
|
|
@ -71,6 +76,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -93,11 +99,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
|
|
@ -106,6 +114,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -128,21 +137,26 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -152,7 +166,8 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
|
||||
eventq_index=0
|
||||
executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -173,6 +188,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
|
|
@ -199,6 +215,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -221,11 +238,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
|
|
@ -234,6 +253,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -256,21 +276,26 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -282,6 +307,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu2.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu2.interrupts
|
||||
|
|
@ -308,6 +334,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -330,11 +357,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu2.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu2.icache]
|
||||
|
|
@ -343,6 +372,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -365,21 +395,26 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu2.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu3]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -391,6 +426,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu3.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu3.interrupts
|
||||
|
|
@ -417,6 +453,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -439,11 +476,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu3.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu3.icache]
|
||||
|
|
@ -452,6 +491,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -474,25 +514,31 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu3.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu3.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu3.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu3.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.l2c]
|
||||
|
|
@ -501,6 +547,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -523,12 +570,14 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -541,6 +590,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -551,6 +601,7 @@ port=system.membus.master[0]
|
|||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -560,5 +611,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu
|
|||
sim_ticks 262794500 # Number of ticks simulated
|
||||
final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 681070 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 681053 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 269712940 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243700 # Number of bytes of host memory used
|
||||
host_seconds 0.97 # Real time elapsed on the host
|
||||
host_inst_rate 200508 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 200507 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 79406810 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291148 # Number of bytes of host memory used
|
||||
host_seconds 3.31 # Real time elapsed on the host
|
||||
sim_insts 663567 # Number of instructions simulated
|
||||
sim_ops 663567 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
|
||||
|
|
@ -169,36 +169,36 @@ system.l2c.overall_misses::cpu3.data 16 # nu
|
|||
system.l2c.overall_misses::total 592 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -277,36 +277,36 @@ system.l2c.overall_miss_rate::cpu3.data 0.640000 # mi
|
|||
system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -385,28 +385,28 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000
|
|||
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -459,28 +459,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000
|
|||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.toL2Bus.throughput 646588875 # Throughput (bytes/s)
|
||||
system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
|
||||
|
|
@ -767,17 +767,17 @@ system.cpu1.num_fp_register_writes 0 # nu
|
|||
system.cpu1.num_mem_refs 58020 # number of memory refs
|
||||
system.cpu1.num_load_insts 41540 # Number of load instructions
|
||||
system.cpu1.num_store_insts 16480 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles
|
||||
system.cpu1.icache.tags.replacements 280 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits
|
||||
|
|
@ -792,12 +792,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 366 #
|
|||
system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 366 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles
|
||||
system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles
|
||||
system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles
|
||||
system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles
|
||||
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles
|
||||
system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles
|
||||
system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles
|
||||
system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses
|
||||
|
|
@ -810,12 +810,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238
|
|||
system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses
|
||||
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency
|
||||
system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency
|
||||
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
|
||||
system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency
|
||||
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency
|
||||
system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency
|
||||
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
|
||||
system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -830,24 +830,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366
|
|||
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
|
||||
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
||||
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses
|
||||
system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses
|
||||
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses
|
||||
system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses
|
||||
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency
|
||||
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
|
||||
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency
|
||||
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use
|
||||
|
|
@ -878,16 +878,16 @@ system.cpu1.dcache.demand_misses::cpu1.data 263 #
|
|||
system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 263 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles
|
||||
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles
|
||||
system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -908,16 +908,16 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539
|
|||
system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency
|
||||
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency
|
||||
system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -936,16 +936,16 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 263
|
|||
system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -956,16 +956,16 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539
|
|||
system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency
|
||||
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency
|
||||
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.numCycles 525588 # number of cpu cycles simulated
|
||||
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -985,17 +985,17 @@ system.cpu2.num_fp_register_writes 0 # nu
|
|||
system.cpu2.num_mem_refs 59208 # number of memory refs
|
||||
system.cpu2.num_load_insts 42171 # Number of load instructions
|
||||
system.cpu2.num_store_insts 17037 # Number of store instructions
|
||||
system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles
|
||||
system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles
|
||||
system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles
|
||||
system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles
|
||||
system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles
|
||||
system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles
|
||||
system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles
|
||||
system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles
|
||||
system.cpu2.icache.tags.replacements 280 # number of replacements
|
||||
system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use
|
||||
system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use
|
||||
system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits
|
||||
|
|
@ -1010,12 +1010,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 366 #
|
|||
system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
|
||||
system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
|
||||
system.cpu2.icache.overall_misses::total 366 # number of overall misses
|
||||
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles
|
||||
system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles
|
||||
system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles
|
||||
system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles
|
||||
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles
|
||||
system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles
|
||||
system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles
|
||||
system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles
|
||||
system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses
|
||||
|
|
@ -1028,12 +1028,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220
|
|||
system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses
|
||||
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses
|
||||
system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses
|
||||
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831 # average ReadReq miss latency
|
||||
system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency
|
||||
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
|
||||
system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_miss_latency::total 14359.256831 # average overall miss latency
|
||||
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency
|
||||
system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency
|
||||
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
|
||||
system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency
|
||||
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1048,32 +1048,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366
|
|||
system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
||||
system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
|
||||
system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
||||
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4513512 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4513512 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses
|
||||
system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses
|
||||
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses
|
||||
system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses
|
||||
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12332 # average ReadReq mshr miss latency
|
||||
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
|
||||
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency
|
||||
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use
|
||||
system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use
|
||||
system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits
|
||||
|
|
@ -1096,16 +1096,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 262 #
|
|||
system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses
|
||||
system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses
|
||||
system.cpu2.dcache.overall_misses::total 262 # number of overall misses
|
||||
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2129481 # number of ReadReq miss cycles
|
||||
system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles
|
||||
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1930500 # number of WriteReq miss cycles
|
||||
system.cpu2.dcache.WriteReq_miss_latency::total 1930500 # number of WriteReq miss cycles
|
||||
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles
|
||||
system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles
|
||||
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles
|
||||
system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles
|
||||
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles
|
||||
system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles
|
||||
system.cpu2.dcache.demand_miss_latency::cpu2.data 4059981 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.demand_miss_latency::total 4059981 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.overall_miss_latency::cpu2.data 4059981 # number of overall miss cycles
|
||||
system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles
|
||||
system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles
|
||||
system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles
|
||||
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -1126,16 +1126,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430
|
|||
system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses
|
||||
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses
|
||||
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421 # average ReadReq miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421 # average ReadReq miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17550 # average WriteReq miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency
|
||||
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency
|
||||
system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency
|
||||
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
|
||||
system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687 # average overall miss latency
|
||||
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
|
||||
system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency
|
||||
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1154,16 +1154,16 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 262
|
|||
system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
|
||||
system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
|
||||
system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1174,16 +1174,16 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430
|
|||
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses
|
||||
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses
|
||||
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency
|
||||
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency
|
||||
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
|
||||
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.numCycles 525588 # number of cpu cycles simulated
|
||||
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
Loading…
Reference in a new issue