2226 lines
257 KiB
Plaintext
2226 lines
257 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.549345 # Number of seconds simulated
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sim_ticks 2549345168000 # Number of ticks simulated
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final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 48945 # Simulator instruction rate (inst/s)
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host_op_rate 62980 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2068782078 # Simulator tick rate (ticks/s)
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host_mem_usage 448444 # Number of bytes of host memory used
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host_seconds 1232.29 # Real time elapsed on the host
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sim_insts 60314699 # Number of instructions simulated
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sim_ops 77609228 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory
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system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15293442 # Number of read requests accepted
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system.physmem.writeReqs 813160 # Number of write requests accepted
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system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 955866 # Per bank write bursts
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system.physmem.perBankRdBursts::1 955512 # Per bank write bursts
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system.physmem.perBankRdBursts::2 954595 # Per bank write bursts
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system.physmem.perBankRdBursts::3 954812 # Per bank write bursts
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system.physmem.perBankRdBursts::4 955762 # Per bank write bursts
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system.physmem.perBankRdBursts::5 955910 # Per bank write bursts
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system.physmem.perBankRdBursts::6 954892 # Per bank write bursts
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system.physmem.perBankRdBursts::7 954654 # Per bank write bursts
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system.physmem.perBankRdBursts::8 956247 # Per bank write bursts
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system.physmem.perBankRdBursts::9 955899 # Per bank write bursts
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system.physmem.perBankRdBursts::10 954311 # Per bank write bursts
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system.physmem.perBankRdBursts::11 954068 # Per bank write bursts
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system.physmem.perBankRdBursts::12 956211 # Per bank write bursts
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system.physmem.perBankRdBursts::13 955980 # Per bank write bursts
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system.physmem.perBankRdBursts::14 955097 # Per bank write bursts
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system.physmem.perBankRdBursts::15 954875 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6687 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6461 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6610 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6631 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6571 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6830 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6820 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6764 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7113 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6879 # Per bank write bursts
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system.physmem.perBankWrBursts::10 6545 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6197 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7141 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6760 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7037 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6911 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2549344036000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 42 # Read request sizes (log2)
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system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 154584 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 754025 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 59135 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 86636 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 11370.889515 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 1019.409545 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 16839.040635 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-71 23447 27.06% 27.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-135 14187 16.38% 43.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-199 2756 3.18% 46.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-263 2051 2.37% 48.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-327 1336 1.54% 50.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-391 1207 1.39% 51.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-455 834 0.96% 52.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-519 1069 1.23% 54.12% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-775 497 0.57% 56.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-839 259 0.30% 56.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-903 256 0.30% 57.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-967 151 0.17% 57.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1031 457 0.53% 57.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1095 109 0.13% 58.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1159 146 0.17% 58.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1287 245 0.28% 58.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1351 63 0.07% 58.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1415 509 0.59% 59.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1543 238 0.27% 59.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1607 21 0.02% 59.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1671 111 0.13% 59.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1735 24 0.03% 59.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1799 197 0.23% 59.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1863 24 0.03% 59.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1927 41 0.05% 60.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2055 375 0.43% 60.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2119 14 0.02% 60.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2247 11 0.01% 60.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2311 279 0.32% 60.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2375 8 0.01% 60.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2439 26 0.03% 60.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2567 24 0.03% 60.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2631 10 0.01% 60.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2695 21 0.02% 60.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2823 158 0.18% 61.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2951 20 0.02% 61.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3015 12 0.01% 61.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3079 221 0.26% 61.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3335 86 0.10% 61.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3399 7 0.01% 61.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3463 12 0.01% 61.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3527 13 0.02% 61.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3591 93 0.11% 61.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3655 7 0.01% 61.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3719 17 0.02% 61.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3783 7 0.01% 61.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3847 145 0.17% 61.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3911 10 0.01% 61.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3975 20 0.02% 62.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4039 16 0.02% 62.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4103 418 0.48% 62.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4295 5 0.01% 62.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4359 16 0.02% 62.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4423 22 0.03% 62.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4487 16 0.02% 62.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4551 10 0.01% 62.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4615 214 0.25% 62.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4679 6 0.01% 62.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4743 10 0.01% 62.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4807 2 0.00% 62.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4871 11 0.01% 62.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4935 11 0.01% 62.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4999 9 0.01% 62.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5063 5 0.01% 62.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5127 326 0.38% 63.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5191 6 0.01% 63.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5319 8 0.01% 63.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5383 81 0.09% 63.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5575 6 0.01% 63.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5639 112 0.13% 63.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5703 3 0.00% 63.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5767 16 0.02% 63.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5831 7 0.01% 63.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6023 12 0.01% 63.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6087 12 0.01% 63.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6151 585 0.68% 64.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6215 5 0.01% 64.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6279 9 0.01% 64.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6407 63 0.07% 64.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6663 9 0.01% 64.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6791 18 0.02% 64.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6855 6 0.01% 64.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6919 188 0.22% 64.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6983 4 0.00% 64.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7111 12 0.01% 64.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7175 264 0.30% 65.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7303 8 0.01% 65.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7367 14 0.02% 65.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7431 15 0.02% 65.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7559 8 0.01% 65.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7623 3 0.00% 65.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7687 139 0.16% 65.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7815 8 0.01% 65.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7943 78 0.09% 65.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8071 7 0.01% 65.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8199 491 0.57% 66.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8448-8455 73 0.08% 66.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8711 137 0.16% 66.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-8967 1 0.00% 66.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9223 257 0.30% 66.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9472-9479 183 0.21% 66.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9735 1 0.00% 66.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-9991 57 0.07% 66.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10247 569 0.66% 67.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10503 64 0.07% 67.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10752-10759 98 0.11% 67.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11008-11015 68 0.08% 67.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11264-11271 311 0.36% 68.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11520-11527 1 0.00% 68.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11783 192 0.22% 68.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11904-11911 1 0.00% 68.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12295 384 0.44% 68.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12551 130 0.15% 69.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12807 71 0.08% 69.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13063 66 0.08% 69.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13319 202 0.23% 69.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13568-13575 137 0.16% 69.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13831 4 0.00% 69.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14087 238 0.27% 69.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14343 326 0.38% 70.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14599 131 0.15% 70.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14855 64 0.07% 70.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15040-15047 1 0.00% 70.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15111 130 0.15% 70.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15367 263 0.30% 70.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15424-15431 1 0.00% 70.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15872-15879 128 0.15% 71.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16000-16007 1 0.00% 71.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16135 62 0.07% 71.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16391 773 0.89% 72.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16647 60 0.07% 72.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16903 129 0.15% 72.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17408-17415 261 0.30% 72.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17671 130 0.15% 72.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17920-17927 64 0.07% 72.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18183 130 0.15% 72.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18688-18695 242 0.28% 73.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18944-18951 2 0.00% 73.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19200-19207 137 0.16% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19264-19271 1 0.00% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19463 198 0.23% 73.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19520-19527 2 0.00% 73.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19584-19591 2 0.00% 73.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19648-19655 1 0.00% 73.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19719 63 0.07% 74.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19968-19975 69 0.08% 74.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20224-20231 129 0.15% 74.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20487 386 0.45% 74.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20864-20871 1 0.00% 74.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20928-20935 1 0.00% 74.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20992-20999 194 0.22% 74.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21376-21383 1 0.00% 74.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21511 312 0.36% 75.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21767 67 0.08% 75.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22023 97 0.11% 75.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22279 65 0.08% 75.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22535 568 0.66% 76.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22784-22791 55 0.06% 76.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22912-22919 2 0.00% 76.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23040-23047 2 0.00% 76.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23296-23303 183 0.21% 76.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23559 257 0.30% 76.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23808-23815 1 0.00% 76.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24064-24071 135 0.16% 76.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24320-24327 73 0.08% 77.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24583 388 0.45% 77.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24832-24839 72 0.08% 77.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24896-24903 2 0.00% 77.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25088-25095 137 0.16% 77.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25351 1 0.00% 77.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25607 257 0.30% 78.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25856-25863 182 0.21% 78.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26048-26055 2 0.00% 78.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26119 1 0.00% 78.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26368-26375 55 0.06% 78.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26631 568 0.66% 78.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26880-26887 64 0.07% 79.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27136-27143 98 0.11% 79.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27399 69 0.08% 79.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27655 312 0.36% 79.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27968-27975 1 0.00% 79.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28160-28167 192 0.22% 79.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28224-28231 1 0.00% 79.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28416-28423 2 0.00% 79.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28544-28551 2 0.00% 79.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28679 387 0.45% 80.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29184-29191 70 0.08% 80.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29440-29447 64 0.07% 80.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29703 199 0.23% 80.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29824-29831 1 0.00% 80.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29952-29959 138 0.16% 80.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30208-30215 2 0.00% 80.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30471 236 0.27% 81.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30727 324 0.37% 81.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30976-30983 131 0.15% 81.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31232-31239 65 0.08% 81.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31495 131 0.15% 81.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31552-31559 1 0.00% 81.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31751 262 0.30% 82.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32519 61 0.07% 82.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32768-32775 772 0.89% 83.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33031 61 0.07% 83.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33287 129 0.15% 83.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33536-33543 2 0.00% 83.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33600-33607 1 0.00% 83.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33664-33671 2 0.00% 83.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33792-33799 262 0.30% 83.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34048-34055 131 0.15% 84.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34304-34311 64 0.07% 84.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34560-34567 131 0.15% 84.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34816-34823 325 0.38% 84.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35072-35079 236 0.27% 84.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35328-35335 2 0.00% 84.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35584-35591 137 0.16% 85.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35840-35847 198 0.23% 85.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36160-36167 1 0.00% 85.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36352-36359 70 0.08% 85.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36608-36615 129 0.15% 85.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36864-36871 384 0.44% 86.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37120-37127 1 0.00% 86.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37376-37383 192 0.22% 86.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37888-37895 312 0.36% 86.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38144-38151 70 0.08% 86.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38400-38407 98 0.11% 86.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38656-38663 64 0.07% 86.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38912-38919 568 0.66% 87.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39168-39175 55 0.06% 87.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39424-39431 1 0.00% 87.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39488-39495 1 0.00% 87.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39680-39687 182 0.21% 87.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40192-40199 1 0.00% 88.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40448-40455 136 0.16% 88.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40704-40711 72 0.08% 88.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40960-40967 387 0.45% 88.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41024-41031 1 0.00% 88.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41216-41223 73 0.08% 88.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41472-41479 135 0.16% 89.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41728-41735 1 0.00% 89.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-41991 257 0.30% 89.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42240-42247 183 0.21% 89.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42752-42759 55 0.06% 89.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43015 569 0.66% 90.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43264-43271 66 0.08% 90.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43520-43527 97 0.11% 90.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43776-43783 68 0.08% 90.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44039 314 0.36% 90.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44160-44167 2 0.00% 90.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44544-44551 196 0.23% 91.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44800-44807 1 0.00% 91.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45056-45063 386 0.45% 91.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45312-45319 132 0.15% 91.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45824-45831 65 0.08% 91.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45888-45895 1 0.00% 91.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46016-46023 3 0.00% 91.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46080-46087 199 0.23% 92.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46336-46343 135 0.16% 92.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46592-46599 1 0.00% 92.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46848-46855 239 0.28% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47040-47047 1 0.00% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47104-47111 324 0.37% 93.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47360-47367 131 0.15% 93.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47616-47623 64 0.07% 93.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47872-47879 131 0.15% 93.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48128-48135 260 0.30% 93.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48640-48647 128 0.15% 93.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48896-48903 61 0.07% 93.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48960-48967 3 0.00% 93.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49159 5274 6.09% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50304-50311 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation
|
|
system.physmem.totQLat 369559391250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 15212838 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 93174 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 158279.45 # Average gap between requests
|
|
system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 54995612 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 16346068 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 16346071 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 763348 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 763348 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 59135 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 131422 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131422 # Transaction distribution
|
|
system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
|
|
system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
|
|
system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 140202797 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
|
system.l2c.tags.replacements 64357 # number of replacements
|
|
system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.074345 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.050564 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000207 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.051046 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.044272 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.785114 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 32950 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 7107 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 506567 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 181823 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 30566 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 6814 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 464544 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 205967 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1436338 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 608494 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 608494 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 58298 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 54682 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 112980 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 32950 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 7107 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 506567 # number of demand (read+write) hits
|
|
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|
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|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 7676 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 73976 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 4707 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 69830 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 156236 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 462156500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 381785750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 290452750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 292088999 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1429809499 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12821282 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 16367635 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 29188917 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4199900099 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4165909168 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 8365809267 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 462156500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 4581685849 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 290452750 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 4457998167 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 9795618766 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 462156500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 4581685849 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 290452750 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 4457998167 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 9795618766 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6012999 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84589545750 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82347341250 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 166942899999 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8959860803 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8414119000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 17373979803 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6012999 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93549406553 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90761460250 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 184316879802 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032489 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021425 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986154 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990315 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.988482 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537930 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.544324 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.541047 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.091600 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.091600 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62516.088096 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64764.744789 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 62038.855339 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.666870 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.055860 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61882.451473 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63776.931537 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62811.563019 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
|
|
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
|
|
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 58478558 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution
|
|
system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
|
|
system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
|
|
system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 148876637 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 48444152 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 123500865 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
|
|
system.cpu0.branchPred.lookups 7183590 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 25676392 # DTB read hits
|
|
system.cpu0.dtb.read_misses 38073 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5871403 # DTB write hits
|
|
system.cpu0.dtb.write_misses 9193 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 25714465 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5880596 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 31547795 # DTB hits
|
|
system.cpu0.dtb.misses 47266 # DTB misses
|
|
system.cpu0.dtb.accesses 31595061 # DTB accesses
|
|
system.cpu0.itb.inst_hits 5793609 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 6965 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses
|
|
system.cpu0.itb.hits 5793609 # DTB hits
|
|
system.cpu0.itb.misses 6965 # DTB misses
|
|
system.cpu0.itb.accesses 5800574 # DTB accesses
|
|
system.cpu0.numCycles 241355643 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked
|
|
system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued
|
|
system.cpu0.iq.rate 0.252625 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 100817 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 5674429 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 6115982 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.248240 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 22754717 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 29270698 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 13537489 # Number of memory references committed
|
|
system.cpu0.commit.loads 7687504 # Number of loads committed
|
|
system.cpu0.commit.membars 203418 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 4891612 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 497791 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 121269057 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 96938789 # The number of ROB writes
|
|
system.cpu0.timesIdled 907351 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 163886679 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 2251360755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 29203197 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 37937631 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 29203197 # Number of Instructions Simulated
|
|
system.cpu0.cpi 8.264699 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 8.264699 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.120997 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.120997 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 271224247 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 42758050 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 22657 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 19930 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 15040337 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 403311 # number of misc regfile writes
|
|
system.cpu0.icache.tags.replacements 984140 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.573239 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 10515740 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 984652 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 10.679651 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 7012159250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 319.827324 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 5233615 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 5282125 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 10515740 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 5233615 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 5282125 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 10515740 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 557933 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 508279 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1066212 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 557933 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 508279 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1066212 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 557933 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 508279 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1066212 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7711361387 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6850959748 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 14562321135 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 7711361387 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 6850959748 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 14562321135 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 7711361387 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 6850959748 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 14562321135 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5791548 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5790404 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 11581952 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 5791548 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 5790404 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 11581952 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 5791548 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 5790404 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 11581952 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096336 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087780 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.092058 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096336 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087780 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.092058 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096336 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087780 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.092058 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.303610 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.738543 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.997786 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13657.997786 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13657.997786 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 6730 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 450 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 431 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.614849 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets 450 # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43117 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38424 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 81541 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 43117 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu1.inst 38424 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 81541 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 43117 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu1.inst 38424 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 81541 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514816 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469855 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 984671 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 514816 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 469855 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 984671 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 514816 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 469855 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 984671 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258274414 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5575421883 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11833696297 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258274414 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5575421883 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11833696297 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258274414 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5575421883 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11833696297 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8426500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8426500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085018 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.085018 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.085018 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.918977 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 644131 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 21534637 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 644643 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 33.405524 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.706394 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.286930 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497473 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502514 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3598843 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 3661860 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 7260703 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114028 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129247 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 243275 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116593 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131076 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247669 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10429044 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 10611511 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 21040555 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10429044 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 10611511 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 21040555 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 324834 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 424795 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 749629 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1512773 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 1450071 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 2962844 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7425 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6132 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 13557 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1837607 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 1874866 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 3712473 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1837607 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 1874866 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 3712473 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5222562191 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6193158591 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 11415720782 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 75296679857 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74371858974 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 149668538831 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106104748 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82161747 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 188266495 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 78000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 80519242048 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 80565017565 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 161084259613 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 80519242048 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 80565017565 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 161084259613 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7155035 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 7374446 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 14529481 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5111616 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5111931 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10223547 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121453 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135379 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 256832 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116595 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131080 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247675 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12266651 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 12486377 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 24753028 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12266651 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 12486377 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 24753028 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045399 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057604 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.051594 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.295948 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.283664 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.289806 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061135 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045295 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052785 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000031 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000024 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.149805 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.150153 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.149981 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.149805 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.150153 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.149981 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16077.634087 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14579.170167 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15228.494071 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49773.944840 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 51288.425859 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50515.160039 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14290.201751 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13398.849804 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13887.032161 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43817.444126 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42971.080368 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 43390.015123 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43817.444126 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42971.080368 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 43390.015123 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 36582 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 25832 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 3477 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.521139 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 88.163823 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 608494 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 608494 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 143520 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219714 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 363234 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1385356 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1328479 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 2713835 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 715 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 651 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1366 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1528876 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1548193 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 3077069 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1528876 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1548193 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 3077069 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181314 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205081 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 386395 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127417 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121592 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 249009 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6710 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5481 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12191 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 308731 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 326673 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 635404 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 308731 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 326673 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 635404 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537114094 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2716244009 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253358103 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5888392200 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5776496365 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11664888565 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84437751 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63633003 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148070754 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8425506294 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8492740374 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 16918246668 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8425506294 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8492740374 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 16918246668 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92381073251 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89949254752 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330328003 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13713085264 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13059234413 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26772319677 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023786 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055248 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040486 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047467 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000024 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13992.929912 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13244.737489 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13595.823194 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46213.552352 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47507.207423 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 7296861 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions.
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 25545961 # DTB read hits
|
|
system.cpu1.dtb.read_misses 37652 # DTB read misses
|
|
system.cpu1.dtb.write_hits 5843070 # DTB write hits
|
|
system.cpu1.dtb.write_misses 9833 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 25583613 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 5852903 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 31389031 # DTB hits
|
|
system.cpu1.dtb.misses 47485 # DTB misses
|
|
system.cpu1.dtb.accesses 31436516 # DTB accesses
|
|
system.cpu1.itb.inst_hits 5792513 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 7242 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses
|
|
system.cpu1.itb.hits 5792513 # DTB hits
|
|
system.cpu1.itb.misses 7242 # DTB misses
|
|
system.cpu1.itb.accesses 5799755 # DTB accesses
|
|
system.cpu1.numCycles 235437063 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued
|
|
system.cpu1.iq.rate 0.263751 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 122647 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 5821795 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 6110780 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.259343 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 24211075 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 31194382 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 13852886 # Number of memory references committed
|
|
system.cpu1.commit.loads 7969478 # Number of loads committed
|
|
system.cpu1.commit.membars 200339 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 5070949 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 493679 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 121392021 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 99804752 # The number of ROB writes
|
|
system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 31111502 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated
|
|
system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|