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regressions: stats update due to decoder changes

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This commit is contained in:
Nilay Vaish 2013-01-04 19:00:48 -06:00
parent e17c375ddd
commit 5ebe3210d8
21 changed files with 1959 additions and 2012 deletions
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6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@ -65,7 +65,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.523500 # Nu
sim_ticks 2523500318000 # Number of ticks simulated
final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54734 # Simulator instruction rate (inst/s)
host_op_rate 70403 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2279341302 # Simulator tick rate (ticks/s)
host_mem_usage 401036 # Number of bytes of host memory used
host_seconds 1107.12 # Real time elapsed on the host
host_inst_rate 64209 # Simulator instruction rate (inst/s)
host_op_rate 82591 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2673913922 # Simulator tick rate (ticks/s)
host_mem_usage 441476 # Number of bytes of host memory used
host_seconds 943.75 # Real time elapsed on the host
sim_insts 60596849 # Number of instructions simulated
sim_ops 77944928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
@ -584,7 +584,7 @@ system.cpu.int_regfile_reads 549353820 # nu
system.cpu.int_regfile_writes 87979072 # number of integer regfile writes
system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads
system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads
system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
system.cpu.icache.replacements 980837 # number of replacements
system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View file

@ -12,6 +12,8 @@ warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here

14
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.593146 # Nu
sim_ticks 2593146078000 # Number of ticks simulated
final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66425 # Simulator instruction rate (inst/s)
host_op_rate 85503 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2731005239 # Simulator tick rate (ticks/s)
host_mem_usage 409388 # Number of bytes of host memory used
host_seconds 949.52 # Real time elapsed on the host
host_inst_rate 77303 # Simulator instruction rate (inst/s)
host_op_rate 99505 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3178225665 # Simulator tick rate (ticks/s)
host_mem_usage 449664 # Number of bytes of host memory used
host_seconds 815.91 # Real time elapsed on the host
sim_insts 63072130 # Number of instructions simulated
sim_ops 81187111 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
@ -1007,7 +1007,7 @@ system.cpu0.int_regfile_reads 175323075 # nu
system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads
system.cpu0.fp_regfile_writes 906 # number of floating regfile writes
system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads
system.cpu0.misc_regfile_reads 13342715 # number of misc regfile reads
system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes
system.cpu0.icache.replacements 399233 # number of replacements
system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use
@ -1577,7 +1577,7 @@ system.cpu1.int_regfile_reads 391481129 # nu
system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes
system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads
system.cpu1.misc_regfile_reads 18962770 # number of misc regfile reads
system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes
system.cpu1.icache.replacements 614989 # number of replacements
system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use

27
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,11 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -64,12 +65,12 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -117,7 +118,6 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -497,23 +497,6 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
View file

@ -11,6 +11,8 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here

336
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.523500 # Nu
sim_ticks 2523500318000 # Number of ticks simulated
final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66325 # Simulator instruction rate (inst/s)
host_op_rate 85314 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2762063576 # Simulator tick rate (ticks/s)
host_mem_usage 400896 # Number of bytes of host memory used
host_seconds 913.63 # Real time elapsed on the host
host_inst_rate 76318 # Simulator instruction rate (inst/s)
host_op_rate 98167 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3178196363 # Simulator tick rate (ticks/s)
host_mem_usage 441472 # Number of bytes of host memory used
host_seconds 794.00 # Real time elapsed on the host
sim_insts 60596849 # Number of instructions simulated
sim_ops 77944928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
@ -539,7 +539,7 @@ system.cpu.int_regfile_reads 549353817 # nu
system.cpu.int_regfile_writes 87979071 # number of integer regfile writes
system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads
system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads
system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
system.cpu.icache.replacements 980837 # number of replacements
system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use
@ -633,6 +633,168 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 643459 # number of replacements
system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
system.cpu.dcache.writebacks::total 607749 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 64388 # number of replacements
system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks.
@ -896,168 +1058,6 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 643459 # number of replacements
system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
system.cpu.dcache.writebacks::total 607749 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.

264
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.164568 # Nu
sim_ticks 164568389500 # Number of ticks simulated
final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 155967 # Simulator instruction rate (inst/s)
host_op_rate 164807 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45026221 # Simulator tick rate (ticks/s)
host_mem_usage 230908 # Number of bytes of host memory used
host_seconds 3654.95 # Real time elapsed on the host
host_inst_rate 195675 # Simulator instruction rate (inst/s)
host_op_rate 206765 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56489453 # Simulator tick rate (ticks/s)
host_mem_usage 277972 # Number of bytes of host memory used
host_seconds 2913.26 # Real time elapsed on the host
sim_insts 570052720 # Number of instructions simulated
sim_ops 602360926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory
@ -502,7 +502,7 @@ system.cpu.ipc_total 1.731963 # IP
system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads
system.cpu.int_regfile_writes 663044095 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 901644614 # number of misc regfile reads
system.cpu.misc_regfile_reads 234776328 # number of misc regfile reads
system.cpu.misc_regfile_writes 3110 # number of misc regfile writes
system.cpu.icache.replacements 60 # number of replacements
system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use
@ -588,6 +588,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440681 # number of replacements
system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use
system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits
system.cpu.dcache.overall_hits::total 197562725 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses
system.cpu.dcache.overall_misses::total 3714801 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159651000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5159651000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250551202 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 45410202202 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 45410202202 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 45410202202 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 45410202202 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.948944 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.948944 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.924972 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12224.127807 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12224.127807 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks
system.cpu.dcache.writebacks::total 421636 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2559 # number of replacements
system.cpu.l2cache.tagsinuse 22365.188889 # Cycle average of tags in use
system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks.
@ -735,131 +861,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440681 # number of replacements
system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use
system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits
system.cpu.dcache.overall_hits::total 197562725 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses
system.cpu.dcache.overall_misses::total 3714801 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159651000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5159651000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250551202 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 45410202202 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 45410202202 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 45410202202 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 45410202202 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.948944 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.948944 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.924972 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12224.127807 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12224.127807 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks
system.cpu.dcache.writebacks::total 421636 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

24
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -78,7 +78,6 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -458,23 +457,6 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -536,9 +518,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

264
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026786 # Nu
sim_ticks 26786364500 # Number of ticks simulated
final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 151377 # Simulator instruction rate (inst/s)
host_op_rate 152464 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44755705 # Simulator tick rate (ticks/s)
host_mem_usage 363280 # Number of bytes of host memory used
host_seconds 598.50 # Real time elapsed on the host
host_inst_rate 184396 # Simulator instruction rate (inst/s)
host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54518089 # Simulator tick rate (ticks/s)
host_mem_usage 410024 # Number of bytes of host memory used
host_seconds 491.33 # Real time elapsed on the host
sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
@ -496,7 +496,7 @@ system.cpu.int_regfile_reads 495578845 # nu
system.cpu.int_regfile_writes 120555497 # number of integer regfile writes
system.cpu.fp_regfile_reads 176 # number of floating regfile reads
system.cpu.fp_regfile_writes 427 # number of floating regfile writes
system.cpu.misc_regfile_reads 181219036 # number of misc regfile reads
system.cpu.misc_regfile_reads 29099412 # number of misc regfile reads
system.cpu.misc_regfile_writes 11608 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use
@ -582,6 +582,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943495 # number of replacements
system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
system.cpu.dcache.writebacks::total 942892 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks.
@ -743,131 +869,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943495 # number of replacements
system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
system.cpu.dcache.writebacks::total 942892 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1392
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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264
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 0.068267 # Nu
sim_ticks 68267465500 # Number of ticks simulated
final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 130031 # Simulator instruction rate (inst/s)
host_op_rate 166236 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32510221 # Simulator tick rate (ticks/s)
host_mem_usage 238756 # Number of bytes of host memory used
host_seconds 2099.88 # Real time elapsed on the host
host_inst_rate 160764 # Simulator instruction rate (inst/s)
host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40194170 # Simulator tick rate (ticks/s)
host_mem_usage 285344 # Number of bytes of host memory used
host_seconds 1698.44 # Real time elapsed on the host
sim_insts 273048375 # Number of instructions simulated
sim_ops 349076099 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
@ -496,7 +496,7 @@ system.cpu.int_regfile_reads 1769305779 # nu
system.cpu.int_regfile_writes 232713829 # number of integer regfile writes
system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads
system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes
system.cpu.misc_regfile_reads 973808735 # number of misc regfile reads
system.cpu.misc_regfile_reads 567370356 # number of misc regfile reads
system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes
system.cpu.icache.replacements 13908 # number of replacements
system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use
@ -582,6 +582,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1414 # number of replacements
system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
system.cpu.dcache.overall_misses::total 25149 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
system.cpu.dcache.writebacks::total 1040 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
@ -727,131 +853,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1414 # number of replacements
system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
system.cpu.dcache.overall_misses::total 25149 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
system.cpu.dcache.writebacks::total 1040 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

264
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.624868 # Nu
sim_ticks 624867585500 # Number of ticks simulated
final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 92987 # Simulator instruction rate (inst/s)
host_op_rate 126636 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41971725 # Simulator tick rate (ticks/s)
host_mem_usage 253512 # Number of bytes of host memory used
host_seconds 14887.82 # Real time elapsed on the host
host_inst_rate 118271 # Simulator instruction rate (inst/s)
host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53384157 # Simulator tick rate (ticks/s)
host_mem_usage 298364 # Number of bytes of host memory used
host_seconds 11705.11 # Real time elapsed on the host
sim_insts 1384379060 # Number of instructions simulated
sim_ops 1885333812 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
@ -502,7 +502,7 @@ system.cpu.int_regfile_reads 11770471325 # nu
system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes
system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads
system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes
system.cpu.misc_regfile_reads 3658188004 # number of misc regfile reads
system.cpu.misc_regfile_reads 1363964167 # number of misc regfile reads
system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes
system.cpu.icache.replacements 22546 # number of replacements
system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use
@ -588,6 +588,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1532987 # number of replacements
system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
system.cpu.dcache.writebacks::total 96322 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 442193 # number of replacements
system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks.
@ -751,131 +877,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1532987 # number of replacements
system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
system.cpu.dcache.writebacks::total 96322 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

264
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026292 # Nu
sim_ticks 26292466000 # Number of ticks simulated
final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 115195 # Simulator instruction rate (inst/s)
host_op_rate 163465 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42703788 # Simulator tick rate (ticks/s)
host_mem_usage 260928 # Number of bytes of host memory used
host_seconds 615.69 # Real time elapsed on the host
host_inst_rate 139577 # Simulator instruction rate (inst/s)
host_op_rate 198063 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51742306 # Simulator tick rate (ticks/s)
host_mem_usage 305460 # Number of bytes of host memory used
host_seconds 508.14 # Real time elapsed on the host
sim_insts 70925094 # Number of instructions simulated
sim_ops 100644341 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory
@ -503,7 +503,7 @@ system.cpu.int_regfile_reads 511431338 # nu
system.cpu.int_regfile_writes 103318196 # number of integer regfile writes
system.cpu.fp_regfile_reads 686 # number of floating regfile reads
system.cpu.fp_regfile_writes 582 # number of floating regfile writes
system.cpu.misc_regfile_reads 143076838 # number of misc regfile reads
system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads
system.cpu.misc_regfile_writes 38826 # number of misc regfile writes
system.cpu.icache.replacements 30543 # number of replacements
system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use
@ -589,6 +589,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 158306 # number of replacements
system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
system.cpu.dcache.writebacks::total 129052 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 95650 # number of replacements
system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use
system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks.
@ -756,131 +882,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 158306 # number of replacements
system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
system.cpu.dcache.writebacks::total 129052 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

264
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.506343 # Nu
sim_ticks 506342716000 # Number of ticks simulated
final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 134396 # Simulator instruction rate (inst/s)
host_op_rate 149928 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44057957 # Simulator tick rate (ticks/s)
host_mem_usage 522896 # Number of bytes of host memory used
host_seconds 11492.65 # Real time elapsed on the host
host_inst_rate 168217 # Simulator instruction rate (inst/s)
host_op_rate 187658 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55145312 # Simulator tick rate (ticks/s)
host_mem_usage 540496 # Number of bytes of host memory used
host_seconds 9181.97 # Real time elapsed on the host
sim_insts 1544563043 # Number of instructions simulated
sim_ops 1723073855 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory
@ -502,7 +502,7 @@ system.cpu.int_regfile_reads 9949187154 # nu
system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes
system.cpu.fp_regfile_reads 155 # number of floating regfile reads
system.cpu.fp_regfile_writes 154 # number of floating regfile writes
system.cpu.misc_regfile_reads 2914618242 # number of misc regfile reads
system.cpu.misc_regfile_reads 737521382 # number of misc regfile reads
system.cpu.misc_regfile_writes 132 # number of misc regfile writes
system.cpu.icache.replacements 22 # number of replacements
system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use
@ -588,6 +588,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53966.451613
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9598051 # number of replacements
system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use
system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits
system.cpu.dcache.overall_hits::total 655966804 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses
system.cpu.dcache.overall_misses::total 17011338 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks
system.cpu.dcache.writebacks::total 3781955 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2214170 # number of replacements
system.cpu.l2cache.tagsinuse 31523.647608 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9246689 # Total number of references to valid blocks.
@ -735,131 +861,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41941.935657
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9598051 # number of replacements
system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use
system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits
system.cpu.dcache.overall_hits::total 655966804 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses
system.cpu.dcache.overall_misses::total 17011338 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks
system.cpu.dcache.writebacks::total 3781955 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

264
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.074245 # Nu
sim_ticks 74245032000 # Number of ticks simulated
final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 109443 # Simulator instruction rate (inst/s)
host_op_rate 119829 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47150577 # Simulator tick rate (ticks/s)
host_mem_usage 234068 # Number of bytes of host memory used
host_seconds 1574.64 # Real time elapsed on the host
host_inst_rate 131550 # Simulator instruction rate (inst/s)
host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56674428 # Simulator tick rate (ticks/s)
host_mem_usage 280244 # Number of bytes of host memory used
host_seconds 1310.03 # Real time elapsed on the host
sim_insts 172333441 # Number of instructions simulated
sim_ops 188686923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory
@ -497,7 +497,7 @@ system.cpu.int_regfile_reads 1079711901 # nu
system.cpu.int_regfile_writes 384939818 # number of integer regfile writes
system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads
system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes
system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads
system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads
system.cpu.misc_regfile_writes 832204 # number of misc regfile writes
system.cpu.icache.replacements 2508 # number of replacements
system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
@ -583,6 +583,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 57 # number of replacements
system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
system.cpu.dcache.overall_misses::total 9552 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks.
@ -742,131 +868,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 57 # number of replacements
system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
system.cpu.dcache.overall_misses::total 9552 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

10
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
View file

@ -4,10 +4,10 @@ sim_seconds 0.000013 # Nu
sim_ticks 13371000 # Number of ticks simulated
final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 32660 # Simulator instruction rate (inst/s)
host_op_rate 40743 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 94998008 # Simulator tick rate (ticks/s)
host_mem_usage 228356 # Number of bytes of host memory used
host_inst_rate 32987 # Simulator instruction rate (inst/s)
host_op_rate 41149 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 95942804 # Simulator tick rate (ticks/s)
host_mem_usage 272856 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
@ -537,7 +537,7 @@ system.cpu.ipc_total 0.171858 # IP
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 15007 # number of misc regfile reads
system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use

22
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
View file

@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -78,7 +78,6 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -458,23 +457,6 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -536,7 +518,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

258
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,10 +4,10 @@ sim_seconds 0.000013 # Nu
sim_ticks 13371000 # Number of ticks simulated
final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 37264 # Simulator instruction rate (inst/s)
host_op_rate 46486 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 108387516 # Simulator tick rate (ticks/s)
host_mem_usage 228452 # Number of bytes of host memory used
host_inst_rate 36978 # Simulator instruction rate (inst/s)
host_op_rate 46127 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 107546339 # Simulator tick rate (ticks/s)
host_mem_usage 272728 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
@ -492,7 +492,7 @@ system.cpu.ipc_total 0.171858 # IP
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 15007 # number of misc regfile reads
system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
@ -578,6 +578,130 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
system.cpu.dcache.overall_hits::total 2371 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
system.cpu.dcache.overall_misses::total 498 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
@ -712,129 +836,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
system.cpu.dcache.overall_hits::total 2371 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
system.cpu.dcache.overall_misses::total 498 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

2
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
View file

@ -463,7 +463,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864

16
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000105 # Nu
sim_ticks 104830500 # Number of ticks simulated
final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 100032 # Simulator instruction rate (inst/s)
host_op_rate 100032 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10132772 # Simulator tick rate (ticks/s)
host_mem_usage 236868 # Number of bytes of host memory used
host_seconds 10.35 # Real time elapsed on the host
host_inst_rate 112424 # Simulator instruction rate (inst/s)
host_op_rate 112424 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11388036 # Simulator tick rate (ticks/s)
host_mem_usage 275264 # Number of bytes of host memory used
host_seconds 9.21 # Real time elapsed on the host
sim_insts 1034897 # Number of instructions simulated
sim_ops 1034897 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
@ -952,7 +952,7 @@ system.cpu1.int_regfile_reads 422509 # nu
system.cpu1.int_regfile_writes 197149 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.replacements 317 # number of replacements
system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use
system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks.
@ -1426,7 +1426,7 @@ system.cpu2.int_regfile_reads 319017 # nu
system.cpu2.int_regfile_writes 150022 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads
system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.replacements 319 # number of replacements
system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use
system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks.
@ -1900,7 +1900,7 @@ system.cpu3.int_regfile_reads 427031 # nu
system.cpu3.int_regfile_writes 198982 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads
system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.icache.replacements 318 # number of replacements
system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use
system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks.