Decoder: Remove the thread context get/set from the decoder.
This interface is no longer used, and getting rid of it simplifies the decoders and code that sets up the decoders. The thread context had been used to read architectural state which was used to contextualize the instruction memory as it came in. That was changed so that the state is now sent to the decoders to keep locally if/when it changes. That's significantly more efficient. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
parent
d1965af220
commit
e17c375ddd
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@ -36,36 +36,20 @@
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#include "cpu/static_inst.hh"
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#include "sim/full_system.hh"
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class ThreadContext;
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namespace AlphaISA
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{
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class Decoder
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{
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protected:
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ThreadContext *tc;
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// The extended machine instruction being generated
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ExtMachInst ext_inst;
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bool instDone;
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public:
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Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
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Decoder() : instDone(false)
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{}
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ThreadContext *
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getTC()
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{
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return tc;
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}
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void
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setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void
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process()
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{ }
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@ -32,7 +32,6 @@
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/utility.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Decoder.hh"
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namespace ArmISA
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@ -39,15 +39,12 @@
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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class ThreadContext;
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namespace ArmISA
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{
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class Decoder
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{
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protected:
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ThreadContext * tc;
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//The extended machine instruction being generated
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ExtMachInst emi;
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MachInst data;
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@ -72,23 +69,11 @@ class Decoder
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foundIt = false;
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}
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Decoder(ThreadContext * _tc) : tc(_tc), data(0),
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fpscrLen(0), fpscrStride(0)
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Decoder() : data(0), fpscrLen(0), fpscrStride(0)
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{
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reset();
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}
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ThreadContext * getTC()
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{
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return tc;
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}
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void
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setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void process();
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//Use this to give data to the decoder. This should be used
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@ -381,7 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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fpscrMask.n = ones;
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newVal = (newVal & (uint32_t)fpscrMask) |
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(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
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tc->getDecodePtr()->setContext(newVal);
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tc->getDecoderPtr()->setContext(newVal);
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}
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break;
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case MISCREG_CPSR_Q:
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@ -37,34 +37,20 @@
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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class ThreadContext;
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namespace MipsISA
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{
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class Decoder
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{
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protected:
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ThreadContext * tc;
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//The extended machine instruction being generated
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ExtMachInst emi;
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bool instDone;
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public:
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Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
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Decoder() : instDone(false)
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{}
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ThreadContext *getTC()
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{
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return tc;
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}
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void
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setTC(ThreadContext *_tc)
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{
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tc = _tc;
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}
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void
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process()
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{
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@ -35,37 +35,21 @@
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#include "arch/types.hh"
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#include "cpu/static_inst.hh"
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class ThreadContext;
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namespace PowerISA
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{
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class Decoder
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{
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protected:
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ThreadContext * tc;
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// The extended machine instruction being generated
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ExtMachInst emi;
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bool instDone;
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public:
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Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
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Decoder() : instDone(false)
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{
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}
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ThreadContext *
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getTC()
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{
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return tc;
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}
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void
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setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void
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process()
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{
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@ -35,9 +35,6 @@
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#include "arch/sparc/registers.hh"
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#include "arch/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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class ThreadContext;
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namespace SparcISA
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{
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@ -45,28 +42,15 @@ namespace SparcISA
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class Decoder
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{
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protected:
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ThreadContext * tc;
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// The extended machine instruction being generated
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ExtMachInst emi;
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bool instDone;
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MiscReg asi;
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public:
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Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
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Decoder() : instDone(false), asi(0)
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{}
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ThreadContext *
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getTC()
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{
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return tc;
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}
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void
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setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void process() {}
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void
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@ -29,6 +29,7 @@
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*/
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/decoder.hh"
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#include "arch/sparc/isa.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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@ -550,7 +551,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
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switch (miscReg) {
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case MISCREG_ASI:
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tc->getDecodePtr()->setContext(val);
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tc->getDecoderPtr()->setContext(val);
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break;
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case MISCREG_STICK:
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case MISCREG_TICK:
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@ -33,7 +33,6 @@
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Decoder.hh"
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namespace X86ISA
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@ -44,8 +44,6 @@
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#include "cpu/static_inst.hh"
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#include "debug/Decoder.hh"
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class ThreadContext;
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namespace X86ISA
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{
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@ -72,7 +70,6 @@ class Decoder
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static InstBytes dummy;
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ThreadContext * tc;
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//The bytes to be predecoded
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MachInst fetchChunk;
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InstBytes *instBytes;
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@ -205,8 +202,7 @@ class Decoder
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static InstCacheMap instCacheMap;
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public:
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Decoder(ThreadContext * _tc) :
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tc(_tc), basePC(0), origPC(0), offset(0),
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Decoder() : basePC(0), origPC(0), offset(0),
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outOfBytes(true), instDone(false),
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state(ResetState)
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{
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@ -259,16 +255,6 @@ class Decoder
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state = ResetState;
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}
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ThreadContext * getTC()
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{
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return tc;
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}
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void setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void process();
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//Use this to give data to the decoder. This should be used
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@ -306,7 +306,6 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
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StaticInstPtr instPtr = NULL;
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//Predecode, ie bundle up an ExtMachInst
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thread->decoder.setTC(thread->getTC());
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//If more fetch data is needed, pass it in.
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Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
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thread->decoder.moreBytes(pcState, fetchPC, machInst);
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@ -59,7 +59,7 @@ FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
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instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
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{
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for (int tid = 0; tid < MaxThreads; tid++)
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decoder[tid] = new Decoder(NULL);
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decoder[tid] = new Decoder;
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}
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FetchUnit::~FetchUnit()
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MachInst mach_inst =
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TheISA::gtoh(fetchInsts[fetch_offset]);
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decoder[tid]->setTC(cpu->thread[tid]->getTC());
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decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
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assert(decoder[tid]->instReady());
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inst->setStaticInst(decoder[tid]->decode(instPC));
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@ -422,7 +422,6 @@ Trace::LegionTraceRecord::dump()
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<< endl;
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TheISA::Decoder *decoder = thread->getDecoderPtr();
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decoder->setTC(thread);
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decoder->moreBytes(m5Pc, m5Pc, shared_data->instruction);
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assert(decoder->instReady());
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@ -134,7 +134,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
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for (int i = 0; i < Impl::MaxThreads; i++) {
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cacheData[i] = NULL;
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decoder[i] = new TheISA::Decoder(NULL);
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decoder[i] = new TheISA::Decoder;
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}
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}
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@ -1225,9 +1225,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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if (blkOffset >= numInsts)
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break;
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}
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MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
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decoder[tid]->setTC(cpu->thread[tid]->getTC());
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MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
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decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
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if (decoder[tid]->needMoreBytes()) {
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@ -380,8 +380,6 @@ BaseSimpleCPU::preExecute()
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TheISA::Decoder *decoder = &(thread->decoder);
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//Predecode, ie bundle up an ExtMachInst
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//This should go away once the constructor can be set up properly
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decoder->setTC(thread->getTC());
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//If more fetch data is needed, pass it in.
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Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
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//if(decoder->needMoreBytes())
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@ -63,16 +63,16 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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Process *_process, TheISA::TLB *_itb,
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TheISA::TLB *_dtb)
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: ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb),
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dtb(_dtb), decoder(NULL)
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dtb(_dtb)
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{
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clearArchRegs();
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tc = new ProxyThreadContext<SimpleThread>(this);
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}
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SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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TheISA::TLB *_itb, TheISA::TLB *_dtb,
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bool use_kernel_stats)
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: ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb),
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decoder(NULL)
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: ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb)
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{
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tc = new ProxyThreadContext<SimpleThread>(this);
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}
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SimpleThread::SimpleThread()
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: ThreadState(NULL, -1, NULL), decoder(NULL)
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: ThreadState(NULL, -1, NULL)
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{
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tc = new ProxyThreadContext<SimpleThread>(this);
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}
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