arch/mips/isa/decoder.isa:
arch/mips/isa_traits.hh:
sim/syscall_emul.cc:
make syscall instruction functional
arch/mips/linux_process.cc:
add all MIPS/Linux syscalls to descriptor list
--HG--
extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
Hand merged
--HG--
extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
put back in Tcc code that was deleted in last merge
arch/sparc/isa/bitfields.isa:
clean up condition codes a little bit
--HG--
extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 02fe0b0170348dc6f6a985c15123806088a8c23e
before getting in a infinite loop. It actually "tries" to syscall too, but syscalls
aren't implemented just yet
arch/mips/faults.cc:
more descriptive names for faults (will help future users as well as me!)
arch/mips/isa/base.isa:
make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest
arch/mips/isa/decoder.isa:
FIX LW/SW Bug!!!! I was actually loading a byte instead of a word
FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction
FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly
base/loader/elf_object.cc:
change back to original way
base/loader/elf_object.hh:
change back to original!
--HG--
extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
arch/alpha/types.hh:
Moved the DependenceTags enum from types to constants.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Corrected a misspelling of PriviledgeOpcode and PrivilegedAction.
arch/sparc/isa/formats.isa:
Fixups towards compiling. Added a few additional instruction formats.
--HG--
extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
arch/sparc/isa/bitfields.isa:
the trap field is 7:0
arch/sparc/isa/decoder.isa:
add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
We need the syscall num register
--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
arch/mips/isa/formats/branch.isa:
let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
add copyRegs function ...
comment out serialize float code for now
arch/mips/isa_traits.hh:
make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
change MIPS to Mips
base/loader/elf_object.cc:
get global pointer initialized to a value
base/loader/elf_object.hh:
Add global_ptr to elf_object constructor
base/loader/object_file.hh:
MIPS to Mips
base/traceflags.py:
SimpleCPU trace flag
cpu/simple/cpu.cc:
DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
Add Decoder functions to static_inst.hh
--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
SConscript:
Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
change MIPS constant to 34k
arch/mips/isa/decoder.isa:
Allow sll,ssnop,nop, and ehb to be determined through decoder using
the different types of default cases
arch/mips/isa/formats/branch.isa:
Delete debug code
arch/mips/isa/formats/noop.isa:
add a Nop format
arch/mips/isa_traits.hh:
use constants instead of enums
arch/mips/process.cc:
point to the correct header file
cpu/simple/cpu.cc:
Output the actual fault name
sim/process.cc:
Inititalize NNPC
--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
arch/alpha/utility.hh:
Got rid of unnecessary extern and static qualifiers, and fixed up the hand merge.
arch/sparc/regfile.hh:
Fixed up SPARC after a hand merge.
--HG--
extra : convert_revision : 56e2d90ddd144f3386dbea50fa96cfc461d46b81
arch/alpha/arguments.cc:
Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
Replaced setFloatRegDouble with setFloatReg
--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
arch/alpha/ev5.cc:
copyIprs now copies from a source ExecContext to a destination ExecContext.
arch/alpha/registerfile.hh:
Have ISA specific functions to copy all architected registers from one ExecContext to another.
cpu/cpu_exec_context.cc:
Call the ISA in order to copy any architected registers.
--HG--
extra : convert_revision : 056cc3b3a9f345535d5a57c6524b114bbd5ae3c8
arch/alpha/process.cc:
arch/mips/process.cc:
arch/sparc/process.cc:
You really do need the headers in the .cc file.
arch/alpha/process.hh:
Don't include unnecessary headers in another header.
Replace with forward class declarations.
arch/mips/process.hh:
arch/sparc/process.hh:
Don't include unnecessary headers in another header.
Replace with forward class declarations.
Also fix std namespace... no "using" in header files!
--HG--
extra : convert_revision : f2cd953d0f4a212bb8148cc54c329aa3c18deb89
arch/alpha/isa_traits.hh:
No unprotected "using" in header files.
cpu/simple/cpu.cc:
Fix ISA namespace "using" statement.
--HG--
extra : convert_revision : 317ea40f8de00748d7613a0116edab05770bdc72
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
extra : convert_revision : b101fa550567d5a9f5de6c2d8c3f67829ae050c1
arch/alpha/isa_traits.hh:
used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
so other archs. can use SimpleCPU
arch/mips/SConscript:
dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
Change Faults to new format
arch/mips/isa/decoder.isa:
Fix readMiscReg access
Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
create copyMiscRegs function...
delete useless code
arch/mips/isa_traits.hh:
clean up for build
arch/mips/linux_process.cc:
mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
new argument for linux process
arch/mips/process.cc:
add system
arch/mips/process.hh:
add system variable
cpu/cpu_exec_context.cc:
Change AlphaISA to TheISA
cpu/exec_context.hh:
add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
include isa_traits for namespace declariation
cpu/simple/cpu.hh:
PC & NPC access/modify functions
arch/mips/utility.hh:
file needed for compile
--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
an obsolete function that doesn't exist.
arch/alpha/tru64/process.cc:
sim/process.cc:
Don't include useless header.
--HG--
extra : convert_revision : 1dd5edeb0703e2190b89ea5ff563df4c95b7cf59
arch/SConscript:
Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh.
arch/alpha/isa_traits.hh:
Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore.
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
cpu/pc_event.hh:
cpu/static_inst.hh:
mem/port.hh:
sim/faults.cc:
sim/system.hh:
base/misc.hh isn't included through isa_traits.hh anymore.
cpu/simple/cpu.cc:
Added include for arch/utility.hh
--HG--
extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
arch/alpha/isa_traits.hh:
Moved constants from isa_traits.hh into constants.hh. Also removed the dependence on ev5.hh
--HG--
extra : convert_revision : f7a03c4ffb1394dcca5a5a96da468c3ff14e1974
Fixed the exec context proxy class to have a getMemPort function.
arch/alpha/linux/process.cc:
arch/alpha/tru64/process.cc:
kern/tru64/tru64.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Fix to use new exec context proxy
--HG--
extra : convert_revision : eaa05dfab3fdb77627f6cf404a2569a44232f604
arch/alpha/isa_traits.hh:
Pulled out basic type definitions into types.hh
arch/alpha/types.hh:
New BitKeeper file ``arch/alpha/types.hh''
For relatively basic types associated with an architecture. This does not include, for instance, register files.
--HG--
extra : convert_revision : ee6c4afc115271ad237208274c863a7dee97c5d7
arch/alpha/isa_traits.hh:
arch/sparc/linux/process.cc:
fix merging problem
sim/syscall_emul.cc:
use setIntReg
--HG--
extra : convert_revision : e88d72e415493cd17d7b88c22c7e995f3199e396
check abi-tag note section of elf binary for OS
add pseudo functions (moved from alpha and made to be generic)
move setsyscallreturn into isa traits
arch/alpha/SConscript:
no more common syscall emulation, now common for everyone
arch/alpha/isa_traits.hh:
move setsyscallreturn into isa description
arch/alpha/linux/process.cc:
arch/alpha/tru64/process.cc:
use generic functions rather than alpha specific ones
arch/sparc/isa_traits.hh:
have consts for generic pseudo syscalls
arch/sparc/linux/process.cc:
use generic functions
base/loader/elf_object.cc:
check abi-tag note section of elf binary for OS
cpu/exec_context.hh:
move syssyscallreturn into isa traits
sim/process.cc:
find call num with a more generic
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add pseudo functions (moved from alpha and made to be generic)
--HG--
extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
set NNPC function
cpu/simple/cpu.cc:
use NNPC in determining what PC we are using
--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
arch/alpha/ev5.cc:
Include function for the MiscRegFile to copy all of the Iprs from an ExecContext.
arch/alpha/isa_traits.hh:
Include functions to copy MiscRegs from an ExecContext.
cpu/cpu_exec_context.cc:
Be sure to copy all of the misc regs when copying all architectural state.
--HG--
extra : convert_revision : cb948b5ff141ea0f739a1016f98236bd2a512f76
arch/alpha/isa_traits.hh:
Changed the enums to const ints, and got rid of a few unnecessary constants.
arch/sparc/isa_traits.hh:
Got rid of the enums, and added in some missing constants.
--HG--
extra : convert_revision : ee47890af9d8c67300b31d8e0dda1d580bd21479
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
Also several files need to include system.hh or symtab.hh. This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well.
arch/alpha/faults.cc:
Avoid accessing XC directly.
arch/alpha/stacktrace.cc:
StackTrace needs to include system.hh.
cpu/cpu_exec_context.cc:
Update for change to CPUExecContext.
cpu/cpu_exec_context.hh:
Make quiesce events use CPUExecContext instead of ExecContext. Include functions to allow the quiesce event and last activate/suspend be accessed.
cpu/exec_context.hh:
Include functions for quiesceEvent.
cpu/intr_control.cc:
Needs to include cpu/exec_context.hh.
cpu/profile.cc:
Needs to include symtab.hh for the symbol table.
cpu/profile.hh:
Needs forward declare of ExecContext.
cpu/simple/cpu.cc:
Rename xc to cpuXC.
dev/tsunami_cchip.cc:
Needs to include exec_context.hh.
kern/kernel_stats.cc:
Needs to include system.hh.
kern/linux/events.cc:
Needs to include system.hh.
Also avoid accessing objects directly from the XC.
kern/tru64/dump_mbuf.cc:
Include symtab.hh for the SymbolTable and system.hh.
kern/tru64/tru64_events.cc:
Include system.hh
sim/pseudo_inst.cc:
Avoid accessing objects directly within the XC.
--HG--
extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
arch/sparc/stacktrace.hh:
- Change the StackTrace code so that the class can more easily be
cleaned out and reused to avoid extra allocations.
- Allow trace() to accept a static instruction pointer so it can
determine if the instruction is worth tracing. This is moved from
the CPU.
- provide constants for special meaning PCs (user, console, unknown),
instead of magic numbers
arch/sparc/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/sparc/stacktrace.hh:
Made Addr a global type
arch/sparc/stacktrace.hh:
bk cp ../alpha/stacktrace.hh stacktrace.hh
--HG--
extra : convert_revision : 8fd15e5ec8d676d081380b21886234561c5f3678
arch/SConscript:
ev5 should now be contained within alpha specific code.
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed.
arch/sparc/isa_traits.hh:
Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes.
cpu/o3/alpha_cpu.hh:
Added typedefs which are required now that there isn't a using namespace EV5.
cpu/o3/alpha_cpu_impl.hh:
Some small changes so that ev5.hh isn't needed directly.
cpu/o3/cpu.hh:
Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile.
cpu/o3/regfile.hh:
Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array.
--HG--
extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd
arch/SConscript:
aout_machdep.h and ecoff_machdep.h are no longer bridging headers, since support of these formats is limitted to alpha.
base/loader/exec_aout.h:
Include the alpha specific version of aout_machdep.h, since only the alpha version of aout will be supported for now.
base/loader/exec_ecoff.h:
Include the alpha specific version of ecoff_machdep.h, since only the alpha version of ecoff will be supported for now.
--HG--
extra : convert_revision : 15328aae54538c26d2c10d7476501e0daa3d22d0
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Implemented the SPARC fault classes. The invoke method still needs to be written, but this depends on the misc regfile.
--HG--
extra : convert_revision : bc9d2785600cee5ea1cba72e563ca5d1a20f37fd
arch/alpha/faults.cc:
Renamed the _stat stat to a more descriptive _count, got rid of some old commented out code, and moved common fault handling code, ie recording that the fault happend and that it wasn't mispeculated, into the FaultBase class.
arch/alpha/faults.hh:
Renamed the _stat stat to the more descriptive _count, and renamed the appropriate accessor functions.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
The fault statistics are now handled by the fault classes themselves.
sim/faults.cc:
The default implementation of the "invoke" method now does what all faults should do first, ie record that the fault happened, and make sure the fault isn't being executed on a mispeculated execution path.
sim/faults.hh:
There is now a default implementation of invoke, and the stat function is taken care of in the architecture specific fault classes.
--HG--
extra : convert_revision : f6656fbea991df9addf85cad740ac37b1036b71a
arch/sparc/faults.cc:
Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/sparc/faults.hh:
Fix to have normal m5 line length limit, change pointers to const pointers.
arch/sparc/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/sparc/faults.hh:
ur
Using cleaned up fault class deiffinitions
arch/sparc/faults.hh:
Added typedef for Addr
arch/sparc/faults.hh:
Made Addr a global type
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Changed Fault to be a RefCountingPtr
arch/sparc/faults.cc:
arch/sparc/faults.hh:
MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Put the Alpha faults into the AlphaISA namespace
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context.
arch/sparc/faults.cc:
AlphaFault is now an abstract class.
arch/sparc/faults.hh:
AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
moved ev5_trap fully into the fault class.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Changed the name of the fault's invocation method from ev5_trap to invoke.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults.
arch/sparc/faults.cc:
bk cp ../alpha/faults.cc faults.cc
arch/sparc/faults.hh:
bk cp ../alpha/faults.hh faults.hh
SConscript:
Moved the alpha specific source files into the alpha specific SConscript
arch/alpha/SConscript:
Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders.
arch/alpha/linux/process.cc:
arch/alpha/process.hh:
arch/sparc/process.hh:
arch/alpha/tru64/process.cc:
Changed the include paths to use the new os specific directories.
--HG--
rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh
rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc
rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh
extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
into ewok.(none):/home/gblack/m5/multiarch
arch/alpha/system.cc:
Hand merged
--HG--
extra : convert_revision : 34d7608d21dc6dee3a3feed5e5671f5de6ebfa26
The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext).
Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out.
Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers.
SConscript:
Include new file, cpu_exec_context.cc.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/stacktrace.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
cpu/intr_control.cc:
Avoid directly accessing objects within the XC.
arch/alpha/ev5.cc:
Avoid directly accessing objects within the XC.
KernelStats have been moved to the BaseCPU instead of the XC.
arch/alpha/isa_traits.hh:
Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext.
cpu/base.cc:
Place kernel stats within the BaseCPU instead of the ExecContext.
For now comment out the profiling code sampling until its exact location is decided upon.
cpu/base.hh:
Kernel stats are now in the BaseCPU instead of the ExecContext.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details.
cpu/exetrace.cc:
Remove unneeded include of exec_context.hh.
cpu/intr_control.hh:
cpu/o3/alpha_cpu_builder.cc:
Remove unneeded include of exec_context.hh
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details.
Also avoid accessing anything directly from the XC.
cpu/pc_event.cc:
Avoid accessing objects directly from the XC.
dev/tsunami_cchip.cc:
Avoid accessing objects directly within the XC>
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/linux/linux_threadinfo.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Avoid accessing objects directly within the XC.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
Kernel stats no longer exist within the XC.
kern/system_events.cc:
Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU.
sim/process.cc:
sim/process.hh:
Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over.
cpu/cpu_exec_context.cc:
Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
cpu/cpu_exec_context.hh:
Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
Remove kernel stats from the ExecContext.
sim/pseudo_inst.cc:
Kernel stats now live within the CPU.
Avoid accessing objects directly within the XC.
--HG--
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
into zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs
arch/alpha/ev5.cc:
Remove intr_post, it is no longer used.
arch/alpha/isa_traits.hh:
Hand merge.
--HG--
extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf
use "" not <>
targetarch->arch
arch/alpha/system.cc:
targetarch -> arch
base/loader/elf_object.cc:
we REALLY don't want to use system headers for libelf...
use "" not <>
--HG--
extra : convert_revision : d0e1672dc655dca3081e36b2158e7b19ef54af40
arch/sparc/SConscript:
Fixed up the SPARC SConscript to use the name of the SPARC source files.
arch/sparc/linux_process.cc:
Changed the namespace name from SPARCISA to SparcISA.
--HG--
extra : convert_revision : c340fbf78200bf7d962e7578a3f2998860224c53
SConscript:
Added ./libelf as an include search directory. There might be a better spot for this than where I put it.
arch/SConscript:
Combined the linux_process.h and tru64_process.h into process.h. This allows each ISA to support processes from arbitrary OSs.
arch/alpha/SConscript:
Added process.cc as a source file. It provides an implementation of createProcess, which takes an object_file object and creates the appropriate process object, or dies.
base/loader/elf_object.cc:
Actually extract the OS and architecture from the elf file, rather than always guessing Alpha and Linux.
base/loader/object_file.hh:
Added constants for SPARC, MIPS, and Solaris, and changed the include for the Addr type.
sim/process.cc:
Pushed creation of specific process objects into the ISA specific code.
--HG--
extra : convert_revision : b4754e7ca8328672d07e1394c4d162e199606b53
The shadow registers are folded into the normal integer registers to ease renaming indexing.
Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.
arch/alpha/ev5.cc:
Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using.
Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.
Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).
Change the dependence tags to reflect the integer registers include the 8 shadow registers.
Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
Change from MachInst to ExtMachInst to support shadow register renaming.
--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
arch/sparc/linux_process.cc:
Began modifying this file for sparc, and replaced the alpha syscall numbers with the sparc ones.
arch/sparc/linux_process.hh:
Begain modifying this file for sparc.
--HG--
extra : convert_revision : b1ed8ac50a35591521c5feaf1ea9c4b8ccc26dc8
arch/alpha/ev5.cc:
Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class.
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
cpu/exec_context.cc:
cpu/exec_context.hh:
Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode.
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Changed the execution context executing a fault to a fault executing on the execution context.
sim/faults.cc:
If not in full system mode, trying to invoke a fault causes a panic.
sim/faults.hh:
Removed the isA function.
--HG--
extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Formatting & doxygen.
arch/sparc/linux_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit, times and rt_sigaction.
Should eventually provide a function for times.
arch/sparc/linux_process.cc:
Fixes for Linux emulation:
- stat struct alignment
- osf_{get,set}sysinfo return values
- additional syscall numbers
- initialize $r0 to 0
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Updated Copyright
arch/sparc/linux_process.cc:
Alphabetize includes.
arch/sparc/linux_process.cc:
Changed all syscalls to use syscall return object
arch/sparc/linux_process.cc:
Removed unecessary constructor call at each return.
arch/sparc/linux_process.cc:
Rename sim/universe.{cc,hh} to root.{cc,hh}.
arch/sparc/linux_process.cc:
shuffle files around for new directory structure
arch/sparc/linux_process.cc:
Remove RCS Id string
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Update copyright dates and author list
arch/sparc/linux_process.hh:
remove $Id$ string
arch/sparc/linux_process.cc:
Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
arch/sparc/linux_process.cc:
Added the endianness namespace. This may change.
arch/sparc/linux_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
arch/sparc/linux_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
arch/sparc/linux_process.cc:
Add endian conversions to fstat
arch/sparc/linux_process.cc:
fix #if. I wonder why my compiler had no issues
arch/sparc/linux_process.cc:
add endian conversions for fstat functions
arch/sparc/linux_process.cc:
move architecture independent code into kern/linux/linux.(hh|cc)
arch/sparc/linux_process.hh:
Add getDesc function
arch/sparc/linux_process.cc:
Added using directive for AlphaISA namespace
arch/sparc/linux_process.cc:
Add pipeFunc.
arch/alpha/linux_process.cc:
Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
arch/sparc/linux_process.cc:
bk cp ../alpha/linux_process.cc linux_process.cc
arch/sparc/linux_process.hh:
bk cp ../alpha/linux_process.hh linux_process.hh
--HG--
extra : convert_revision : a8eca1c5f848383263a2326b0e3cde4bcd85f14b
This changeset removes a check that prevents quiescing when an
interrupt is pending. *** You should only call quiesce if that
isn't a problem. ***
arch/alpha/isa/decoder.isa:
sim/pseudo_inst.cc:
sim/pseudo_inst.hh:
Add quiesceNs, quiesceCycles, quisceTime and m5panic pseudo ops.
These quiesce for a number of ns, cycles, report how long
we were quiesced for, and panic the simulator respectively.
The latter is added to the panic() function in the console and linux
kernel instead of executing an infinite loop until someone notices.
cpu/exec_context.cc:
cpu/exec_context.hh:
Add a quiesce end event to the execution contexted which upon
executing wakes up a CPU for quiesceCycles/quiesceNs.
util/m5/Makefile:
Make the makefile more reasonable
util/m5/m5.c:
update the m5op executable to use the files from the linux tree
util/m5/m5op.S:
update m5op.S from linux tree
util/m5/m5op.h:
update m5op.h from linux tree
--HG--
rename : util/m5/m5op.s => util/m5/m5op.S
extra : convert_revision : 3be18525e811405b112e33f24a8c4e772d15462d
