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Updates for the quiesceEvent that was added to the XC.

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Also several files need to include system.hh or symtab.hh.  This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well.

arch/alpha/faults.cc:
    Avoid accessing XC directly.
arch/alpha/stacktrace.cc:
    StackTrace needs to include system.hh.
cpu/cpu_exec_context.cc:
    Update for change to CPUExecContext.
cpu/cpu_exec_context.hh:
    Make quiesce events use CPUExecContext instead of ExecContext.  Include functions to allow the quiesce event and last activate/suspend be accessed.
cpu/exec_context.hh:
    Include functions for quiesceEvent.
cpu/intr_control.cc:
    Needs to include cpu/exec_context.hh.
cpu/profile.cc:
    Needs to include symtab.hh for the symbol table.
cpu/profile.hh:
    Needs forward declare of ExecContext.
cpu/simple/cpu.cc:
    Rename xc to cpuXC.
dev/tsunami_cchip.cc:
    Needs to include exec_context.hh.
kern/kernel_stats.cc:
    Needs to include system.hh.
kern/linux/events.cc:
    Needs to include system.hh.

    Also avoid accessing objects directly from the XC.
kern/tru64/dump_mbuf.cc:
    Include symtab.hh for the SymbolTable and system.hh.
kern/tru64/tru64_events.cc:
    Include system.hh
sim/pseudo_inst.cc:
    Avoid accessing objects directly within the XC.

--HG--
extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
This commit is contained in:
Kevin Lim 2006-03-07 19:59:12 -05:00
parent 20eced3ea0
commit 11aead894d
15 changed files with 93 additions and 60 deletions
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18
arch/alpha/faults.cc
View file

@ -103,15 +103,15 @@ FaultStat IntegerOverflowFault::_stat;
void AlphaFault::invoke(ExecContext * xc)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
xc->cpu->recordEvent(csprintf("Fault %s", name()));
DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
assert(!xc->misspeculating());
xc->kernelStats->fault(this);
xc->getCpuPtr()->kernelStats->fault(this);
// exception restart address
if (setRestartAddress() || !xc->inPalMode())
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
@ -119,17 +119,17 @@ void AlphaFault::invoke(ExecContext * xc)
xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
xc->regs.npc = xc->regs.pc + sizeof(MachInst);
xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
xc->setNextPC(xc->readPC() + sizeof(MachInst));
}
void ArithmeticFault::invoke(ExecContext * xc)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
xc->cpu->recordEvent(csprintf("Fault %s", name()));
DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
assert(!xc->misspeculating());
xc->kernelStats->fault(this);
xc->getCpuPtr()->kernelStats->fault(this);
panic("Arithmetic traps are unimplemented!");
}

1
arch/alpha/stacktrace.cc
View file

@ -35,6 +35,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "sim/system.hh"
using namespace std;
using namespace AlphaISA;

37
cpu/cpu_exec_context.cc
View file

@ -57,8 +57,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this),
func_exe_inst(0), storeCondFailures(0)
profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0)
{
proxy = new ProxyExecContext<CPUExecContext>(this);
@ -119,21 +118,22 @@ void
CPUExecContext::dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
profile->dump(proxy, *os);
}
ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
: Event(&mainEventQueue), xc(_xc)
CPUExecContext::EndQuiesceEvent::EndQuiesceEvent(CPUExecContext *_cpuXC)
: Event(&mainEventQueue), cpuXC(_cpuXC)
{
}
void
ExecContext::EndQuiesceEvent::process()
CPUExecContext::EndQuiesceEvent::process()
{
xc->activate();
cpuXC->activate();
}
const char*
ExecContext::EndQuiesceEvent::description()
CPUExecContext::EndQuiesceEvent::description()
{
return "End Quiesce Event.";
}
@ -142,25 +142,25 @@ ExecContext::EndQuiesceEvent::description()
void
CPUExecContext::takeOverFrom(ExecContext *oldContext)
{
/*
// some things should already be set up
assert(mem == oldContext->mem);
assert(mem == oldContext->getMemPtr());
#if FULL_SYSTEM
assert(system == oldContext->system);
assert(system == oldContext->getSystemPtr());
#else
assert(process == oldContext->process);
assert(process == oldContext->getProcessPtr());
#endif
// copy over functional state
_status = oldContext->_status;
regs = oldContext->regs;
cpu_id = oldContext->cpu_id;
func_exe_inst = oldContext->func_exe_inst;
_status = oldContext->status();
copyArchRegs(oldContext);
cpu_id = oldContext->readCpuId();
#if !FULL_SYSTEM
func_exe_inst = oldContext->readFuncExeInst();
#endif
storeCondFailures = 0;
oldContext->_status = CPUExecContext::Unallocated;
*/
oldContext->setStatus(ExecContext::Unallocated);
}
void
@ -281,6 +281,9 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
setMiscReg(AlphaISA::Lock_Addr_DepTag,
xc->readMiscReg(AlphaISA::Lock_Addr_DepTag));
// Also need to copy all the IPRs. Probably should just have a copy misc
// regs function defined on the misc regs.
// Lastly copy PC/NPC
setPC(xc->readPC());
setNextPC(xc->readNextPC());

10
cpu/cpu_exec_context.hh
View file

@ -139,9 +139,9 @@ class CPUExecContext
struct EndQuiesceEvent : public Event
{
/** A pointer to the execution context that is quiesced */
ExecContext *xc;
CPUExecContext *cpuXC;
EndQuiesceEvent(ExecContext *_xc);
EndQuiesceEvent(CPUExecContext *_cpuXC);
/** Event process to occur at interrupt*/
virtual void process();
@ -151,6 +151,12 @@ class CPUExecContext
};
EndQuiesceEvent quiesceEvent;
Event *getQuiesceEvent() { return &quiesceEvent; }
Tick readLastActivate() { return lastActivate; }
Tick readLastSuspend() { return lastSuspend; }
#else
Process *process;

49
cpu/exec_context.hh
View file

@ -42,6 +42,7 @@
class AlphaDTB;
class AlphaITB;
class BaseCPU;
class Event;
class FunctionalMemory;
class PhysicalMemory;
class Process;
@ -102,6 +103,8 @@ class ExecContext
virtual Status status() const = 0;
virtual void setStatus(Status new_status) = 0;
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
virtual void activate(int delay = 1) = 0;
@ -119,13 +122,22 @@ class ExecContext
virtual void dumpFuncProfile() = 0;
#endif
virtual void takeOverFrom(ExecContext *oldContext) = 0;
virtual void takeOverFrom(ExecContext *old_context) = 0;
virtual void regStats(const std::string &name) = 0;
virtual void serialize(std::ostream &os) = 0;
virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
#if FULL_SYSTEM
virtual Event *getQuiesceEvent() = 0;
// Not necessarily the best location for these...
// Having an extra function just to read these is obnoxious
virtual Tick readLastActivate() = 0;
virtual Tick readLastSuspend() = 0;
#endif
virtual int getThreadNum() = 0;
virtual bool validInstAddr(Addr addr) = 0;
@ -139,6 +151,7 @@ class ExecContext
virtual Fault translateDataWriteReq(MemReqPtr &req) = 0;
// Also somewhat obnoxious. Really only used for the TLB fault.
virtual TheISA::MachInst getInst() = 0;
virtual void copyArchRegs(ExecContext *xc) = 0;
@ -180,6 +193,8 @@ class ExecContext
virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
virtual unsigned readStCondFailures() = 0;
virtual void setStCondFailures(unsigned sc_failures) = 0;
@ -189,20 +204,12 @@ class ExecContext
virtual void setIntrFlag(int val) = 0;
virtual Fault hwrei() = 0;
virtual bool inPalMode() = 0;
virtual void ev5_trap(Fault fault) = 0;
virtual bool simPalCheck(int palFunc) = 0;
#endif
// Only really makes sense for old CPU model. Still could be useful though.
virtual bool misspeculating() = 0;
/** Meant to be more generic trap function to be
* called when an instruction faults.
* @param fault The fault generated by executing the instruction.
* @todo How to do this properly so it's dependent upon ISA only?
*/
virtual void trap(Fault fault) = 0;
#if !FULL_SYSTEM
virtual IntReg getSyscallArg(int i) = 0;
@ -213,6 +220,7 @@ class ExecContext
virtual void syscall() = 0;
// Same with st cond failures.
virtual Counter readFuncExeInst() = 0;
virtual void setFuncExeInst(Counter new_val) = 0;
@ -253,6 +261,8 @@ class ProxyExecContext : public ExecContext
Status status() const { return actualXC->status(); }
void setStatus(Status new_status) { actualXC->setStatus(new_status); }
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
void activate(int delay = 1) { actualXC->activate(delay); }
@ -279,6 +289,13 @@ class ProxyExecContext : public ExecContext
void unserialize(Checkpoint *cp, const std::string &section)
{ actualXC->unserialize(cp, section); }
#if FULL_SYSTEM
Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
Tick readLastActivate() { return actualXC->readLastActivate(); }
Tick readLastSuspend() { return actualXC->readLastSuspend(); }
#endif
int getThreadNum() { return actualXC->getThreadNum(); }
bool validInstAddr(Addr addr) { return actualXC->validInstAddr(addr); }
@ -365,21 +382,11 @@ class ProxyExecContext : public ExecContext
bool inPalMode() { return actualXC->inPalMode(); }
void ev5_trap(Fault fault) { actualXC->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
#endif
// @todo: Fix this!
bool misspeculating() { return false; }
/** Meant to be more generic trap function to be
* called when an instruction faults.
* @param fault The fault generated by executing the instruction.
* @todo How to do this properly so it's dependent upon ISA only?
*/
void trap(Fault fault) { actualXC->trap(fault); }
bool misspeculating() { return actualXC->misspeculating(); }
#if !FULL_SYSTEM
IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }

1
cpu/intr_control.cc
View file

@ -30,6 +30,7 @@
#include <vector>
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"

1
cpu/profile.cc
View file

@ -32,6 +32,7 @@
#include "base/callback.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "cpu/profile.hh"

2
cpu/profile.hh
View file

@ -35,6 +35,8 @@
#include "sim/host.hh"
#include "arch/stacktrace.hh"
class ExecContext;
class ProfileNode
{
private:

2
cpu/simple/cpu.cc
View file

@ -766,7 +766,7 @@ SimpleCPU::tick()
// decode the instruction
inst = gtoh(inst);
curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC()));
curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
cpuXC->readPC());

1
dev/tsunami_cchip.cc
View file

@ -42,6 +42,7 @@
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"

1
kern/kernel_stats.cc
View file

@ -35,6 +35,7 @@
#include "cpu/exec_context.hh"
#include "kern/kernel_stats.hh"
#include "kern/tru64/tru64_syscalls.hh"
#include "sim/system.hh"
using namespace std;
using namespace Stats;

3
kern/linux/events.cc
View file

@ -32,6 +32,7 @@
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "kern/system_events.hh"
#include "sim/system.hh"
namespace Linux {
@ -41,7 +42,7 @@ DebugPrintkEvent::process(ExecContext *xc)
{
if (DTRACE(DebugPrintf)) {
if (!raw) {
StringWrap name(xc->system->name() + ".dprintk");
StringWrap name(xc->getSystemPtr()->name() + ".dprintk");
DPRINTFN("");
}

2
kern/tru64/dump_mbuf.cc
View file

@ -31,9 +31,11 @@
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/mbuf.hh"
#include "sim/host.hh"
#include "sim/system.hh"
#include "arch/arguments.hh"
#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"

1
kern/tru64/tru64_events.cc
View file

@ -35,6 +35,7 @@
#include "mem/functional/memory_control.hh"
#include "arch/arguments.hh"
#include "arch/isa_traits.hh"
#include "sim/system.hh"
using namespace TheISA;

24
sim/pseudo_inst.cc
View file

@ -83,13 +83,15 @@ namespace AlphaPseudo
if (!doQuiesce || ns == 0)
return;
if (xc->quiesceEvent.scheduled())
xc->quiesceEvent.reschedule(curTick + Clock::Int::ns * ns);
Event *quiesceEvent = xc->getQuiesceEvent();
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(curTick + Clock::Int::ns * ns);
else
xc->quiesceEvent.schedule(curTick + Clock::Int::ns * ns);
quiesceEvent->schedule(curTick + Clock::Int::ns * ns);
xc->suspend();
xc->kernelStats->quiesce();
xc->getCpuPtr()->kernelStats->quiesce();
}
void
@ -98,19 +100,23 @@ namespace AlphaPseudo
if (!doQuiesce || cycles == 0)
return;
if (xc->quiesceEvent.scheduled())
xc->quiesceEvent.reschedule(curTick + xc->cpu->cycles(cycles));
Event *quiesceEvent = xc->getQuiesceEvent();
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(curTick +
xc->getCpuPtr()->cycles(cycles));
else
xc->quiesceEvent.schedule(curTick + xc->cpu->cycles(cycles));
quiesceEvent->schedule(curTick +
xc->getCpuPtr()->cycles(cycles));
xc->suspend();
xc->kernelStats->quiesce();
xc->getCpuPtr()->kernelStats->quiesce();
}
uint64_t
quiesceTime(ExecContext *xc)
{
return (xc->lastActivate - xc->lastSuspend) / Clock::Int::ns ;
return (xc->readLastActivate() - xc->readLastSuspend()) / Clock::Int::ns;
}
void