sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Hand merge. Stuff probably doesn't compile.

Browse source 
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
This commit is contained in:
Gabe Black 2006-03-09 18:35:28 -05:00
commit 872bbdfc33
243 changed files with 19901 additions and 8800 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

129
SConscript
View file

@ -43,11 +43,8 @@ Import('env')
###################################################
# Base sources used by all configurations.
base_sources = Split('''
arch/alpha/decoder.cc
arch/alpha/faults.cc
arch/alpha/isa_traits.cc
base_sources = Split('''
base/circlebuf.cc
base/copyright.cc
base/cprintf.cc
@ -84,7 +81,7 @@ base_sources = Split('''
base/stats/text.cc
cpu/base.cc
cpu/exec_context.cc
cpu/cpu_exec_context.cc
cpu/exetrace.cc
cpu/op_class.cc
cpu/pc_event.cc
@ -104,6 +101,7 @@ base_sources = Split('''
sim/configfile.cc
sim/debug.cc
sim/eventq.cc
sim/faults.cc
sim/main.cc
sim/param.cc
sim/profile.cc
@ -119,28 +117,8 @@ base_sources = Split('''
sim/trace_context.cc
''')
fast_cpu_sources = Split('''
arch/alpha/fast_cpu_exec.cc
cpu/fast/cpu.cc
''')
simple_cpu_sources = Split('''
arch/alpha/simple_cpu_exec.cc
cpu/simple/cpu.cc
''')
trace_reader_sources = Split('''
cpu/trace/reader/mem_trace_reader.cc
cpu/trace/reader/ibm_reader.cc
cpu/trace/reader/itx_reader.cc
cpu/trace/reader/m5_reader.cc
cpu/trace/opt_cpu.cc
cpu/trace/trace_cpu.cc
''')
# Old FullCPU sources
full_cpu_sources = Split('''
arch/alpha/full_cpu_exec.cc
cpu/base_dyn_inst.cc
encumbered/cpu/full/bpred.cc
encumbered/cpu/full/commit.cc
encumbered/cpu/full/cpu.cc
@ -153,6 +131,7 @@ full_cpu_sources = Split('''
encumbered/cpu/full/execute.cc
encumbered/cpu/full/fetch.cc
encumbered/cpu/full/floss_reasons.cc
encumbered/cpu/full/fu_pool.cc
encumbered/cpu/full/inst_fifo.cc
encumbered/cpu/full/instpipe.cc
encumbered/cpu/full/issue.cc
@ -177,32 +156,17 @@ full_cpu_sources = Split('''
encumbered/cpu/full/iq/standard/iq_standard.cc
''')
o3_cpu_sources = Split('''
arch/alpha/alpha_o3_exec.cc
cpu/o3/2bit_local_pred.cc
cpu/o3/alpha_dyn_inst.cc
cpu/o3/alpha_cpu.cc
cpu/o3/alpha_cpu_builder.cc
cpu/o3/bpred_unit.cc
cpu/o3/btb.cc
cpu/o3/commit.cc
cpu/o3/decode.cc
cpu/o3/fetch.cc
cpu/o3/free_list.cc
cpu/o3/cpu.cc
cpu/o3/iew.cc
cpu/o3/inst_queue.cc
cpu/o3/ldstq.cc
cpu/o3/mem_dep_unit.cc
cpu/o3/ras.cc
cpu/o3/rename.cc
cpu/o3/rename_map.cc
cpu/o3/rob.cc
cpu/o3/sat_counter.cc
cpu/o3/store_set.cc
cpu/o3/tournament_pred.cc
trace_reader_sources = Split('''
cpu/trace/reader/mem_trace_reader.cc
cpu/trace/reader/ibm_reader.cc
cpu/trace/reader/itx_reader.cc
cpu/trace/reader/m5_reader.cc
cpu/trace/opt_cpu.cc
cpu/trace/trace_cpu.cc
''')
# MySql sources
mysql_sources = Split('''
base/mysql.cc
@ -211,14 +175,6 @@ mysql_sources = Split('''
# Full-system sources
full_system_sources = Split('''
arch/alpha/alpha_memory.cc
arch/alpha/arguments.cc
arch/alpha/ev5.cc
arch/alpha/osfpal.cc
arch/alpha/pseudo_inst.cc
arch/alpha/stacktrace.cc
arch/alpha/vtophys.cc
base/crc.cc
base/inet.cc
base/remote_gdb.cc
@ -258,17 +214,16 @@ full_system_sources = Split('''
kern/kernel_binning.cc
kern/kernel_stats.cc
kern/system_events.cc
kern/freebsd/freebsd_system.cc
kern/linux/events.cc
kern/linux/linux_syscalls.cc
kern/linux/linux_system.cc
kern/linux/printk.cc
kern/tru64/dump_mbuf.cc
kern/tru64/printf.cc
kern/tru64/tru64_events.cc
kern/tru64/tru64_syscalls.cc
kern/tru64/tru64_system.cc
mem/functional/memory_control.cc
sim/pseudo_inst.cc
''')
# turbolaser encumbered sources
@ -293,12 +248,11 @@ turbolaser_sources = Split('''
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
arch/alpha/alpha_common_syscall_emul.cc
arch/alpha/alpha_linux_process.cc
arch/alpha/alpha_tru64_process.cc
encumbered/eio/exolex.cc
encumbered/eio/libexo.cc
kern/linux/linux.cc
kern/tru64/tru64.cc
sim/process.cc
sim/syscall_emul.cc
''')
@ -311,33 +265,22 @@ memtest_sources = Split('''
cpu/memtest/memtest.cc
''')
targetarch_files = Split('''
alpha_common_syscall_emul.hh
alpha_linux_process.hh
alpha_memory.hh
alpha_tru64_process.hh
aout_machdep.h
arguments.hh
byte_swap.hh
ecoff_machdep.h
ev5.hh
faults.hh
isa_fullsys_traits.hh
isa_traits.hh
osfpal.hh
pseudo_inst.hh
stacktrace.hh
vptr.hh
vtophys.hh
''')
# Add a flag defining what THE_ISA should be for all compilation
env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
for f in targetarch_files:
env.Command('targetarch/' + f, 'arch/alpha/' + f,
'''echo '#include "arch/alpha/%s"' > $TARGET''' % f)
arch_sources = SConscript('arch/SConscript',
exports = 'env', duplicate = False)
cpu_sources = SConscript('cpu/SConscript',
exports = 'env', duplicate = False)
# This is outside of cpu/SConscript since the source directory isn't
# underneath 'cpu'.
if 'FullCPU' in env['CPU_MODELS']:
cpu_sources += full_cpu_sources
# Set up complete list of sources based on configuration.
sources = base_sources + simple_cpu_sources
sources = base_sources + arch_sources + cpu_sources
if env['FULL_SYSTEM']:
sources += full_system_sources
@ -364,17 +307,6 @@ env.Command(Split('base/traceflags.hh base/traceflags.cc'),
'base/traceflags.py',
'python $SOURCE $TARGET.base')
# several files are generated from arch/$TARGET_ISA/isa_desc.
env.Command(Split('''arch/alpha/decoder.cc
arch/alpha/decoder.hh
arch/alpha/alpha_o3_exec.cc
arch/alpha/fast_cpu_exec.cc
arch/alpha/simple_cpu_exec.cc'''),
Split('''arch/alpha/isa_desc
arch/isa_parser.py'''),
'$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/alpha')
# libelf build is described in its own SConscript file.
# SConscript-local is the per-config build, which just copies some
# header files into a place where they can be found.
@ -407,6 +339,7 @@ def make_objs(sources, env):
# the corresponding build directory to pick up generated include
# files.
env.Append(CPPPATH='.')
env.Append(CPPPATH='./libelf')
# Debug binary
debugEnv = env.Copy(OBJSUFFIX='.do')

153
arch/SConscript Normal file
View file

@ -0,0 +1,153 @@
# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os.path
# Import build environment variable from SConstruct.
Import('env')
# Right now there are no source files immediately in this directory
sources = []
#################################################################
#
# ISA "switch header" generation.
#
# Auto-generate arch headers that include the right ISA-specific
# header based on the setting of THE_ISA preprocessor variable.
#
#################################################################
# List of headers to generate
isa_switch_hdrs = Split('''
isa_traits.hh
tlb.hh
process.hh
arguments.hh
stacktrace.hh
vtophys.hh
faults.hh
''')
# Generate the header. target[0] is the full path of the output
# header to generate. 'source' is a dummy variable, since we get the
# list of ISAs from env['ALL_ISA_LIST'].
def gen_switch_hdr(target, source, env):
fname = str(target[0])
basename = os.path.basename(fname)
f = open(fname, 'w')
f.write('#include "arch/isa_specific.hh"\n')
cond = '#if'
for isa in env['ALL_ISA_LIST']:
f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n'
% (cond, isa.upper(), isa, basename))
cond = '#elif'
f.write('#else\n#error "THE_ISA not set"\n#endif\n')
f.close()
return 0
# String to print when generating header
def gen_switch_hdr_string(target, source, env):
return "Generating ISA switch header " + str(target[0])
# Build SCons Action object. 'varlist' specifies env vars that this
# action depends on; when env['ALL_ISA_LIST'] changes these actions
# should get re-executed.
switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
varlist=['ALL_ISA_LIST'])
# Instantiate actions for each header
for hdr in isa_switch_hdrs:
env.Command(hdr, [], switch_hdr_action)
#################################################################
#
# Include architecture-specific files.
#
#################################################################
#
# Build a SCons scanner for ISA files
#
import SCons.Scanner
def ISAScan():
return SCons.Scanner.Classic("ISAScan",
"$ISASUFFIXES",
"SRCDIR",
'^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"')
def ISAPath(env, dir, target=None, source=None, a=None):
return (Dir(env['SRCDIR']), Dir('.'))
iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"],
path_function = ISAPath)
env.Append(SCANNERS = iscan)
#
# Now create a Builder object that uses isa_parser.py to generate C++
# output from the ISA description (*.isa) files.
#
# Convert to File node to fix path
isa_parser = File('isa_parser.py')
cpu_models_file = File('#m5/cpu/cpu_models.py')
# This sucks in the defintions of the CpuModel objects.
execfile(cpu_models_file.srcnode().abspath)
# Several files are generated from the ISA description.
# We always get the basic decoder and header file.
isa_desc_gen_files = Split('decoder.cc decoder.hh')
# We also get an execute file for each selected CPU model.
isa_desc_gen_files += [CpuModel.dict[cpu].filename
for cpu in env['CPU_MODELS']]
# The emitter patches up the sources & targets to include the
# autogenerated files as targets and isa parser itself as a source.
def isa_desc_emitter(target, source, env):
return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
# Pieces are in place, so create the builder.
isa_desc_builder = Builder(action='$SOURCES $TARGET.dir $CPU_MODELS',
source_scanner = iscan,
emitter = isa_desc_emitter)
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
#
# Now include other ISA-specific sources from the ISA subdirectories.
#
isa = env['TARGET_ISA'] # someday this may be a list of ISAs
# Let the target architecture define what additional sources it needs
sources += SConscript(os.path.join(isa, 'SConscript'),
exports = 'env', duplicate = False)
Return('sources')

91
arch/alpha/SConscript Normal file
View file

@ -0,0 +1,91 @@
# -*- mode:python -*-
# Copyright (c) 2004-2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import sys
from os.path import isdir
# This file defines how to build a particular configuration of M5
# based on variable settings in the 'env' build environment.
# Import build environment variable from SConstruct.
Import('env')
###################################################
#
# Define needed sources.
#
###################################################
# Base sources used by all configurations.
base_sources = Split('''
faults.cc
isa_traits.cc
''')
# Full-system sources
full_system_sources = Split('''
tlb.cc
arguments.cc
ev5.cc
osfpal.cc
stacktrace.cc
vtophys.cc
system.cc
freebsd/system.cc
linux/system.cc
tru64/system.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
linux/process.cc
tru64/process.cc
process.cc
''')
# Set up complete list of sources based on configuration.
sources = base_sources
if env['FULL_SYSTEM']:
sources += full_system_sources
else:
sources += syscall_emulation_sources
# Convert file names to SCons File objects. This takes care of the
# path relative to the top of the directory tree.
sources = [File(s) for s in sources]
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
# Only non-header files need to be compiled.
isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
sources += isa_desc_sources
Return('sources')

1936
arch/alpha/alpha_tru64_process.cc
View file

File diff suppressed because it is too large Load diff

10
arch/alpha/arguments.cc
View file

@ -31,6 +31,8 @@
#include "cpu/exec_context.hh"
#include "mem/functional/physical.hh"
using namespace AlphaISA;
AlphaArguments::Data::~Data()
{
while (!data.empty()) {
@ -52,13 +54,13 @@ AlphaArguments::getArg(bool fp)
{
if (number < 6) {
if (fp)
return xc->regs.floatRegFile.q[16 + number];
return xc->readFloatRegInt(16 + number);
else
return xc->regs.intRegFile[16 + number];
return xc->readIntReg(16 + number);
} else {
Addr sp = xc->regs.intRegFile[30];
Addr sp = xc->readIntReg(30);
Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t));
return xc->physmem->phys_read_qword(paddr);
return xc->getPhysMemPtr()->phys_read_qword(paddr);
}
}

251
arch/alpha/ev5.cc
View file

@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/alpha/alpha_memory.hh"
#include "arch/alpha/tlb.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/osfpal.hh"
#include "base/kgdb.h"
@ -34,6 +34,7 @@
#include "base/stats/events.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
#include "cpu/exec_context.hh"
#include "cpu/fast/cpu.hh"
#include "kern/kernel_stats.hh"
@ -44,85 +45,36 @@
using namespace EV5;
////////////////////////////////////////////////////////////////////////
//
//
//
void
AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
{
if (regs->pal_shadow == use_shadow)
panic("swap_palshadow: wrong PAL shadow state");
regs->pal_shadow = use_shadow;
for (int i = 0; i < NumIntRegs; i++) {
if (reg_redir[i]) {
IntReg temp = regs->intRegFile[i];
regs->intRegFile[i] = regs->palregs[i];
regs->palregs[i] = temp;
}
}
}
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
//
void
AlphaISA::initCPU(RegFile *regs)
AlphaISA::initCPU(ExecContext *xc, int cpuId)
{
initIPRs(regs);
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
initIPRs(xc, cpuId);
regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
regs->npc = regs->pc + sizeof(MachInst);
xc->setIntReg(16, cpuId);
xc->setIntReg(0, cpuId);
xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
xc->setNextPC(xc->readPC() + sizeof(MachInst));
}
////////////////////////////////////////////////////////////////////////
//
// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
//
Addr
AlphaISA::fault_addr[Num_Faults] = {
0x0000, /* No_Fault */
0x0001, /* Reset_Fault */
0x0401, /* Machine_Check_Fault */
0x0501, /* Arithmetic_Fault */
0x0101, /* Interrupt_Fault */
0x0201, /* Ndtb_Miss_Fault */
0x0281, /* Pdtb_Miss_Fault */
0x0301, /* Alignment_Fault */
0x0381, /* DTB_Fault_Fault */
0x0381, /* DTB_Acv_Fault */
0x0181, /* ITB_Miss_Fault */
0x0181, /* ITB_Fault_Fault */
0x0081, /* ITB_Acv_Fault */
0x0481, /* Unimplemented_Opcode_Fault */
0x0581, /* Fen_Fault */
0x2001, /* Pal_Fault */
0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
};
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
/* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
////////////////////////////////////////////////////////////////////////
//
//
//
void
AlphaISA::initIPRs(RegFile *regs)
AlphaISA::initIPRs(ExecContext *xc, int cpuId)
{
uint64_t *ipr = regs->ipr;
for (int i = 0; i < NumInternalProcRegs; ++i) {
xc->setMiscReg(i, 0);
}
bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
ipr[IPR_PAL_BASE] = PalBase;
ipr[IPR_MCSR] = 0x6;
xc->setMiscReg(IPR_PAL_BASE, PalBase);
xc->setMiscReg(IPR_MCSR, 0x6);
xc->setMiscReg(IPR_PALtemp16, cpuId);
}
@ -134,17 +86,16 @@ AlphaISA::processInterrupts(CPU *cpu)
//Handle the interrupts
int ipl = 0;
int summary = 0;
IntReg *ipr = cpu->getIprPtr();
cpu->checkInterrupts = false;
if (ipr[IPR_ASTRR])
if (cpu->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
if (ipr[IPR_SIRR]) {
if (cpu->readMiscReg(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
if (ipr[IPR_SIRR] & (ULL(1) << i)) {
if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@ -165,12 +116,12 @@ AlphaISA::processInterrupts(CPU *cpu)
}
}
if (ipl && ipl > ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
cpu->trap(Interrupt_Fault);
if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
cpu->setMiscReg(IPR_ISR, summary);
cpu->setMiscReg(IPR_INTID, ipl);
cpu->trap(new InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
cpu->readMiscReg(IPR_IPLR), ipl, summary);
}
}
@ -182,96 +133,43 @@ AlphaISA::zeroRegisters(CPU *cpu)
// Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
cpu->xc->setIntReg(ZeroReg, 0);
cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
}
void
ExecContext::ev5_trap(Fault fault)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
assert(!misspeculating());
kernelStats->fault(fault);
if (fault == Arithmetic_Fault)
panic("Arithmetic traps are unimplemented!");
AlphaISA::InternalProcReg *ipr = regs.ipr;
// exception restart address
if (fault != Interrupt_Fault || !inPalMode())
ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
fault == Interrupt_Fault && !inPalMode() */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
regs.npc = regs.pc + sizeof(MachInst);
}
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{
InternalProcReg *ipr = regs->ipr;
bool use_pc = (fault == No_Fault);
if (fault == Arithmetic_Fault)
panic("arithmetic faults NYI...");
// compute exception restart address
if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
// traps... skip faulting instruction
ipr[IPR_EXC_ADDR] = regs->pc + 4;
} else {
// fault, post fault at excepting instruction
ipr[IPR_EXC_ADDR] = regs->pc;
}
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
else
regs->npc = ipr[IPR_PAL_BASE] + pc;
// that's it! (orders of magnitude less painful than x86)
cpu->cpuXC->setIntReg(ZeroReg, 0);
cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
}
Fault
ExecContext::hwrei()
CPUExecContext::hwrei()
{
uint64_t *ipr = regs.ipr;
if (!inPalMode())
return Unimplemented_Opcode_Fault;
return new UnimplementedOpcodeFault;
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
if (!misspeculating()) {
kernelStats->hwrei();
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(&regs, false);
cpu->kernelStats->hwrei();
cpu->checkInterrupts = true;
}
// FIXME: XXX check for interrupts? XXX
return No_Fault;
return NoFault;
}
uint64_t
ExecContext::readIpr(int idx, Fault &fault)
int
AlphaISA::MiscRegFile::getInstAsid()
{
return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
AlphaISA::MiscRegFile::getDataAsid()
{
return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
AlphaISA::MiscReg
AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
{
uint64_t *ipr = regs.ipr;
uint64_t retval = 0; // return value, default 0
switch (idx) {
@ -324,7 +222,7 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= cpu->curCycle() & ULL(0x00000000ffffffff);
retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
break;
case AlphaISA::IPR_VA:
@ -341,7 +239,7 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_DTB_PTE:
{
AlphaISA::PTE &pte = dtb->index(!misspeculating());
AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@ -363,12 +261,12 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
fault = Unimplemented_Opcode_Fault;
fault = new UnimplementedOpcodeFault;
break;
default:
// invalid IPR
fault = Unimplemented_Opcode_Fault;
fault = new UnimplementedOpcodeFault;
break;
}
@ -381,13 +279,12 @@ int break_ipl = -1;
#endif
Fault
ExecContext::setIpr(int idx, uint64_t val)
AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
{
uint64_t *ipr = regs.ipr;
uint64_t old;
if (misspeculating())
return No_Fault;
if (xc->misspeculating())
return NoFault;
switch (idx) {
case AlphaISA::IPR_PALtemp0:
@ -439,7 +336,7 @@ ExecContext::setIpr(int idx, uint64_t val)
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
kernelStats->context(old, val);
xc->getCpuPtr()->kernelStats->context(old, val, xc);
break;
case AlphaISA::IPR_DTB_PTE:
@ -466,14 +363,14 @@ ExecContext::setIpr(int idx, uint64_t val)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
kernelStats->swpipl(ipr[idx]);
xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
break;
case AlphaISA::IPR_DTB_CM:
if (val & 0x18)
kernelStats->mode(Kernel::user);
xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
else
kernelStats->mode(Kernel::kernel);
xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
@ -533,7 +430,7 @@ ExecContext::setIpr(int idx, uint64_t val)
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
return Unimplemented_Opcode_Fault;
return new UnimplementedOpcodeFault;
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
@ -547,21 +444,22 @@ ExecContext::setIpr(int idx, uint64_t val)
// really a control write
ipr[idx] = 0;
dtb->flushAll();
xc->getDTBPtr()->flushAll();
break;
case AlphaISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
dtb->flushProcesses();
xc->getDTBPtr()->flushProcesses();
break;
case AlphaISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
xc->getDTBPtr()->flushAddr(val,
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
@ -584,7 +482,7 @@ ExecContext::setIpr(int idx, uint64_t val)
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
dtb->insert(val, pte);
xc->getDTBPtr()->insert(val, pte);
}
break;
@ -608,7 +506,7 @@ ExecContext::setIpr(int idx, uint64_t val)
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
}
break;
@ -616,30 +514,39 @@ ExecContext::setIpr(int idx, uint64_t val)
// really a control write
ipr[idx] = 0;
itb->flushAll();
xc->getITBPtr()->flushAll();
break;
case AlphaISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
itb->flushProcesses();
xc->getITBPtr()->flushProcesses();
break;
case AlphaISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
xc->getITBPtr()->flushAddr(val,
ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
// invalid IPR
return Unimplemented_Opcode_Fault;
return new UnimplementedOpcodeFault;
}
// no error...
return No_Fault;
return NoFault;
}
void
AlphaISA::MiscRegFile::copyIprs(ExecContext *xc)
{
for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
ipr[i] = xc->readMiscReg(i);
}
}
/**
@ -647,9 +554,9 @@ ExecContext::setIpr(int idx, uint64_t val)
* If return value is false, actual PAL call will be suppressed.
*/
bool
ExecContext::simPalCheck(int palFunc)
CPUExecContext::simPalCheck(int palFunc)
{
kernelStats->callpal(palFunc);
cpu->kernelStats->callpal(palFunc, proxy);
switch (palFunc) {
case PAL::halt:

4
arch/alpha/ev5.hh
View file

@ -30,9 +30,13 @@
#define __ARCH_ALPHA_EV5_HH__
#include "config/alpha_tlaser.hh"
#include "arch/alpha/isa_traits.hh"
namespace EV5 {
//It seems like a safe assumption EV5 only applies to alpha
using namespace AlphaISA;
#if ALPHA_TLASER
const uint64_t AsnMask = ULL(0x7f);
#else

124
arch/alpha/faults.cc
View file

@ -27,35 +27,105 @@
*/
#include "arch/alpha/faults.hh"
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
namespace {
const char *
fault_name[Num_Faults] = {
"none",
"reset",
"mchk",
"arith",
"interrupt",
"dtb_miss_single",
"dtb_miss_double",
"unalign",
"dfault",
"dfault",
"itbmiss",
"itbmiss",
"iaccvio",
"opdec",
"fen",
"pal",
};
}
const char *
FaultName(int index)
namespace AlphaISA
{
if (index < 0 || index >= Num_Faults)
return 0;
return fault_name[index];
FaultName MachineCheckFault::_name = "mchk";
FaultVect MachineCheckFault::_vect = 0x0401;
FaultStat MachineCheckFault::_count;
FaultName AlignmentFault::_name = "unalign";
FaultVect AlignmentFault::_vect = 0x0301;
FaultStat AlignmentFault::_count;
FaultName ResetFault::_name = "reset";
FaultVect ResetFault::_vect = 0x0001;
FaultStat ResetFault::_count;
FaultName ArithmeticFault::_name = "arith";
FaultVect ArithmeticFault::_vect = 0x0501;
FaultStat ArithmeticFault::_count;
FaultName InterruptFault::_name = "interrupt";
FaultVect InterruptFault::_vect = 0x0101;
FaultStat InterruptFault::_count;
FaultName NDtbMissFault::_name = "dtb_miss_single";
FaultVect NDtbMissFault::_vect = 0x0201;
FaultStat NDtbMissFault::_count;
FaultName PDtbMissFault::_name = "dtb_miss_double";
FaultVect PDtbMissFault::_vect = 0x0281;
FaultStat PDtbMissFault::_count;
FaultName DtbPageFault::_name = "dfault";
FaultVect DtbPageFault::_vect = 0x0381;
FaultStat DtbPageFault::_count;
FaultName DtbAcvFault::_name = "dfault";
FaultVect DtbAcvFault::_vect = 0x0381;
FaultStat DtbAcvFault::_count;
FaultName ItbMissFault::_name = "itbmiss";
FaultVect ItbMissFault::_vect = 0x0181;
FaultStat ItbMissFault::_count;
FaultName ItbPageFault::_name = "itbmiss";
FaultVect ItbPageFault::_vect = 0x0181;
FaultStat ItbPageFault::_count;
FaultName ItbAcvFault::_name = "iaccvio";
FaultVect ItbAcvFault::_vect = 0x0081;
FaultStat ItbAcvFault::_count;
FaultName UnimplementedOpcodeFault::_name = "opdec";
FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
FaultStat UnimplementedOpcodeFault::_count;
FaultName FloatEnableFault::_name = "fen";
FaultVect FloatEnableFault::_vect = 0x0581;
FaultStat FloatEnableFault::_count;
FaultName PalFault::_name = "pal";
FaultVect PalFault::_vect = 0x2001;
FaultStat PalFault::_count;
FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
#if FULL_SYSTEM
void AlphaFault::invoke(ExecContext * xc)
{
FaultBase::invoke(xc);
countStat()++;
// exception restart address
if (setRestartAddress() || !xc->inPalMode())
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
xc->setNextPC(xc->readPC() + sizeof(MachInst));
}
void ArithmeticFault::invoke(ExecContext * xc)
{
FaultBase::invoke(xc);
panic("Arithmetic traps are unimplemented!");
}
#endif
} // namespace AlphaISA

260
arch/alpha/faults.hh
View file

@ -26,32 +26,244 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FAULTS_HH__
#define __FAULTS_HH__
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
enum Fault {
No_Fault,
Reset_Fault, // processor reset
Machine_Check_Fault, // machine check (also internal S/W fault)
Arithmetic_Fault, // FP exception
Interrupt_Fault, // external interrupt
Ndtb_Miss_Fault, // DTB miss
Pdtb_Miss_Fault, // nested DTB miss
Alignment_Fault, // unaligned access
DTB_Fault_Fault, // DTB page fault
DTB_Acv_Fault, // DTB access violation
ITB_Miss_Fault, // ITB miss
ITB_Fault_Fault, // ITB page fault
ITB_Acv_Fault, // ITB access violation
Unimplemented_Opcode_Fault, // invalid/unimplemented instruction
Fen_Fault, // FP not-enabled fault
Pal_Fault, // call_pal S/W interrupt
Integer_Overflow_Fault,
Fake_Mem_Fault,
Num_Faults // number of faults
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
namespace AlphaISA
{
typedef const Addr FaultVect;
class AlphaFault : public FaultBase
{
protected:
virtual bool skipFaultingInstruction() {return false;}
virtual bool setRestartAddress() {return true;}
public:
#if FULL_SYSTEM
void invoke(ExecContext * xc);
#endif
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
};
const char *
FaultName(int index);
class MachineCheckFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
bool isMachineCheckFault() {return true;}
};
class AlignmentFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
bool isAlignmentFault() {return true;}
};
static inline Fault genMachineCheckFault()
{
return new MachineCheckFault;
}
static inline Fault genAlignmentFault()
{
return new AlignmentFault;
}
class ResetFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class ArithmeticFault : public AlphaFault
{
protected:
bool skipFaultingInstruction() {return true;}
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if FULL_SYSTEM
void invoke(ExecContext * xc);
#endif
};
class InterruptFault : public AlphaFault
{
protected:
bool setRestartAddress() {return false;}
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class NDtbMissFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class PDtbMissFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class DtbPageFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class DtbAcvFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class ItbMissFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class ItbPageFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class ItbAcvFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class UnimplementedOpcodeFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class FloatEnableFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class PalFault : public AlphaFault
{
protected:
bool skipFaultingInstruction() {return true;}
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class IntegerOverflowFault : public AlphaFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
} // AlphaISA namespace
#endif // __FAULTS_HH__

40
kern/freebsd/freebsd_system.cc → arch/alpha/freebsd/system.cc
View file

@ -33,20 +33,24 @@
*
*/
#include "arch/alpha/system.hh"
#include "arch/alpha/freebsd/system.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh"
#include "kern/freebsd/freebsd_system.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "arch/isa_traits.hh"
#include "sim/builder.hh"
#include "targetarch/vtophys.hh"
#include "sim/byteswap.hh"
#include "arch/vtophys.hh"
#define TIMER_FREQUENCY 1193180
using namespace std;
using namespace AlphaISA;
FreebsdSystem::FreebsdSystem(Params *p)
: System(p)
FreebsdAlphaSystem::FreebsdAlphaSystem(Params *p)
: AlphaSystem(p)
{
/**
* Any time DELAY is called just skip the function.
@ -58,7 +62,7 @@ FreebsdSystem::FreebsdSystem(Params *p)
}
FreebsdSystem::~FreebsdSystem()
FreebsdAlphaSystem::~FreebsdAlphaSystem()
{
delete skipDelayEvent;
delete skipCalibrateClocks;
@ -66,15 +70,15 @@ FreebsdSystem::~FreebsdSystem()
void
FreebsdSystem::doCalibrateClocks(ExecContext *xc)
FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc)
{
Addr ppc_vaddr = 0;
Addr timer_vaddr = 0;
Addr ppc_paddr = 0;
Addr timer_paddr = 0;
ppc_vaddr = (Addr)xc->regs.intRegFile[ArgumentReg1];
timer_vaddr = (Addr)xc->regs.intRegFile[ArgumentReg2];
ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1);
timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2);
ppc_paddr = vtophys(physmem, ppc_vaddr);
timer_paddr = vtophys(physmem, timer_vaddr);
@ -88,14 +92,14 @@ FreebsdSystem::doCalibrateClocks(ExecContext *xc)
void
FreebsdSystem::SkipCalibrateClocksEvent::process(ExecContext *xc)
FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc)
{
SkipFuncEvent::process(xc);
((FreebsdSystem *)xc->system)->doCalibrateClocks(xc);
((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdSystem)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<MemoryController *> memctrl;
@ -116,9 +120,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdSystem)
VectorParam<string> binned_fns;
Param<bool> bin_int;
END_DECLARE_SIM_OBJECT_PARAMS(FreebsdSystem)
END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(memctrl, "memory controller"),
@ -136,11 +140,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdSystem)
INIT_PARAM(binned_fns, "functions to be broken down and binned"),
INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
END_INIT_SIM_OBJECT_PARAMS(FreebsdSystem)
END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
CREATE_SIM_OBJECT(FreebsdSystem)
CREATE_SIM_OBJECT(FreebsdAlphaSystem)
{
System::Params *p = new System::Params;
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->memctrl = memctrl;
@ -156,8 +160,8 @@ CREATE_SIM_OBJECT(FreebsdSystem)
p->bin = bin;
p->binned_fns = binned_fns;
p->bin_int = bin_int;
return new FreebsdSystem(p);
return new FreebsdAlphaSystem(p);
}
REGISTER_SIM_OBJECT("FreebsdSystem", FreebsdSystem)
REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem)

6
kern/freebsd/freebsd_system.hh → arch/alpha/freebsd/system.hh
View file

@ -31,7 +31,7 @@
#include "kern/system_events.hh"
class FreebsdSystem : public System
class FreebsdAlphaSystem : public AlphaSystem
{
private:
class SkipCalibrateClocksEvent : public SkipFuncEvent
@ -47,8 +47,8 @@ class FreebsdSystem : public System
SkipCalibrateClocksEvent *skipCalibrateClocks;
public:
FreebsdSystem(Params *p);
~FreebsdSystem();
FreebsdAlphaSystem(Params *p);
~FreebsdAlphaSystem();
void doCalibrateClocks(ExecContext *xc);
};

259
arch/alpha/isa/branch.isa Normal file
View file

@ -0,0 +1,259 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Base class for instructions whose disassembly is not purely a
* function of the machine instruction (i.e., it depends on the
* PC). This class overrides the disassemble() method to check
* the PC and symbol table values before re-using a cached
* disassembly string. This is necessary for branches and jumps,
* where the disassembly string includes the target address (which
* may depend on the PC and/or symbol table).
*/
class PCDependentDisassembly : public AlphaStaticInst
{
protected:
/// Cached program counter from last disassembly
mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly
mutable const SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
cachedPC(0), cachedSymtab(0)
{
}
const std::string &
disassemble(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for branches (PC-relative control transfers),
* conditional or unconditional.
*/
class Branch : public PCDependentDisassembly
{
protected:
/// Displacement to target address (signed).
int32_t disp;
/// Constructor.
Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(BRDISP << 2)
{
}
Addr branchTarget(Addr branchPC) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for jumps (register-indirect control transfers). In
* the Alpha ISA, these are always unconditional.
*/
class Jump : public PCDependentDisassembly
{
protected:
/// Displacement to target address (signed).
int32_t disp;
public:
/// Constructor
Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(BRDISP)
{
}
Addr branchTarget(ExecContext *xc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
Addr
Branch::branchTarget(Addr branchPC) const
{
return branchPC + 4 + disp;
}
Addr
Jump::branchTarget(ExecContext *xc) const
{
Addr NPC = xc->readPC() + 4;
uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}
const std::string &
PCDependentDisassembly::disassemble(Addr pc,
const SymbolTable *symtab) const
{
if (!cachedDisassembly ||
pc != cachedPC || symtab != cachedSymtab)
{
if (cachedDisassembly)
delete cachedDisassembly;
cachedDisassembly =
new std::string(generateDisassembly(pc, symtab));
cachedPC = pc;
cachedSymtab = symtab;
}
return *cachedDisassembly;
}
std::string
Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// There's only one register arg (RA), but it could be
// either a source (the condition for conditional
// branches) or a destination (the link reg for
// unconditional branches)
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
}
else if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
ss << ",";
}
#ifdef SS_COMPATIBLE_DISASSEMBLY
if (_numSrcRegs == 0 && _numDestRegs == 0) {
printReg(ss, 31);
ss << ",";
}
#endif
Addr target = pc + 4 + disp;
std::string str;
if (symtab && symtab->findSymbol(target, str))
ss << str;
else
ccprintf(ss, "0x%x", target);
return ss.str();
}
std::string
Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
#ifdef SS_COMPATIBLE_DISASSEMBLY
if (_numDestRegs == 0) {
printReg(ss, 31);
ss << ",";
}
#endif
if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
ss << ",";
}
ccprintf(ss, "(r%d)", RB);
return ss.str();
}
}};
def template JumpOrBranchDecode {{
return (RA == 31)
? (StaticInst *)new %(class_name)s(machInst)
: (StaticInst *)new %(class_name)sAndLink(machInst);
}};
def format CondBranch(code) {{
code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl'))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
let {{
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
# Declare basic control transfer w/o link (i.e. link reg is R31)
nolink_code = 'NPC = %s;\n' % npc_expr
nolink_iop = InstObjParams(name, Name, base_class,
CodeBlock(nolink_code), flags)
header_output = BasicDeclare.subst(nolink_iop)
decoder_output = BasicConstructor.subst(nolink_iop)
exec_output = BasicExecute.subst(nolink_iop)
# Generate declaration of '*AndLink' version, append to decls
link_code = 'Ra = NPC & ~3;\n' + nolink_code
link_iop = InstObjParams(name, Name + 'AndLink', base_class,
CodeBlock(link_code), flags)
header_output += BasicDeclare.subst(link_iop)
decoder_output += BasicConstructor.subst(link_iop)
exec_output += BasicExecute.subst(link_iop)
# need to use link_iop for the decode template since it is expecting
# the shorter version of class_name (w/o "AndLink")
return (header_output, decoder_output,
JumpOrBranchDecode.subst(nolink_iop), exec_output)
}};
def format UncondBranch(*flags) {{
flags += ('IsUncondControl', 'IsDirectControl')
(header_output, decoder_output, decode_block, exec_output) = \
UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
}};
def format Jump(*flags) {{
flags += ('IsUncondControl', 'IsIndirectControl')
(header_output, decoder_output, decode_block, exec_output) = \
UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
}};

819
arch/alpha/isa/decoder.isa Normal file
View file

@ -0,0 +1,819 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
decode OPCODE default Unknown::unknown() {
format LoadAddress {
0x08: lda({{ Ra = Rb + disp; }});
0x09: ldah({{ Ra = Rb + (disp << 16); }});
}
format LoadOrNop {
0x0a: ldbu({{ Ra.uq = Mem.ub; }});
0x0c: ldwu({{ Ra.uq = Mem.uw; }});
0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
0x23: ldt({{ Fa = Mem.df; }});
0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
{{ fault = xc->copySrcTranslate(EA); }},
inst_flags = [IsMemRef, IsLoad, IsCopy]);
}
format LoadOrPrefetch {
0x28: ldl({{ Ra.sl = Mem.sl; }});
0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
// IsFloating flag on lds gets the prefetch to disassemble
// using f31 instead of r31... funcitonally it's unnecessary
0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
}
format Store {
0x0e: stb({{ Mem.ub = Ra<7:0>; }});
0x0d: stw({{ Mem.uw = Ra<15:0>; }});
0x2c: stl({{ Mem.ul = Ra<31:0>; }});
0x2d: stq({{ Mem.uq = Ra.uq; }});
0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
0x27: stt({{ Mem.df = Fa; }});
0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
{{ fault = xc->copy(EA); }},
inst_flags = [IsMemRef, IsStore, IsCopy]);
}
format StoreCond {
0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
{{
uint64_t tmp = write_result;
// see stq_c
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
}}, mem_flags = LOCKED);
0x2f: stq_c({{ Mem.uq = Ra; }},
{{
uint64_t tmp = write_result;
// If the write operation returns 0 or 1, then
// this was a conventional store conditional,
// and the value indicates the success/failure
// of the operation. If another value is
// returned, then this was a Turbolaser
// mailbox access, and we don't update the
// result register at all.
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
}}, mem_flags = LOCKED);
}
format IntegerOperate {
0x10: decode INTFUNC { // integer arithmetic operations
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
0x40: addlv({{
uint32_t tmp = Ra.sl + Rb_or_imm.sl;
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
0x20: addq({{ Rc = Ra + Rb_or_imm; }});
0x60: addqv({{
uint64_t tmp = Ra + Rb_or_imm;
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
0x49: sublv({{
uint32_t tmp = Ra.sl - Rb_or_imm.sl;
// signed overflow detection is same as for add,
// except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
0x29: subq({{ Rc = Ra - Rb_or_imm; }});
0x69: subqv({{
uint64_t tmp = Ra - Rb_or_imm;
// signed overflow detection is same as for add,
// except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
0x0f: cmpbge({{
int hi = 7;
int lo = 0;
uint64_t tmp = 0;
for (int i = 0; i < 8; ++i) {
tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
hi += 8;
lo += 8;
}
Rc = tmp;
}});
}
0x11: decode INTFUNC { // integer logical operations
0x00: and({{ Rc = Ra & Rb_or_imm; }});
0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
0x20: bis({{ Rc = Ra | Rb_or_imm; }});
0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
// conditional moves
0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
// For AMASK, RA must be R31.
0x61: decode RA {
31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
}
// For IMPLVER, RA must be R31 and the B operand
// must be the immediate value 1.
0x6c: decode RA {
31: decode IMM {
1: decode INTIMM {
// return EV5 for FULL_SYSTEM and EV6 otherwise
1: implver({{
#if FULL_SYSTEM
Rc = 1;
#else
Rc = 2;
#endif
}});
}
}
}
#if FULL_SYSTEM
// The mysterious 11.25...
0x25: WarnUnimpl::eleven25();
#endif
}
0x12: decode INTFUNC {
0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
0x52: mskwh({{
int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
}});
0x62: msklh({{
int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
}});
0x72: mskqh({{
int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
}});
0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
0x5a: extwh({{
Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
0x6a: extlh({{
Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
0x7a: extqh({{
Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
0x57: inswh({{
int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
}});
0x67: inslh({{
int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
}});
0x77: insqh({{
int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
}});
0x30: zap({{
uint64_t zapmask = 0;
for (int i = 0; i < 8; ++i) {
if (Rb_or_imm<i:>)
zapmask |= (mask(8) << (i * 8));
}
Rc = Ra & ~zapmask;
}});
0x31: zapnot({{
uint64_t zapmask = 0;
for (int i = 0; i < 8; ++i) {
if (!Rb_or_imm<i:>)
zapmask |= (mask(8) << (i * 8));
}
Rc = Ra & ~zapmask;
}});
}
0x13: decode INTFUNC { // integer multiplies
0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{
uint64_t hi, lo;
mul128(Ra, Rb_or_imm, hi, lo);
Rc = hi;
}}, IntMultOp);
0x40: mullv({{
// 32-bit multiply with trap on overflow
int64_t Rax = Ra.sl; // sign extended version of Ra.sl
int64_t Rbx = Rb_or_imm.sl;
int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
fault = new IntegerOverflowFault;
Rc.sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
// 64-bit multiply with trap on overflow
uint64_t hi, lo;
mul128(Ra, Rb_or_imm, hi, lo);
// all the upper 64 bits must match the sign bit of
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
fault = new IntegerOverflowFault;
Rc = lo;
}}, IntMultOp);
}
0x1c: decode INTFUNC {
0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
0x32: ctlz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (temp<63:32>) temp >>= 32; else count += 32;
if (temp<31:16>) temp >>= 16; else count += 16;
if (temp<15:8>) temp >>= 8; else count += 8;
if (temp<7:4>) temp >>= 4; else count += 4;
if (temp<3:2>) temp >>= 2; else count += 2;
if (temp<1:1>) temp >>= 1; else count += 1;
if ((temp<0:0>) != 0x1) count += 1;
Rc = count;
}}, IntAluOp);
0x33: cttz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (!(temp<31:0>)) { temp >>= 32; count += 32; }
if (!(temp<15:0>)) { temp >>= 16; count += 16; }
if (!(temp<7:0>)) { temp >>= 8; count += 8; }
if (!(temp<3:0>)) { temp >>= 4; count += 4; }
if (!(temp<1:0>)) { temp >>= 2; count += 2; }
if (!(temp<0:0> & ULL(0x1))) count += 1;
Rc = count;
}}, IntAluOp);
format FailUnimpl {
0x30: ctpop();
0x31: perr();
0x34: unpkbw();
0x35: unpkbl();
0x36: pkwb();
0x37: pklb();
0x38: minsb8();
0x39: minsw4();
0x3a: minub8();
0x3b: minuw4();
0x3c: maxub8();
0x3d: maxuw4();
0x3e: maxsb8();
0x3f: maxsw4();
}
format BasicOperateWithNopCheck {
0x70: decode RB {
31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
}
0x78: decode RB {
31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
FloatCvtOp);
}
}
}
}
// Conditional branches.
format CondBranch {
0x39: beq({{ cond = (Ra == 0); }});
0x3d: bne({{ cond = (Ra != 0); }});
0x3e: bge({{ cond = (Ra.sq >= 0); }});
0x3f: bgt({{ cond = (Ra.sq > 0); }});
0x3b: ble({{ cond = (Ra.sq <= 0); }});
0x3a: blt({{ cond = (Ra.sq < 0); }});
0x38: blbc({{ cond = ((Ra & 1) == 0); }});
0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
0x31: fbeq({{ cond = (Fa == 0); }});
0x35: fbne({{ cond = (Fa != 0); }});
0x36: fbge({{ cond = (Fa >= 0); }});
0x37: fbgt({{ cond = (Fa > 0); }});
0x33: fble({{ cond = (Fa <= 0); }});
0x32: fblt({{ cond = (Fa < 0); }});
}
// unconditional branches
format UncondBranch {
0x30: br();
0x34: bsr(IsCall);
}
// indirect branches
0x1a: decode JMPFUNC {
format Jump {
0: jmp();
1: jsr(IsCall);
2: ret(IsReturn);
3: jsr_coroutine(IsCall, IsReturn);
}
}
// Square root and integer-to-FP moves
0x14: decode FP_SHORTFUNC {
// Integer to FP register moves must have RB == 31
0x4: decode RB {
31: decode FP_FULLFUNC {
format BasicOperateWithNopCheck {
0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
0x014: FailUnimpl::itoff(); // VAX-format conversion
}
}
}
// Square root instructions must have FA == 31
0xb: decode FA {
31: decode FP_TYPEFUNC {
format FloatingPointOperate {
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
if (Fb.sf < 0.0)
fault = new ArithmeticFault;
Fc.sf = sqrt(Fb.sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
}
}
// VAX-format sqrtf and sqrtg are not implemented
0xa: FailUnimpl::sqrtfg();
}
// IEEE floating point
0x16: decode FP_SHORTFUNC_TOP2 {
// The top two bits of the short function code break this
// space into four groups: binary ops, compares, reserved, and
// conversions. See Table 4-12 of AHB. There are different
// special cases in these different groups, so we decode on
// these top two bits first just to select a decode strategy.
// Most of these instructions may have various trapping and
// rounding mode flags set; these are decoded in the
// FloatingPointDecode template used by the
// FloatingPointOperate format.
// add/sub/mul/div: just decode on the short function code
// and source type. All valid trapping and rounding modes apply.
0: decode FP_TRAPMODE {
// check for valid trapping modes here
0,1,5,7: decode FP_TYPEFUNC {
format FloatingPointOperate {
#if SS_COMPATIBLE_FP
0x00: adds({{ Fc = Fa + Fb; }});
0x01: subs({{ Fc = Fa - Fb; }});
0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
#else
0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
#endif
0x20: addt({{ Fc = Fa + Fb; }});
0x21: subt({{ Fc = Fa - Fb; }});
0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
}
}
}
// Floating-point compare instructions must have the default
// rounding mode, and may use the default trapping mode or
// /SU. Both trapping modes are treated the same by M5; the
// only difference on the real hardware (as far a I can tell)
// is that without /SU you'd get an imprecise trap if you
// tried to compare a NaN with something else (instead of an
// "unordered" result).
1: decode FP_FULLFUNC {
format BasicOperateWithNopCheck {
0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
FloatCmpOp);
0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
FloatCmpOp);
0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
FloatCmpOp);
0x0a4, 0x5a4: cmptun({{ // unordered
Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
}}, FloatCmpOp);
}
}
// The FP-to-integer and integer-to-FP conversion insts
// require that FA be 31.
3: decode FA {
31: decode FP_TYPEFUNC {
format FloatingPointOperate {
0x2f: decode FP_ROUNDMODE {
format FPFixedRounding {
// "chopped" i.e. round toward zero
0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
Chopped);
// round to minus infinity
1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
MinusInfinity);
}
default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
}
// The cvtts opcode is overloaded to be cvtst if the trap
// mode is 2 or 6 (which are not valid otherwise)
0x2c: decode FP_FULLFUNC {
format BasicOperateWithNopCheck {
// trap on denorm version "cvtst/s" is
// simulated same as cvtst
0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
}
default: cvtts({{ Fc.sf = Fb; }});
}
// The trapping mode for integer-to-FP conversions
// must be /SUI or nothing; /U and /SU are not
// allowed. The full set of rounding modes are
// supported though.
0x3c: decode FP_TRAPMODE {
0,7: cvtqs({{ Fc.sf = Fb.sq; }});
}
0x3e: decode FP_TRAPMODE {
0,7: cvtqt({{ Fc = Fb.sq; }});
}
}
}
}
}
// misc FP operate
0x17: decode FP_FULLFUNC {
format BasicOperateWithNopCheck {
0x010: cvtlq({{
Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
}});
0x030: cvtql({{
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
}});
// We treat the precise & imprecise trapping versions of
// cvtql identically.
0x130, 0x530: cvtqlv({{
// To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb.uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
fault = new IntegerOverflowFault;
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
}});
0x020: cpys({{ // copy sign
Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
}});
0x021: cpysn({{ // copy sign negated
Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
}});
0x022: cpyse({{ // copy sign and exponent
Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
}});
0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
0x024: mt_fpcr({{ FPCR = Fa.uq; }});
0x025: mf_fpcr({{ Fa.uq = FPCR; }});
}
}
// miscellaneous mem-format ops
0x18: decode MEMFUNC {
format WarnUnimpl {
0x8000: fetch();
0xa000: fetch_m();
0xe800: ecb();
}
format MiscPrefetch {
0xf800: wh64({{ EA = Rb & ~ULL(63); }},
{{ xc->writeHint(EA, 64, memAccessFlags); }},
mem_flags = NO_FAULT,
inst_flags = [IsMemRef, IsDataPrefetch,
IsStore, MemWriteOp]);
}
format BasicOperate {
0xc000: rpcc({{
#if FULL_SYSTEM
/* Rb is a fake dependency so here is a fun way to get
* the parser to understand that.
*/
Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
#else
Ra = curTick;
#endif
}});
// All of the barrier instructions below do nothing in
// their execute() methods (hence the empty code blocks).
// All of their functionality is hard-coded in the
// pipeline based on the flags IsSerializing,
// IsMemBarrier, and IsWriteBarrier. In the current
// detailed CPU model, the execute() function only gets
// called at fetch, so there's no way to generate pipeline
// behavior at any other stage. Once we go to an
// exec-in-exec CPU model we should be able to get rid of
// these flags and implement this behavior via the
// execute() methods.
// trapb is just a barrier on integer traps, where excb is
// a barrier on integer and FP traps. "EXCB is thus a
// superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
// them the same though.
0x0000: trapb({{ }}, IsSerializing, No_OpClass);
0x0400: excb({{ }}, IsSerializing, No_OpClass);
0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
#if FULL_SYSTEM
format BasicOperate {
0xe000: rc({{
Ra = xc->readIntrFlag();
xc->setIntrFlag(0);
}}, IsNonSpeculative);
0xf000: rs({{
Ra = xc->readIntrFlag();
xc->setIntrFlag(1);
}}, IsNonSpeculative);
}
#else
format FailUnimpl {
0xe000: rc();
0xf000: rs();
}
#endif
}
#if FULL_SYSTEM
0x00: CallPal::call_pal({{
if (!palValid ||
(palPriv
&& xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
fault = new UnimplementedOpcodeFault;
}
else {
// check to see if simulator wants to do something special
// on this PAL call (including maybe suppress it)
bool dopal = xc->simPalCheck(palFunc);
if (dopal) {
xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
}
}
}}, IsNonSpeculative);
#else
0x00: decode PALFUNC {
format EmulatedCallPal {
0x00: halt ({{
SimExit(curTick, "halt instruction encountered");
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall();
}}, IsNonSpeculative);
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});
// Write uniq reg with value from ABI arg register (r16)
0x9f: wruniq({{ Runiq = R16; }});
}
}
#endif
#if FULL_SYSTEM
0x1b: decode PALMODE {
0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD {
format HwLoad {
0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
}
}
}
0x1f: decode PALMODE {
0: OpcdecFault::hw_st_cond();
format HwStore {
1: decode HW_LDST_COND {
0: decode HW_LDST_QUAD {
0: hw_st({{ EA = (Rb + disp) & ~3; }},
{{ Mem.ul = Ra<31:0>; }}, L);
1: hw_st({{ EA = (Rb + disp) & ~7; }},
{{ Mem.uq = Ra.uq; }}, Q);
}
1: FailUnimpl::hw_st_cond();
}
}
}
0x19: decode PALMODE {
0: OpcdecFault::hw_mfpr();
format HwMoveIPR {
1: hw_mfpr({{
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
}});
}
}
0x1d: decode PALMODE {
0: OpcdecFault::hw_mtpr();
format HwMoveIPR {
1: hw_mtpr({{
xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
}});
}
}
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
}
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
AlphaPseudo::arm(xc->xcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
AlphaPseudo::quiesce(xc->xcBase());
}}, IsNonSpeculative);
0x02: quiesceNs({{
AlphaPseudo::quiesceNs(xc->xcBase(), R16);
}}, IsNonSpeculative);
0x03: quiesceCycles({{
AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
}}, IsNonSpeculative);
0x04: quiesceTime({{
R0 = AlphaPseudo::quiesceTime(xc->xcBase());
}}, IsNonSpeculative);
0x10: ivlb({{
AlphaPseudo::ivlb(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
0x11: ivle({{
AlphaPseudo::ivle(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
0x20: m5exit_old({{
AlphaPseudo::m5exit_old(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
AlphaPseudo::m5exit(xc->xcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
AlphaPseudo::debugbreak(xc->xcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
AlphaPseudo::switchcpu(xc->xcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called.");
}}, IsNonSpeculative);
}
}
#endif
}

301
arch/alpha/isa/fp.isa Normal file
View file

@ -0,0 +1,301 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output exec {{
/// Check "FP enabled" machine status bit. Called when executing any FP
/// instruction in full-system mode.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
fault = new FloatEnableFault;
}
return fault;
}
#else
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
return NoFault;
}
#endif
}};
output header {{
/**
* Base class for general floating-point instructions. Includes
* support for various Alpha rounding and trapping modes. Only FP
* instructions that require this support are derived from this
* class; the rest derive directly from AlphaStaticInst.
*/
class AlphaFP : public AlphaStaticInst
{
public:
/// Alpha FP rounding modes.
enum RoundingMode {
Chopped = 0, ///< round toward zero
Minus_Infinity = 1, ///< round toward minus infinity
Normal = 2, ///< round to nearest (default)
Dynamic = 3, ///< use FPCR setting (in instruction)
Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
};
/// Alpha FP trapping modes.
/// For instructions that produce integer results, the
/// "Underflow Enable" modes really mean "Overflow Enable", and
/// the assembly modifier is V rather than U.
enum TrappingMode {
/// default: nothing enabled
Imprecise = 0, ///< no modifier
/// underflow/overflow traps enabled, inexact disabled
Underflow_Imprecise = 1, ///< /U or /V
Underflow_Precise = 5, ///< /SU or /SV
/// underflow/overflow and inexact traps enabled
Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
};
protected:
/// Map Alpha rounding mode to C99 constants from <fenv.h>.
static const int alphaToC99RoundingMode[];
/// Map enum RoundingMode values to disassembly suffixes.
static const char *roundingModeSuffix[];
/// Map enum TrappingMode values to FP disassembly suffixes.
static const char *fpTrappingModeSuffix[];
/// Map enum TrappingMode values to integer disassembly suffixes.
static const char *intTrappingModeSuffix[];
/// This instruction's rounding mode.
RoundingMode roundingMode;
/// This instruction's trapping mode.
TrappingMode trappingMode;
/// Have we warned about this instruction's unsupported
/// rounding mode (if applicable)?
mutable bool warnedOnRounding;
/// Have we warned about this instruction's unsupported
/// trapping mode (if applicable)?
mutable bool warnedOnTrapping;
/// Constructor
AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
roundingMode((enum RoundingMode)FP_ROUNDMODE),
trappingMode((enum TrappingMode)FP_TRAPMODE),
warnedOnRounding(false),
warnedOnTrapping(false)
{
}
int getC99RoundingMode(uint64_t fpcr_val) const;
// This differs from the AlphaStaticInst version only in
// printing suffixes for non-default rounding & trapping modes.
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
int
AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
{
if (roundingMode == Dynamic) {
return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
}
else {
return alphaToC99RoundingMode[roundingMode];
}
}
std::string
AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::string mnem_str(mnemonic);
#ifndef SS_COMPATIBLE_DISASSEMBLY
std::string suffix("");
suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
? fpTrappingModeSuffix[trappingMode]
: intTrappingModeSuffix[trappingMode]);
suffix += roundingModeSuffix[roundingMode];
if (suffix != "") {
mnem_str = csprintf("%s/%s", mnemonic, suffix);
}
#endif
std::stringstream ss;
ccprintf(ss, "%-10s ", mnem_str.c_str());
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
}
if (_numSrcRegs > 1) {
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
// just print the first dest... if there's a second one,
// it's generally implicit
if (_numDestRegs > 0) {
if (_numSrcRegs > 0)
ss << ",";
printReg(ss, _destRegIdx[0]);
}
return ss.str();
}
const int AlphaFP::alphaToC99RoundingMode[] = {
FE_TOWARDZERO, // Chopped
FE_DOWNWARD, // Minus_Infinity
FE_TONEAREST, // Normal
FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
// mark invalid trapping modes, but don't fail on them, because
// you could decode anything on a misspeculated path
const char *AlphaFP::fpTrappingModeSuffix[] =
{ "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
const char *AlphaFP::intTrappingModeSuffix[] =
{ "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
}};
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
warn("%s: non-standard trapping mode not supported",
generateDisassembly(0, NULL));
warnedOnTrapping = true;
}
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
#if USE_FENV
if (roundingMode == Normal) {
%(code)s;
} else {
fesetround(getC99RoundingMode(
xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
%(code)s;
fesetround(FE_TONEAREST);
}
#else
if (roundingMode != Normal && !warnedOnRounding) {
warn("%s: non-standard rounding mode not supported",
generateDisassembly(0, NULL));
warnedOnRounding = true;
}
%(code)s;
#endif
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
// FP instruction class execute method template where no dynamic
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
warn("%s: non-standard trapping mode not supported",
generateDisassembly(0, NULL));
warnedOnTrapping = true;
}
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template FloatingPointDecode {{
{
AlphaStaticInst *i = new %(class_name)s(machInst);
if (FC == 31) {
i = makeNop(i);
}
return i;
}
}};
// General format for floating-point operate instructions:
// - Checks trapping and rounding mode flags. Trapping modes
// currently unimplemented (will fail).
// - Generates NOP if FC == 31.
def format FloatingPointOperate(code, *opt_args) {{
iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
decode_block = FloatingPointDecode.subst(iop)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = FloatingPointExecute.subst(iop)
}};
// Special format for cvttq where rounding mode is pre-decoded
def format FPFixedRounding(code, class_suffix, *opt_args) {{
Name += class_suffix
iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
decode_block = FloatingPointDecode.subst(iop)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = FPFixedRoundingExecute.subst(iop)
}};

128
arch/alpha/isa/int.isa Normal file
View file

@ -0,0 +1,128 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Base class for integer immediate instructions.
*/
class IntegerImm : public AlphaStaticInst
{
protected:
/// Immediate operand value (unsigned 8-bit int).
uint8_t imm;
/// Constructor
IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
{
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// just print the first source reg... if there's
// a second one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
}
ss << (int)imm;
if (_numDestRegs > 0) {
ss << ",";
printReg(ss, _destRegIdx[0]);
}
return ss.str();
}
}};
def template RegOrImmDecode {{
{
AlphaStaticInst *i =
(IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
: (AlphaStaticInst *)new %(class_name)s(machInst);
if (RC == 31) {
i = makeNop(i);
}
return i;
}
}};
// Primary format for integer operate instructions:
// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
// - Generates NOP if RC == 31.
def format IntegerOperate(code, *opt_flags) {{
# If the code block contains 'Rb_or_imm', we define two instructions,
# one using 'Rb' and one using 'imm', and have the decoder select
# the right one.
uses_imm = (code.find('Rb_or_imm') != -1)
if uses_imm:
orig_code = code
# base code is reg version:
# rewrite by substituting 'Rb' for 'Rb_or_imm'
code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
# generate immediate version by substituting 'imm'
# note that imm takes no extenstion, so we extend
# the regexp to replace any extension as well
imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
# generate declaration for register version
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BasicExecute.subst(iop)
if uses_imm:
# append declaration for imm version
imm_cblk = CodeBlock(imm_code)
imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += BasicExecute.subst(imm_iop)
# decode checks IMM bit to pick correct version
decode_block = RegOrImmDecode.subst(iop)
else:
# no imm version: just check for nop
decode_block = OperateNopCheckDecode.subst(iop)
}};

448
arch/alpha/isa/main.isa Normal file
View file

@ -0,0 +1,448 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
#include <sstream>
#include <iostream>
#include <iomanip>
#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
#include "arch/alpha/faults.hh"
#include "mem/request.hh" // some constructors use MemReq flags
}};
output decoder {{
#include "base/cprintf.hh"
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include <math.h>
using namespace AlphaISA;
}};
output exec {{
#include <math.h>
#if FULL_SYSTEM
#include "sim/pseudo_inst.hh"
#endif
#include "base/fenv.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
using namespace AlphaISA;
}};
////////////////////////////////////////////////////////////////////
//
// Namespace statement. Everything below this line will be in the
// AlphaISAInst namespace.
//
namespace AlphaISA;
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
// Universal (format-independent) fields
def bitfield PALMODE <32:32>;
def bitfield OPCODE <31:26>;
def bitfield RA <25:21>;
def bitfield RB <20:16>;
// Memory format
def signed bitfield MEMDISP <15: 0>; // displacement
def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
// Memory-format jumps
def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
// Branch format
def signed bitfield BRDISP <20: 0>; // displacement
// Integer operate format(s>;
def bitfield INTIMM <20:13>; // integer immediate (literal)
def bitfield IMM <12:12>; // immediate flag
def bitfield INTFUNC <11: 5>; // function code
def bitfield RC < 4: 0>; // dest reg
// Floating-point operate format
def bitfield FA <25:21>;
def bitfield FB <20:16>;
def bitfield FP_FULLFUNC <15: 5>; // complete function code
def bitfield FP_TRAPMODE <15:13>; // trapping mode
def bitfield FP_ROUNDMODE <12:11>; // rounding mode
def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
def bitfield FP_SRCTYPE <10: 9>; // source reg type
def bitfield FP_SHORTFUNC < 8: 5>; // short function code
def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
def bitfield FC < 4: 0>; // dest reg
// PALcode format
def bitfield PALFUNC <25: 0>; // function code
// EV5 PAL instructions:
// HW_LD/HW_ST
def bitfield HW_LDST_PHYS <15>; // address is physical
def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
// HW_REI
def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
def bitfield HW_REI_MBZ <13: 0>; // must be zero
// HW_MTPR/MW_MFPR
def bitfield HW_IPR_IDX <15:0>; // IPR index
// M5 instructions
def bitfield M5FUNC <7:0>;
def operand_types {{
'sb' : ('signed int', 8),
'ub' : ('unsigned int', 8),
'sw' : ('signed int', 16),
'uw' : ('unsigned int', 16),
'sl' : ('signed int', 32),
'ul' : ('unsigned int', 32),
'sq' : ('signed int', 64),
'uq' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64)
}};
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
'IsInteger', 1),
'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
'IsInteger', 2),
'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
'IsInteger', 3),
'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
'R17': ('IntReg', 'uq', '17', None, 1),
'R18': ('IntReg', 'uq', '18', None, 1)
}};
////////////////////////////////////////////////////////////////////
//
// Basic instruction classes/templates/formats etc.
//
output header {{
// uncomment the following to get SimpleScalar-compatible disassembly
// (useful for diffing output traces).
// #define SS_COMPATIBLE_DISASSEMBLY
/**
* Base class for all Alpha static instructions.
*/
class AlphaStaticInst : public StaticInst
{
protected:
/// Make AlphaISA register dependence tags directly visible in
/// this class and derived classes. Maybe these should really
/// live here and not in the AlphaISA namespace.
enum DependenceTags {
FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
Uniq_DepTag = AlphaISA::Uniq_DepTag,
Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
};
/// Constructor.
AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: StaticInst(mnem, _machInst, __opClass)
{
}
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void printReg(std::ostream &os, int reg) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
void
AlphaStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
}
else {
ccprintf(os, "f%d", reg - FP_Base_DepTag);
}
}
std::string
AlphaStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
}
if (_numSrcRegs > 1) {
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
// just print the first dest... if there's a second one,
// it's generally implicit
if (_numDestRegs > 0) {
if (_numSrcRegs > 0)
ss << ",";
printReg(ss, _destRegIdx[0]);
}
return ss.str();
}
}};
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
def template BasicDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
}
}};
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
// Basic decode template.
def template BasicDecode {{
return new %(class_name)s(machInst);
}};
// Basic decode template, passing mnemonic in as string arg to constructor.
def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
////////////////////////////////////////////////////////////////////
//
// Nop
//
output header {{
/**
* Static instruction class for no-ops. This is a leaf class.
*/
class Nop : public AlphaStaticInst
{
/// Disassembly of original instruction.
const std::string originalDisassembly;
public:
/// Constructor
Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
: AlphaStaticInst("nop", _machInst, No_OpClass),
originalDisassembly(_originalDisassembly)
{
flags[IsNop] = true;
}
~Nop() { }
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
%(BasicExecDeclare)s
};
/// Helper function for decoding nops. Substitute Nop object
/// for original inst passed in as arg (and delete latter).
static inline
AlphaStaticInst *
makeNop(AlphaStaticInst *inst)
{
AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
delete inst;
return nop;
}
}};
output decoder {{
std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return originalDisassembly;
#else
return csprintf("%-10s (%s)", "nop", originalDisassembly);
#endif
}
}};
output exec {{
Fault
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
return NoFault;
}
}};
// integer & FP operate instructions use Rc as dest, so check for
// Rc == 31 to detect nops
def template OperateNopCheckDecode {{
{
AlphaStaticInst *i = new %(class_name)s(machInst);
if (RC == 31) {
i = makeNop(i);
}
return i;
}
}};
// Like BasicOperate format, but generates NOP if RC/FC == 31
def format BasicOperateWithNopCheck(code, *opt_args) {{
iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
opt_args)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = OperateNopCheckDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
// Integer instruction templates, formats, etc.
##include "m5/arch/alpha/isa/int.isa"
// Floating-point instruction templates, formats, etc.
##include "m5/arch/alpha/isa/fp.isa"
// Memory instruction templates, formats, etc.
##include "m5/arch/alpha/isa/mem.isa"
// Branch/jump instruction templates, formats, etc.
##include "m5/arch/alpha/isa/branch.isa"
// PAL instruction templates, formats, etc.
##include "m5/arch/alpha/isa/pal.isa"
// Opcdec fault instruction templates, formats, etc.
##include "m5/arch/alpha/isa/opcdec.isa"
// Unimplemented instruction templates, formats, etc.
##include "m5/arch/alpha/isa/unimp.isa"
// Unknown instruction templates, formats, etc.
##include "m5/arch/alpha/isa/unknown.isa"
// Execution utility functions
##include "m5/arch/alpha/isa/util.isa"
// The actual decoder
##include "m5/arch/alpha/isa/decoder.isa"

702
arch/alpha/isa/mem.isa Normal file
View file

@ -0,0 +1,702 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Base class for general Alpha memory-format instructions.
*/
class Memory : public AlphaStaticInst
{
protected:
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
/// Pointer to EAComp object.
const StaticInstPtr eaCompPtr;
/// Pointer to MemAcc object.
const StaticInstPtr memAccPtr;
/// Constructor
Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: AlphaStaticInst(mnem, _machInst, __opClass),
memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
{
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
public:
const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
const StaticInstPtr &memAccInst() const { return memAccPtr; }
};
/**
* Base class for memory-format instructions using a 32-bit
* displacement (i.e. most of them).
*/
class MemoryDisp32 : public Memory
{
protected:
/// Displacement for EA calculation (signed).
int32_t disp;
/// Constructor.
MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
disp(MEMDISP)
{
}
};
/**
* Base class for a few miscellaneous memory-format insts
* that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
* None of these instructions has a destination register either.
*/
class MemoryNoDisp : public Memory
{
protected:
/// Constructor
MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
{
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
}
std::string
MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (r%d)", mnemonic, RB);
}
}};
def format LoadAddress(code) {{
iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def template LoadStoreDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
protected:
/**
* "Fake" effective address computation class for "%(mnemonic)s".
*/
class EAComp : public %(base_class)s
{
public:
/// Constructor
EAComp(ExtMachInst machInst);
%(BasicExecDeclare)s
};
/**
* "Fake" memory access instruction class for "%(mnemonic)s".
*/
class MemAcc : public %(base_class)s
{
public:
/// Constructor
MemAcc(ExtMachInst machInst);
%(BasicExecDeclare)s
};
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
};
}};
def template InitiateAccDeclare {{
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template LoadStoreConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(ea_constructor)s;
}
inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(memacc_constructor)s;
}
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
{
%(constructor)s;
}
}};
def template EACompExecute {{
Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
xc->setEA(EA);
}
return fault;
}
}};
def template LoadMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
}
return fault;
}
}};
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
%(op_dest_decl)s;
memcpy(&Mem, data, sizeof(Mem));
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == NoFault) {
%(code)s;
}
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_src_decl)s;
%(op_dest_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
return fault;
}
}};
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_dest_decl)s;
memcpy(&write_result, data, sizeof(write_result));
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template MiscMemAccExecute {{
Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == NoFault) {
%(code)s;
}
return NoFault;
}
}};
def template MiscExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(memacc_code)s;
}
return NoFault;
}
}};
def template MiscInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
return NoFault;
}
}};
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
return NoFault;
}
}};
// load instructions use Ra as dest, so check for
// Ra == 31 to detect nops
def template LoadNopCheckDecode {{
{
AlphaStaticInst *i = new %(class_name)s(machInst);
if (RA == 31) {
i = makeNop(i);
}
return i;
}
}};
// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
def template LoadPrefetchCheckDecode {{
{
if (RA != 31) {
return new %(class_name)s(machInst);
}
else {
return new %(class_name)sPrefetch(machInst);
}
}
}};
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
postacc_code = '', base_class = 'MemoryDisp32',
decode_template = BasicDecode, exec_template_base = ''):
# Make sure flags are in lists (convert to lists if not).
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
# add hook to get effective addresses into execution trace output.
ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
# generate code block objects
ea_cblk = CodeBlock(ea_code)
memacc_cblk = CodeBlock(memacc_code)
postacc_cblk = CodeBlock(postacc_code)
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
# to generate three StaticInst objects. Note that the latter two
# are nested inside the larger "atomic" one.
# generate InstObjParams for EAComp object
ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
# generate InstObjParams for MemAcc object
memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
# in the split execution model, the MemAcc portion is responsible
# for the post-access code.
memacc_iop.postacc_code = postacc_cblk.code
# generate InstObjParams for InitiateAcc, CompleteAcc object
# The code used depends on the template being used
if (exec_template_base == 'Load'):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(memacc_code + postacc_code)
elif (exec_template_base == 'Store'):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(postacc_code)
else:
initiateacc_cblk = ''
completeacc_cblk = ''
initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
inst_flags)
completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
inst_flags)
if (exec_template_base == 'Load'):
initiateacc_iop.ea_code = ea_cblk.code
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
elif (exec_template_base == 'Store'):
initiateacc_iop.ea_code = ea_cblk.code
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
# generate InstObjParams for unified execution
cblk = CodeBlock(ea_code + memacc_code + postacc_code)
iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
iop.ea_constructor = ea_cblk.constructor
iop.ea_code = ea_cblk.code
iop.memacc_constructor = memacc_cblk.constructor
iop.memacc_code = memacc_cblk.code
iop.postacc_code = postacc_cblk.code
if mem_flags:
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s
memacc_iop.constructor += s
# select templates
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
EACompExecute.subst(ea_iop)
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(initiateacc_iop)
+ completeAccTemplate.subst(completeacc_iop))
}};
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = LoadNopCheckDecode,
exec_template_base = 'Load')
}};
// Note that the flags passed in apply only to the prefetch version
def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
mem_flags = [], pf_flags = [], inst_flags = []) {{
# declare the load instruction object and generate the decode block
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = LoadPrefetchCheckDecode,
exec_template_base = 'Load')
# Declare the prefetch instruction object.
# Make sure flag args are lists so we can mess with them.
mem_flags = makeList(mem_flags)
pf_flags = makeList(pf_flags)
inst_flags = makeList(inst_flags)
pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
'IsDataPrefetch', 'MemReadOp']
(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
LoadStoreBase(name, Name + 'Prefetch', ea_code,
'xc->prefetch(EA, memAccessFlags);',
pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
header_output += pf_header_output
decoder_output += pf_decoder_output
exec_output += pf_exec_output
}};
def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
exec_template_base = 'Store')
}};
def format StoreCond(memacc_code, postacc_code,
ea_code = {{ EA = Rb + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
postacc_code, exec_template_base = 'Store')
}};
// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
def format MiscPrefetch(ea_code, memacc_code,
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
}};

72
arch/alpha/isa/opcdec.isa Normal file
View file

@ -0,0 +1,72 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Static instruction class for instructions that cause an OPCDEC fault
* when executed. This is currently only for PAL mode instructions
* executed in non-PAL mode.
*/
class OpcdecFault : public AlphaStaticInst
{
public:
/// Constructor
OpcdecFault(ExtMachInst _machInst)
: AlphaStaticInst("opcdec fault", _machInst, No_OpClass)
{
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
" OPCDEC fault", machInst, OPCODE);
}
}};
output exec {{
Fault
OpcdecFault::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
return new UnimplementedOpcodeFault;
}
}};
def format OpcdecFault() {{
decode_block = 'return new OpcdecFault(machInst);\n'
}};

271
arch/alpha/isa/pal.isa Normal file
View file

@ -0,0 +1,271 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Base class for emulated call_pal calls (used only in
* non-full-system mode).
*/
class EmulatedCallPal : public AlphaStaticInst
{
protected:
/// Constructor.
EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass)
{
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
EmulatedCallPal::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%s %s", "call_pal", mnemonic);
#else
return csprintf("%-10s %s", "call_pal", mnemonic);
#endif
}
}};
def format EmulatedCallPal(code, *flags) {{
iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
output header {{
/**
* Base class for full-system-mode call_pal instructions.
* Probably could turn this into a leaf class and get rid of the
* parser template.
*/
class CallPalBase : public AlphaStaticInst
{
protected:
int palFunc; ///< Function code part of instruction
int palOffset; ///< Target PC, offset from IPR_PAL_BASE
bool palValid; ///< is the function code valid?
bool palPriv; ///< is this call privileged?
/// Constructor.
CallPalBase(const char *mnem, ExtMachInst _machInst,
OpClass __opClass);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
inline
CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
palFunc(PALFUNC)
{
// From the 21164 HRM (paraphrased):
// Bit 7 of the function code (mask 0x80) indicates
// whether the call is privileged (bit 7 == 0) or
// unprivileged (bit 7 == 1). The privileged call table
// starts at 0x2000, the unprivielged call table starts at
// 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
// offset.
const int palPrivMask = 0x80;
const int palOffsetMask = 0x3f;
// Pal call is invalid unless all other bits are 0
palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
palPriv = ((machInst & palPrivMask) == 0);
int shortPalFunc = (machInst & palOffsetMask);
// Add 1 to base to set pal-mode bit
palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
}
std::string
CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %#x", "call_pal", palFunc);
}
}};
def format CallPal(code, *flags) {{
iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
////////////////////////////////////////////////////////////////////
//
// hw_ld, hw_st
//
output header {{
/**
* Base class for hw_ld and hw_st.
*/
class HwLoadStore : public Memory
{
protected:
/// Displacement for EA calculation (signed).
int16_t disp;
/// Constructor
HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
inline
HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
OpClass __opClass,
StaticInstPtr _eaCompPtr,
StaticInstPtr _memAccPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
disp(HW_LDST_DISP)
{
memAccessFlags = 0;
if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
if (HW_LDST_VPTE) memAccessFlags |= VPTE;
if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
}
std::string
HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
#else
// HW_LDST_LOCK and HW_LDST_COND are the same bit.
const char *lock_str =
(HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
mnemonic, RA, disp, RB,
HW_LDST_PHYS ? ",PHYS" : "",
HW_LDST_ALT ? ",ALT" : "",
HW_LDST_QUAD ? ",QUAD" : "",
HW_LDST_VPTE ? ",VPTE" : "",
lock_str);
#endif
}
}};
def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
mem_flags = [], inst_flags = flags,
base_class = 'HwLoadStore', exec_template_base = 'Load')
}};
def format HwStore(ea_code, memacc_code, class_ext, *flags) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
mem_flags = [], inst_flags = flags,
base_class = 'HwLoadStore', exec_template_base = 'Store')
}};
def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext,
*flags) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
postacc_code, mem_flags = [], inst_flags = flags,
base_class = 'HwLoadStore')
}};
output header {{
/**
* Base class for hw_mfpr and hw_mtpr.
*/
class HwMoveIPR : public AlphaStaticInst
{
protected:
/// Index of internal processor register.
int ipr_index;
/// Constructor
HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
ipr_index(HW_IPR_IDX)
{
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
if (_numSrcRegs > 0) {
// must be mtpr
return csprintf("%-10s r%d,IPR(%#x)",
mnemonic, RA, ipr_index);
}
else {
// must be mfpr
return csprintf("%-10s IPR(%#x),r%d",
mnemonic, ipr_index, RA);
}
}
}};
def format HwMoveIPR(code) {{
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
['IprAccessOp'])
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

165
arch/alpha/isa/unimp.isa Normal file
View file

@ -0,0 +1,165 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Static instruction class for unimplemented instructions that
* cause simulator termination. Note that these are recognized
* (legal) instructions that the simulator does not support; the
* 'Unknown' class is used for unrecognized/illegal instructions.
* This is a leaf class.
*/
class FailUnimplemented : public AlphaStaticInst
{
public:
/// Constructor
FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for unimplemented instructions that cause a warning
* to be printed (but do not terminate simulation). This
* implementation is a little screwy in that it will print a
* warning for each instance of a particular unimplemented machine
* instruction, not just for each unimplemented opcode. Should
* probably make the 'warned' flag a static member of the derived
* class.
*/
class WarnUnimplemented : public AlphaStaticInst
{
private:
/// Have we warned on this instruction yet?
mutable bool warned;
public:
/// Constructor
WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
FailUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%-10s", mnemonic);
#else
return csprintf("%-10s (unimplemented)", mnemonic);
#endif
}
}};
output exec {{
Fault
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
return new UnimplementedOpcodeFault;
}
Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);
warned = true;
}
return NoFault;
}
}};
def format FailUnimpl() {{
iop = InstObjParams(name, 'FailUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
output header {{
/**
* Static instruction class for unknown (illegal) instructions.
* These cause simulator termination if they are executed in a
* non-speculative mode. This is a leaf class.
*/
class Unknown : public AlphaStaticInst
{
public:
/// Constructor
Unknown(ExtMachInst _machInst)
: AlphaStaticInst("unknown", _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};

52
arch/alpha/isa/unknown.isa Normal file
View file

@ -0,0 +1,52 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output decoder {{
std::string
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
"unknown", machInst, OPCODE);
}
}};
output exec {{
Fault
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
return new UnimplementedOpcodeFault;
}
}};
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

112
arch/alpha/isa/util.isa Normal file
View file

@ -0,0 +1,112 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output exec {{
/// Return opa + opb, summing carry into third arg.
inline uint64_t
addc(uint64_t opa, uint64_t opb, int &carry)
{
uint64_t res = opa + opb;
if (res < opa || res < opb)
++carry;
return res;
}
/// Multiply two 64-bit values (opa * opb), returning the 128-bit
/// product in res_hi and res_lo.
inline void
mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
{
// do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
uint64_t opa_hi = opa<63:32>;
uint64_t opa_lo = opa<31:0>;
uint64_t opb_hi = opb<63:32>;
uint64_t opb_lo = opb<31:0>;
res_lo = opa_lo * opb_lo;
// The middle partial products logically belong in bit
// positions 95 to 32. Thus the lower 32 bits of each product
// sum into the upper 32 bits of the low result, while the
// upper 32 sum into the low 32 bits of the upper result.
uint64_t partial1 = opa_hi * opb_lo;
uint64_t partial2 = opa_lo * opb_hi;
uint64_t partial1_lo = partial1<31:0> << 32;
uint64_t partial1_hi = partial1<63:32>;
uint64_t partial2_lo = partial2<31:0> << 32;
uint64_t partial2_hi = partial2<63:32>;
// Add partial1_lo and partial2_lo to res_lo, keeping track
// of any carries out
int carry_out = 0;
res_lo = addc(partial1_lo, res_lo, carry_out);
res_lo = addc(partial2_lo, res_lo, carry_out);
// Now calculate the high 64 bits...
res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
}
/// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
/// See Table 2-2 of Alpha AHB.
inline int
map_s(int old_exp)
{
int hibit = old_exp<7:>;
int lobits = old_exp<6:0>;
if (hibit == 1) {
return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
}
else {
return (lobits == 0) ? 0 : (0x380 | lobits);
}
}
/// Convert a 32-bit S-floating value to the equivalent 64-bit
/// representation to be stored in an FP reg.
inline uint64_t
s_to_t(uint32_t s_val)
{
uint64_t tmp = s_val;
return (tmp<31:> << 63 // sign bit
| (uint64_t)map_s(tmp<30:23>) << 52 // exponent
| tmp<22:0> << 29); // fraction
}
/// Convert a 64-bit T-floating value to the equivalent 32-bit
/// S-floating representation to be stored in memory.
inline int32_t
t_to_s(uint64_t t_val)
{
return (t_val<63:62> << 30 // sign bit & hi exp bit
| t_val<58:29>); // rest of exp & fraction
}
}};

2737
arch/alpha/isa_desc
View file

File diff suppressed because it is too large Load diff

328
arch/alpha/isa_traits.hh
View file

@ -29,81 +29,131 @@
#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
#define __ARCH_ALPHA_ISA_TRAITS_HH__
#include "arch/alpha/faults.hh"
namespace LittleEndianGuest {}
using namespace LittleEndianGuest;
//#include "arch/alpha/faults.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
#include "sim/faults.hh"
class ExecContext;
class FastCPU;
class FullCPU;
class Checkpoint;
#define TARGET_ALPHA
template <class ISA> class StaticInst;
template <class ISA> class StaticInstPtr;
class StaticInst;
class StaticInstPtr;
namespace EV5 {
int DTB_ASN_ASN(uint64_t reg);
int ITB_ASN_ASN(uint64_t reg);
}
class AlphaISA
#if !FULL_SYSTEM
class SyscallReturn {
public:
template <class T>
SyscallReturn(T v, bool s)
{
retval = (uint64_t)v;
success = s;
}
template <class T>
SyscallReturn(T v)
{
success = (v >= 0);
retval = (uint64_t)v;
}
~SyscallReturn() {}
SyscallReturn& operator=(const SyscallReturn& s) {
retval = s.retval;
success = s.success;
return *this;
}
bool successful() { return success; }
uint64_t value() { return retval; }
private:
uint64_t retval;
bool success;
};
#endif
namespace AlphaISA
{
public:
typedef uint32_t MachInst;
typedef uint64_t Addr;
typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
enum {
MemoryEnd = 0xffffffffffffffffULL,
const int NumIntArchRegs = 32;
const int NumPALShadowRegs = 8;
const int NumFloatArchRegs = 32;
// @todo: Figure out what this number really should be.
const int NumMiscArchRegs = 32;
NumIntRegs = 32,
NumFloatRegs = 32,
NumMiscRegs = 32,
// Static instruction parameters
const int MaxInstSrcRegs = 3;
const int MaxInstDestRegs = 2;
MaxRegsOfAnyType = 32,
// Static instruction parameters
MaxInstSrcRegs = 3,
MaxInstDestRegs = 2,
// semantically meaningful register indices
const int ZeroReg = 31; // architecturally meaningful
// the rest of these depend on the ABI
const int StackPointerReg = 30;
const int GlobalPointerReg = 29;
const int ProcedureValueReg = 27;
const int ReturnAddressReg = 26;
const int ReturnValueReg = 0;
const int FramePointerReg = 15;
const int ArgumentReg0 = 16;
const int ArgumentReg1 = 17;
const int ArgumentReg2 = 18;
const int ArgumentReg3 = 19;
const int ArgumentReg4 = 20;
const int ArgumentReg5 = 21;
const int SyscallNumReg = ReturnValueReg;
const int SyscallPseudoReturnReg = ArgumentReg4;
const int SyscallSuccessReg = 19;
// semantically meaningful register indices
ZeroReg = 31, // architecturally meaningful
// the rest of these depend on the ABI
StackPointerReg = 30,
GlobalPointerReg = 29,
ProcedureValueReg = 27,
ReturnAddressReg = 26,
ReturnValueReg = 0,
FramePointerReg = 15,
ArgumentReg0 = 16,
ArgumentReg1 = 17,
ArgumentReg2 = 18,
ArgumentReg3 = 19,
ArgumentReg4 = 20,
ArgumentReg5 = 21,
LogVMPageSize = 13, // 8K bytes
VMPageSize = (1 << LogVMPageSize),
BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
WordBytes = 4,
HalfwordBytes = 2,
ByteBytes = 1,
DepNA = 0,
};
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
const int WordBytes = 4;
const int HalfwordBytes = 2;
const int ByteBytes = 1;
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
const int NumMiscRegs = NumMiscArchRegs;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 64,
Fpcr_DepTag = 64, // floating point control register
Uniq_DepTag = 65,
IPR_Base_DepTag = 66
FP_Base_DepTag = 40,
Ctrl_Base_DepTag = 72,
Fpcr_DepTag = 72, // floating point control register
Uniq_DepTag = 73,
Lock_Flag_DepTag = 74,
Lock_Addr_DepTag = 75,
IPR_Base_DepTag = 76
};
typedef uint64_t IntReg;
@ -120,19 +170,13 @@ class AlphaISA
double d[NumFloatRegs]; // double-precision floating point view
} FloatRegFile;
// control register file contents
typedef uint64_t MiscReg;
typedef struct {
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
} MiscRegFile;
extern const Addr PageShift;
extern const Addr PageBytes;
extern const Addr PageMask;
extern const Addr PageOffset;
static const Addr PageShift = 13;
static const Addr PageBytes = ULL(1) << PageShift;
static const Addr PageMask = ~(PageBytes - 1);
static const Addr PageOffset = PageBytes - 1;
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];
#if FULL_SYSTEM
@ -141,19 +185,53 @@ static const Addr PageOffset = PageBytes - 1;
#include "arch/alpha/isa_fullsys_traits.hh"
#else
enum {
NumInternalProcRegs = 0
};
const int NumInternalProcRegs = 0;
#endif
enum {
TotalNumRegs =
NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
// control register file contents
typedef uint64_t MiscReg;
class MiscRegFile {
protected:
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
public:
MiscReg readReg(int misc_reg);
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
Fault setReg(int misc_reg, const MiscReg &val);
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc);
void copyMiscRegs(ExecContext *xc);
#if FULL_SYSTEM
protected:
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
Fault setIpr(int idx, uint64_t val, ExecContext *xc);
void copyIprs(ExecContext *xc);
#endif
friend class RegFile;
};
enum {
TotalDataRegs = NumIntRegs + NumFloatRegs
};
const int TotalNumRegs = NumIntRegs + NumFloatRegs +
NumMiscRegs + NumInternalProcRegs;
const int TotalDataRegs = NumIntRegs + NumFloatRegs;
typedef union {
IntReg intreg;
@ -167,23 +245,26 @@ static const Addr PageOffset = PageBytes - 1;
MiscRegFile miscRegs; // control register file
Addr pc; // program counter
Addr npc; // next-cycle program counter
Addr nnpc;
#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
inline int instAsid()
{ return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
inline int dataAsid()
{ return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
#endif // FULL_SYSTEM
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
StaticInstPtr decodeInst(ExtMachInst);
// return a no-op instruction... used for instruction fetch faults
static const MachInst NoopMachInst;
extern const ExtMachInst NoopMachInst;
enum annotes {
ANNOTE_NONE = 0,
@ -238,10 +319,10 @@ static const Addr PageOffset = PageBytes - 1;
// Machine operations
static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
int regnum);
static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
void restoreMachineReg(RegFile &regs, const AnyReg &reg,
int regnum);
#if 0
@ -259,82 +340,41 @@ static const Addr PageOffset = PageBytes - 1;
* @param xc The execution context.
*/
template <class XC>
static void zeroRegisters(XC *xc);
};
typedef AlphaISA TheISA;
typedef TheISA::MachInst MachInst;
typedef TheISA::Addr Addr;
typedef TheISA::RegIndex RegIndex;
typedef TheISA::IntReg IntReg;
typedef TheISA::IntRegFile IntRegFile;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegFile FloatRegFile;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::AnyReg AnyReg;
typedef TheISA::RegFile RegFile;
const int NumIntRegs = TheISA::NumIntRegs;
const int NumFloatRegs = TheISA::NumFloatRegs;
const int NumMiscRegs = TheISA::NumMiscRegs;
const int TotalNumRegs = TheISA::TotalNumRegs;
const int VMPageSize = TheISA::VMPageSize;
const int LogVMPageSize = TheISA::LogVMPageSize;
const int ZeroReg = TheISA::ZeroReg;
const int StackPointerReg = TheISA::StackPointerReg;
const int GlobalPointerReg = TheISA::GlobalPointerReg;
const int ReturnAddressReg = TheISA::ReturnAddressReg;
const int ReturnValueReg = TheISA::ReturnValueReg;
const int ArgumentReg0 = TheISA::ArgumentReg0;
const int ArgumentReg1 = TheISA::ArgumentReg1;
const int ArgumentReg2 = TheISA::ArgumentReg2;
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
const int MaxAddr = (Addr)-1;
#if !FULL_SYSTEM
class SyscallReturn {
public:
template <class T>
SyscallReturn(T v, bool s)
{
retval = (uint64_t)v;
success = s;
}
template <class T>
SyscallReturn(T v)
{
success = (v >= 0);
retval = (uint64_t)v;
}
~SyscallReturn() {}
SyscallReturn& operator=(const SyscallReturn& s) {
retval = s.retval;
success = s.success;
return *this;
}
bool successful() { return success; }
uint64_t value() { return retval; }
private:
uint64_t retval;
bool success;
void zeroRegisters(XC *xc);
const Addr MaxAddr = (Addr)-1;
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
// check for error condition. Alpha syscall convention is to
// indicate success/failure in reg a3 (r19) and put the
// return value itself in the standard return value reg (v0).
if (return_value.successful()) {
// no error
regs->intRegFile[SyscallSuccessReg] = 0;
regs->intRegFile[ReturnValueReg] = return_value.value();
} else {
// got an error, return details
regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
regs->intRegFile[ReturnValueReg] = -return_value.value();
}
}
};
static inline AlphaISA::ExtMachInst
AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
#if FULL_SYSTEM
AlphaISA::ExtMachInst ext_inst = inst;
if (pc && 0x1)
return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
else
return ext_inst;
#else
return AlphaISA::ExtMachInst(inst);
#endif
}
#if FULL_SYSTEM
typedef TheISA::InternalProcReg InternalProcReg;
const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
const int NumInterruptLevels = TheISA::NumInterruptLevels;
#include "arch/alpha/ev5.hh"
#endif

8
kern/linux/aligned.hh → arch/alpha/linux/aligned.hh
View file

@ -26,15 +26,15 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __KERN_LINUX_ALIGNED_HH__
#define __KERN_LINUX_ALIGNED_HH__
#ifndef __ARCH_ALPHA_LINUX_ALIGNED_HH__
#define __ARCH_ALPHA_LINUX_ALIGNED_HH__
/* GCC 3.3.X has a bug in which attributes+typedefs don't work. 3.2.X is fine
* as in 3.4.X, but the bug is marked will not fix in 3.3.X so here is
* the work around.
*/
#if __GNUC__ == 3 && __GNUC_MINOR__ != 3
#if (__GNUC__ == 3 && __GNUC_MINOR__ != 3) || __GNUC__ > 3
typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
typedef Addr Addr_a __attribute__ ((aligned (8))) ;
@ -44,4 +44,4 @@ typedef Addr Addr_a __attribute__ ((aligned (8))) ;
#define Addr_a Addr __attribute__ ((aligned (8)))
#endif /* __GNUC__ __GNUC_MINOR__ */
#endif /* __KERN_LINUX_ALIGNED_HH__ */
#endif /* __ARCH_ALPHA_LINUX_ALIGNED_HH__ */

8
kern/linux/hwrpb.hh → arch/alpha/linux/hwrpb.hh
View file

@ -22,10 +22,10 @@
* SOFTWARE.
*/
#ifndef __KERN_LINUX_HWRPB_HH__
#define __KERN_LINUX_HWRPB_HH__
#ifndef __ARCH_ALPHA_LINUX_HWRPB_HH__
#define __ARCH_ALPHA_LINUX_HWRPB_HH__
#include "kern/linux/aligned.hh"
#include "arch/alpha/linux/aligned.hh"
namespace Linux {
struct pcb_struct {
@ -39,4 +39,4 @@ namespace Linux {
uint64_ta res1, res2;
};
}
#endif // __KERN_LINUX_HWRPB_HH__
#endif // __ARCH_ALPHA_LINUX_HWRPB_HH__

589
arch/alpha/linux/process.cc Normal file
View file

@ -0,0 +1,589 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/alpha/linux/process.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "kern/linux/linux.hh"
#include "mem/functional/functional.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
using namespace std;
using namespace AlphaISA;
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->release, "2.4.20");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
name.copyOut(xc->getMemPtr());
return 0;
}
/// Target osf_getsysyinfo() handler. Even though this call is
/// borrowed from Tru64, the subcases that get used appear to be
/// different in practice from those used by Tru64 processes.
static SyscallReturn
osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
// unsigned nbytes = xc->getSyscallArg(2);
switch (op) {
case 45: { // GSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
fpcr.copyOut(xc->getMemPtr());
return 0;
}
default:
cerr << "osf_getsysinfo: unknown op " << op << endl;
abort();
break;
}
return 1;
}
/// Target osf_setsysinfo() handler.
static SyscallReturn
osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
// unsigned nbytes = xc->getSyscallArg(2);
switch (op) {
case 14: { // SSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
fpcr.copyIn(xc->getMemPtr());
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
}
default:
cerr << "osf_setsysinfo: unknown op " << op << endl;
abort();
break;
}
return 1;
}
SyscallDesc AlphaLinuxProcess::syscallDescs[] = {
/* 0 */ SyscallDesc("osf_syscall", unimplementedFunc),
/* 1 */ SyscallDesc("exit", exitFunc),
/* 2 */ SyscallDesc("fork", unimplementedFunc),
/* 3 */ SyscallDesc("read", readFunc),
/* 4 */ SyscallDesc("write", writeFunc),
/* 5 */ SyscallDesc("osf_old_open", unimplementedFunc),
/* 6 */ SyscallDesc("close", closeFunc),
/* 7 */ SyscallDesc("osf_wait4", unimplementedFunc),
/* 8 */ SyscallDesc("osf_old_creat", unimplementedFunc),
/* 9 */ SyscallDesc("link", unimplementedFunc),
/* 10 */ SyscallDesc("unlink", unlinkFunc),
/* 11 */ SyscallDesc("osf_execve", unimplementedFunc),
/* 12 */ SyscallDesc("chdir", unimplementedFunc),
/* 13 */ SyscallDesc("fchdir", unimplementedFunc),
/* 14 */ SyscallDesc("mknod", unimplementedFunc),
/* 15 */ SyscallDesc("chmod", chmodFunc<Linux>),
/* 16 */ SyscallDesc("chown", chownFunc),
/* 17 */ SyscallDesc("brk", obreakFunc),
/* 18 */ SyscallDesc("osf_getfsstat", unimplementedFunc),
/* 19 */ SyscallDesc("lseek", lseekFunc),
/* 20 */ SyscallDesc("getxpid", getpidPseudoFunc),
/* 21 */ SyscallDesc("osf_mount", unimplementedFunc),
/* 22 */ SyscallDesc("umount", unimplementedFunc),
/* 23 */ SyscallDesc("setuid", setuidFunc),
/* 24 */ SyscallDesc("getxuid", getuidPseudoFunc),
/* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc),
/* 26 */ SyscallDesc("osf_ptrace", unimplementedFunc),
/* 27 */ SyscallDesc("osf_nrecvmsg", unimplementedFunc),
/* 28 */ SyscallDesc("osf_nsendmsg", unimplementedFunc),
/* 29 */ SyscallDesc("osf_nrecvfrom", unimplementedFunc),
/* 30 */ SyscallDesc("osf_naccept", unimplementedFunc),
/* 31 */ SyscallDesc("osf_ngetpeername", unimplementedFunc),
/* 32 */ SyscallDesc("osf_ngetsockname", unimplementedFunc),
/* 33 */ SyscallDesc("access", unimplementedFunc),
/* 34 */ SyscallDesc("osf_chflags", unimplementedFunc),
/* 35 */ SyscallDesc("osf_fchflags", unimplementedFunc),
/* 36 */ SyscallDesc("sync", unimplementedFunc),
/* 37 */ SyscallDesc("kill", unimplementedFunc),
/* 38 */ SyscallDesc("osf_old_stat", unimplementedFunc),
/* 39 */ SyscallDesc("setpgid", unimplementedFunc),
/* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc),
/* 41 */ SyscallDesc("dup", unimplementedFunc),
/* 42 */ SyscallDesc("pipe", pipePseudoFunc),
/* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc),
/* 44 */ SyscallDesc("osf_profil", unimplementedFunc),
/* 45 */ SyscallDesc("open", openFunc<Linux>),
/* 46 */ SyscallDesc("osf_old_sigaction", unimplementedFunc),
/* 47 */ SyscallDesc("getxgid", getgidPseudoFunc),
/* 48 */ SyscallDesc("osf_sigprocmask", ignoreFunc),
/* 49 */ SyscallDesc("osf_getlogin", unimplementedFunc),
/* 50 */ SyscallDesc("osf_setlogin", unimplementedFunc),
/* 51 */ SyscallDesc("acct", unimplementedFunc),
/* 52 */ SyscallDesc("sigpending", unimplementedFunc),
/* 53 */ SyscallDesc("osf_classcntl", unimplementedFunc),
/* 54 */ SyscallDesc("ioctl", ioctlFunc<Linux>),
/* 55 */ SyscallDesc("osf_reboot", unimplementedFunc),
/* 56 */ SyscallDesc("osf_revoke", unimplementedFunc),
/* 57 */ SyscallDesc("symlink", unimplementedFunc),
/* 58 */ SyscallDesc("readlink", unimplementedFunc),
/* 59 */ SyscallDesc("execve", unimplementedFunc),
/* 60 */ SyscallDesc("umask", unimplementedFunc),
/* 61 */ SyscallDesc("chroot", unimplementedFunc),
/* 62 */ SyscallDesc("osf_old_fstat", unimplementedFunc),
/* 63 */ SyscallDesc("getpgrp", unimplementedFunc),
/* 64 */ SyscallDesc("getpagesize", getpagesizeFunc),
/* 65 */ SyscallDesc("osf_mremap", unimplementedFunc),
/* 66 */ SyscallDesc("vfork", unimplementedFunc),
/* 67 */ SyscallDesc("stat", statFunc<Linux>),
/* 68 */ SyscallDesc("lstat", lstatFunc<Linux>),
/* 69 */ SyscallDesc("osf_sbrk", unimplementedFunc),
/* 70 */ SyscallDesc("osf_sstk", unimplementedFunc),
/* 71 */ SyscallDesc("mmap", mmapFunc<Linux>),
/* 72 */ SyscallDesc("osf_old_vadvise", unimplementedFunc),
/* 73 */ SyscallDesc("munmap", munmapFunc),
/* 74 */ SyscallDesc("mprotect", ignoreFunc),
/* 75 */ SyscallDesc("madvise", unimplementedFunc),
/* 76 */ SyscallDesc("vhangup", unimplementedFunc),
/* 77 */ SyscallDesc("osf_kmodcall", unimplementedFunc),
/* 78 */ SyscallDesc("osf_mincore", unimplementedFunc),
/* 79 */ SyscallDesc("getgroups", unimplementedFunc),
/* 80 */ SyscallDesc("setgroups", unimplementedFunc),
/* 81 */ SyscallDesc("osf_old_getpgrp", unimplementedFunc),
/* 82 */ SyscallDesc("setpgrp", unimplementedFunc),
/* 83 */ SyscallDesc("osf_setitimer", unimplementedFunc),
/* 84 */ SyscallDesc("osf_old_wait", unimplementedFunc),
/* 85 */ SyscallDesc("osf_table", unimplementedFunc),
/* 86 */ SyscallDesc("osf_getitimer", unimplementedFunc),
/* 87 */ SyscallDesc("gethostname", gethostnameFunc),
/* 88 */ SyscallDesc("sethostname", unimplementedFunc),
/* 89 */ SyscallDesc("getdtablesize", unimplementedFunc),
/* 90 */ SyscallDesc("dup2", unimplementedFunc),
/* 91 */ SyscallDesc("fstat", fstatFunc<Linux>),
/* 92 */ SyscallDesc("fcntl", fcntlFunc),
/* 93 */ SyscallDesc("osf_select", unimplementedFunc),
/* 94 */ SyscallDesc("poll", unimplementedFunc),
/* 95 */ SyscallDesc("fsync", unimplementedFunc),
/* 96 */ SyscallDesc("setpriority", unimplementedFunc),
/* 97 */ SyscallDesc("socket", unimplementedFunc),
/* 98 */ SyscallDesc("connect", unimplementedFunc),
/* 99 */ SyscallDesc("accept", unimplementedFunc),
/* 100 */ SyscallDesc("getpriority", unimplementedFunc),
/* 101 */ SyscallDesc("send", unimplementedFunc),
/* 102 */ SyscallDesc("recv", unimplementedFunc),
/* 103 */ SyscallDesc("sigreturn", unimplementedFunc),
/* 104 */ SyscallDesc("bind", unimplementedFunc),
/* 105 */ SyscallDesc("setsockopt", unimplementedFunc),
/* 106 */ SyscallDesc("listen", unimplementedFunc),
/* 107 */ SyscallDesc("osf_plock", unimplementedFunc),
/* 108 */ SyscallDesc("osf_old_sigvec", unimplementedFunc),
/* 109 */ SyscallDesc("osf_old_sigblock", unimplementedFunc),
/* 110 */ SyscallDesc("osf_old_sigsetmask", unimplementedFunc),
/* 111 */ SyscallDesc("sigsuspend", unimplementedFunc),
/* 112 */ SyscallDesc("osf_sigstack", ignoreFunc),
/* 113 */ SyscallDesc("recvmsg", unimplementedFunc),
/* 114 */ SyscallDesc("sendmsg", unimplementedFunc),
/* 115 */ SyscallDesc("osf_old_vtrace", unimplementedFunc),
/* 116 */ SyscallDesc("osf_gettimeofday", unimplementedFunc),
/* 117 */ SyscallDesc("osf_getrusage", unimplementedFunc),
/* 118 */ SyscallDesc("getsockopt", unimplementedFunc),
/* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc),
/* 120 */ SyscallDesc("readv", unimplementedFunc),
/* 121 */ SyscallDesc("writev", writevFunc<Linux>),
/* 122 */ SyscallDesc("osf_settimeofday", unimplementedFunc),
/* 123 */ SyscallDesc("fchown", fchownFunc),
/* 124 */ SyscallDesc("fchmod", fchmodFunc<Linux>),
/* 125 */ SyscallDesc("recvfrom", unimplementedFunc),
/* 126 */ SyscallDesc("setreuid", unimplementedFunc),
/* 127 */ SyscallDesc("setregid", unimplementedFunc),
/* 128 */ SyscallDesc("rename", renameFunc),
/* 129 */ SyscallDesc("truncate", unimplementedFunc),
/* 130 */ SyscallDesc("ftruncate", unimplementedFunc),
/* 131 */ SyscallDesc("flock", unimplementedFunc),
/* 132 */ SyscallDesc("setgid", unimplementedFunc),
/* 133 */ SyscallDesc("sendto", unimplementedFunc),
/* 134 */ SyscallDesc("shutdown", unimplementedFunc),
/* 135 */ SyscallDesc("socketpair", unimplementedFunc),
/* 136 */ SyscallDesc("mkdir", unimplementedFunc),
/* 137 */ SyscallDesc("rmdir", unimplementedFunc),
/* 138 */ SyscallDesc("osf_utimes", unimplementedFunc),
/* 139 */ SyscallDesc("osf_old_sigreturn", unimplementedFunc),
/* 140 */ SyscallDesc("osf_adjtime", unimplementedFunc),
/* 141 */ SyscallDesc("getpeername", unimplementedFunc),
/* 142 */ SyscallDesc("osf_gethostid", unimplementedFunc),
/* 143 */ SyscallDesc("osf_sethostid", unimplementedFunc),
/* 144 */ SyscallDesc("getrlimit", getrlimitFunc<Linux>),
/* 145 */ SyscallDesc("setrlimit", ignoreFunc),
/* 146 */ SyscallDesc("osf_old_killpg", unimplementedFunc),
/* 147 */ SyscallDesc("setsid", unimplementedFunc),
/* 148 */ SyscallDesc("quotactl", unimplementedFunc),
/* 149 */ SyscallDesc("osf_oldquota", unimplementedFunc),
/* 150 */ SyscallDesc("getsockname", unimplementedFunc),
/* 151 */ SyscallDesc("osf_pread", unimplementedFunc),
/* 152 */ SyscallDesc("osf_pwrite", unimplementedFunc),
/* 153 */ SyscallDesc("osf_pid_block", unimplementedFunc),
/* 154 */ SyscallDesc("osf_pid_unblock", unimplementedFunc),
/* 155 */ SyscallDesc("osf_signal_urti", unimplementedFunc),
/* 156 */ SyscallDesc("sigaction", ignoreFunc),
/* 157 */ SyscallDesc("osf_sigwaitprim", unimplementedFunc),
/* 158 */ SyscallDesc("osf_nfssvc", unimplementedFunc),
/* 159 */ SyscallDesc("osf_getdirentries", unimplementedFunc),
/* 160 */ SyscallDesc("osf_statfs", unimplementedFunc),
/* 161 */ SyscallDesc("osf_fstatfs", unimplementedFunc),
/* 162 */ SyscallDesc("unknown #162", unimplementedFunc),
/* 163 */ SyscallDesc("osf_async_daemon", unimplementedFunc),
/* 164 */ SyscallDesc("osf_getfh", unimplementedFunc),
/* 165 */ SyscallDesc("osf_getdomainname", unimplementedFunc),
/* 166 */ SyscallDesc("setdomainname", unimplementedFunc),
/* 167 */ SyscallDesc("unknown #167", unimplementedFunc),
/* 168 */ SyscallDesc("unknown #168", unimplementedFunc),
/* 169 */ SyscallDesc("osf_exportfs", unimplementedFunc),
/* 170 */ SyscallDesc("unknown #170", unimplementedFunc),
/* 171 */ SyscallDesc("unknown #171", unimplementedFunc),
/* 172 */ SyscallDesc("unknown #172", unimplementedFunc),
/* 173 */ SyscallDesc("unknown #173", unimplementedFunc),
/* 174 */ SyscallDesc("unknown #174", unimplementedFunc),
/* 175 */ SyscallDesc("unknown #175", unimplementedFunc),
/* 176 */ SyscallDesc("unknown #176", unimplementedFunc),
/* 177 */ SyscallDesc("unknown #177", unimplementedFunc),
/* 178 */ SyscallDesc("unknown #178", unimplementedFunc),
/* 179 */ SyscallDesc("unknown #179", unimplementedFunc),
/* 180 */ SyscallDesc("unknown #180", unimplementedFunc),
/* 181 */ SyscallDesc("osf_alt_plock", unimplementedFunc),
/* 182 */ SyscallDesc("unknown #182", unimplementedFunc),
/* 183 */ SyscallDesc("unknown #183", unimplementedFunc),
/* 184 */ SyscallDesc("osf_getmnt", unimplementedFunc),
/* 185 */ SyscallDesc("unknown #185", unimplementedFunc),
/* 186 */ SyscallDesc("unknown #186", unimplementedFunc),
/* 187 */ SyscallDesc("osf_alt_sigpending", unimplementedFunc),
/* 188 */ SyscallDesc("osf_alt_setsid", unimplementedFunc),
/* 189 */ SyscallDesc("unknown #189", unimplementedFunc),
/* 190 */ SyscallDesc("unknown #190", unimplementedFunc),
/* 191 */ SyscallDesc("unknown #191", unimplementedFunc),
/* 192 */ SyscallDesc("unknown #192", unimplementedFunc),
/* 193 */ SyscallDesc("unknown #193", unimplementedFunc),
/* 194 */ SyscallDesc("unknown #194", unimplementedFunc),
/* 195 */ SyscallDesc("unknown #195", unimplementedFunc),
/* 196 */ SyscallDesc("unknown #196", unimplementedFunc),
/* 197 */ SyscallDesc("unknown #197", unimplementedFunc),
/* 198 */ SyscallDesc("unknown #198", unimplementedFunc),
/* 199 */ SyscallDesc("osf_swapon", unimplementedFunc),
/* 200 */ SyscallDesc("msgctl", unimplementedFunc),
/* 201 */ SyscallDesc("msgget", unimplementedFunc),
/* 202 */ SyscallDesc("msgrcv", unimplementedFunc),
/* 203 */ SyscallDesc("msgsnd", unimplementedFunc),
/* 204 */ SyscallDesc("semctl", unimplementedFunc),
/* 205 */ SyscallDesc("semget", unimplementedFunc),
/* 206 */ SyscallDesc("semop", unimplementedFunc),
/* 207 */ SyscallDesc("osf_utsname", unimplementedFunc),
/* 208 */ SyscallDesc("lchown", unimplementedFunc),
/* 209 */ SyscallDesc("osf_shmat", unimplementedFunc),
/* 210 */ SyscallDesc("shmctl", unimplementedFunc),
/* 211 */ SyscallDesc("shmdt", unimplementedFunc),
/* 212 */ SyscallDesc("shmget", unimplementedFunc),
/* 213 */ SyscallDesc("osf_mvalid", unimplementedFunc),
/* 214 */ SyscallDesc("osf_getaddressconf", unimplementedFunc),
/* 215 */ SyscallDesc("osf_msleep", unimplementedFunc),
/* 216 */ SyscallDesc("osf_mwakeup", unimplementedFunc),
/* 217 */ SyscallDesc("msync", unimplementedFunc),
/* 218 */ SyscallDesc("osf_signal", unimplementedFunc),
/* 219 */ SyscallDesc("osf_utc_gettime", unimplementedFunc),
/* 220 */ SyscallDesc("osf_utc_adjtime", unimplementedFunc),
/* 221 */ SyscallDesc("unknown #221", unimplementedFunc),
/* 222 */ SyscallDesc("osf_security", unimplementedFunc),
/* 223 */ SyscallDesc("osf_kloadcall", unimplementedFunc),
/* 224 */ SyscallDesc("unknown #224", unimplementedFunc),
/* 225 */ SyscallDesc("unknown #225", unimplementedFunc),
/* 226 */ SyscallDesc("unknown #226", unimplementedFunc),
/* 227 */ SyscallDesc("unknown #227", unimplementedFunc),
/* 228 */ SyscallDesc("unknown #228", unimplementedFunc),
/* 229 */ SyscallDesc("unknown #229", unimplementedFunc),
/* 230 */ SyscallDesc("unknown #230", unimplementedFunc),
/* 231 */ SyscallDesc("unknown #231", unimplementedFunc),
/* 232 */ SyscallDesc("unknown #232", unimplementedFunc),
/* 233 */ SyscallDesc("getpgid", unimplementedFunc),
/* 234 */ SyscallDesc("getsid", unimplementedFunc),
/* 235 */ SyscallDesc("sigaltstack", ignoreFunc),
/* 236 */ SyscallDesc("osf_waitid", unimplementedFunc),
/* 237 */ SyscallDesc("osf_priocntlset", unimplementedFunc),
/* 238 */ SyscallDesc("osf_sigsendset", unimplementedFunc),
/* 239 */ SyscallDesc("osf_set_speculative", unimplementedFunc),
/* 240 */ SyscallDesc("osf_msfs_syscall", unimplementedFunc),
/* 241 */ SyscallDesc("osf_sysinfo", unimplementedFunc),
/* 242 */ SyscallDesc("osf_uadmin", unimplementedFunc),
/* 243 */ SyscallDesc("osf_fuser", unimplementedFunc),
/* 244 */ SyscallDesc("osf_proplist_syscall", unimplementedFunc),
/* 245 */ SyscallDesc("osf_ntp_adjtime", unimplementedFunc),
/* 246 */ SyscallDesc("osf_ntp_gettime", unimplementedFunc),
/* 247 */ SyscallDesc("osf_pathconf", unimplementedFunc),
/* 248 */ SyscallDesc("osf_fpathconf", unimplementedFunc),
/* 249 */ SyscallDesc("unknown #249", unimplementedFunc),
/* 250 */ SyscallDesc("osf_uswitch", unimplementedFunc),
/* 251 */ SyscallDesc("osf_usleep_thread", unimplementedFunc),
/* 252 */ SyscallDesc("osf_audcntl", unimplementedFunc),
/* 253 */ SyscallDesc("osf_audgen", unimplementedFunc),
/* 254 */ SyscallDesc("sysfs", unimplementedFunc),
/* 255 */ SyscallDesc("osf_subsys_info", unimplementedFunc),
/* 256 */ SyscallDesc("osf_getsysinfo", osf_getsysinfoFunc),
/* 257 */ SyscallDesc("osf_setsysinfo", osf_setsysinfoFunc),
/* 258 */ SyscallDesc("osf_afs_syscall", unimplementedFunc),
/* 259 */ SyscallDesc("osf_swapctl", unimplementedFunc),
/* 260 */ SyscallDesc("osf_memcntl", unimplementedFunc),
/* 261 */ SyscallDesc("osf_fdatasync", unimplementedFunc),
/* 262 */ SyscallDesc("unknown #262", unimplementedFunc),
/* 263 */ SyscallDesc("unknown #263", unimplementedFunc),
/* 264 */ SyscallDesc("unknown #264", unimplementedFunc),
/* 265 */ SyscallDesc("unknown #265", unimplementedFunc),
/* 266 */ SyscallDesc("unknown #266", unimplementedFunc),
/* 267 */ SyscallDesc("unknown #267", unimplementedFunc),
/* 268 */ SyscallDesc("unknown #268", unimplementedFunc),
/* 269 */ SyscallDesc("unknown #269", unimplementedFunc),
/* 270 */ SyscallDesc("unknown #270", unimplementedFunc),
/* 271 */ SyscallDesc("unknown #271", unimplementedFunc),
/* 272 */ SyscallDesc("unknown #272", unimplementedFunc),
/* 273 */ SyscallDesc("unknown #273", unimplementedFunc),
/* 274 */ SyscallDesc("unknown #274", unimplementedFunc),
/* 275 */ SyscallDesc("unknown #275", unimplementedFunc),
/* 276 */ SyscallDesc("unknown #276", unimplementedFunc),
/* 277 */ SyscallDesc("unknown #277", unimplementedFunc),
/* 278 */ SyscallDesc("unknown #278", unimplementedFunc),
/* 279 */ SyscallDesc("unknown #279", unimplementedFunc),
/* 280 */ SyscallDesc("unknown #280", unimplementedFunc),
/* 281 */ SyscallDesc("unknown #281", unimplementedFunc),
/* 282 */ SyscallDesc("unknown #282", unimplementedFunc),
/* 283 */ SyscallDesc("unknown #283", unimplementedFunc),
/* 284 */ SyscallDesc("unknown #284", unimplementedFunc),
/* 285 */ SyscallDesc("unknown #285", unimplementedFunc),
/* 286 */ SyscallDesc("unknown #286", unimplementedFunc),
/* 287 */ SyscallDesc("unknown #287", unimplementedFunc),
/* 288 */ SyscallDesc("unknown #288", unimplementedFunc),
/* 289 */ SyscallDesc("unknown #289", unimplementedFunc),
/* 290 */ SyscallDesc("unknown #290", unimplementedFunc),
/* 291 */ SyscallDesc("unknown #291", unimplementedFunc),
/* 292 */ SyscallDesc("unknown #292", unimplementedFunc),
/* 293 */ SyscallDesc("unknown #293", unimplementedFunc),
/* 294 */ SyscallDesc("unknown #294", unimplementedFunc),
/* 295 */ SyscallDesc("unknown #295", unimplementedFunc),
/* 296 */ SyscallDesc("unknown #296", unimplementedFunc),
/* 297 */ SyscallDesc("unknown #297", unimplementedFunc),
/* 298 */ SyscallDesc("unknown #298", unimplementedFunc),
/* 299 */ SyscallDesc("unknown #299", unimplementedFunc),
/*
* Linux-specific system calls begin at 300
*/
/* 300 */ SyscallDesc("bdflush", unimplementedFunc),
/* 301 */ SyscallDesc("sethae", unimplementedFunc),
/* 302 */ SyscallDesc("mount", unimplementedFunc),
/* 303 */ SyscallDesc("old_adjtimex", unimplementedFunc),
/* 304 */ SyscallDesc("swapoff", unimplementedFunc),
/* 305 */ SyscallDesc("getdents", unimplementedFunc),
/* 306 */ SyscallDesc("create_module", unimplementedFunc),
/* 307 */ SyscallDesc("init_module", unimplementedFunc),
/* 308 */ SyscallDesc("delete_module", unimplementedFunc),
/* 309 */ SyscallDesc("get_kernel_syms", unimplementedFunc),
/* 310 */ SyscallDesc("syslog", unimplementedFunc),
/* 311 */ SyscallDesc("reboot", unimplementedFunc),
/* 312 */ SyscallDesc("clone", unimplementedFunc),
/* 313 */ SyscallDesc("uselib", unimplementedFunc),
/* 314 */ SyscallDesc("mlock", unimplementedFunc),
/* 315 */ SyscallDesc("munlock", unimplementedFunc),
/* 316 */ SyscallDesc("mlockall", unimplementedFunc),
/* 317 */ SyscallDesc("munlockall", unimplementedFunc),
/* 318 */ SyscallDesc("sysinfo", unimplementedFunc),
/* 319 */ SyscallDesc("_sysctl", unimplementedFunc),
/* 320 */ SyscallDesc("was sys_idle", unimplementedFunc),
/* 321 */ SyscallDesc("oldumount", unimplementedFunc),
/* 322 */ SyscallDesc("swapon", unimplementedFunc),
/* 323 */ SyscallDesc("times", ignoreFunc),
/* 324 */ SyscallDesc("personality", unimplementedFunc),
/* 325 */ SyscallDesc("setfsuid", unimplementedFunc),
/* 326 */ SyscallDesc("setfsgid", unimplementedFunc),
/* 327 */ SyscallDesc("ustat", unimplementedFunc),
/* 328 */ SyscallDesc("statfs", unimplementedFunc),
/* 329 */ SyscallDesc("fstatfs", unimplementedFunc),
/* 330 */ SyscallDesc("sched_setparam", unimplementedFunc),
/* 331 */ SyscallDesc("sched_getparam", unimplementedFunc),
/* 332 */ SyscallDesc("sched_setscheduler", unimplementedFunc),
/* 333 */ SyscallDesc("sched_getscheduler", unimplementedFunc),
/* 334 */ SyscallDesc("sched_yield", unimplementedFunc),
/* 335 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
/* 336 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
/* 337 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
/* 338 */ SyscallDesc("afs_syscall", unimplementedFunc),
/* 339 */ SyscallDesc("uname", unameFunc),
/* 340 */ SyscallDesc("nanosleep", unimplementedFunc),
/* 341 */ SyscallDesc("mremap", unimplementedFunc),
/* 342 */ SyscallDesc("nfsservctl", unimplementedFunc),
/* 343 */ SyscallDesc("setresuid", unimplementedFunc),
/* 344 */ SyscallDesc("getresuid", unimplementedFunc),
/* 345 */ SyscallDesc("pciconfig_read", unimplementedFunc),
/* 346 */ SyscallDesc("pciconfig_write", unimplementedFunc),
/* 347 */ SyscallDesc("query_module", unimplementedFunc),
/* 348 */ SyscallDesc("prctl", unimplementedFunc),
/* 349 */ SyscallDesc("pread", unimplementedFunc),
/* 350 */ SyscallDesc("pwrite", unimplementedFunc),
/* 351 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
/* 352 */ SyscallDesc("rt_sigaction", ignoreFunc),
/* 353 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
/* 354 */ SyscallDesc("rt_sigpending", unimplementedFunc),
/* 355 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
/* 356 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc),
/* 357 */ SyscallDesc("rt_sigsuspend", unimplementedFunc),
/* 358 */ SyscallDesc("select", unimplementedFunc),
/* 359 */ SyscallDesc("gettimeofday", gettimeofdayFunc<Linux>),
/* 360 */ SyscallDesc("settimeofday", unimplementedFunc),
/* 361 */ SyscallDesc("getitimer", unimplementedFunc),
/* 362 */ SyscallDesc("setitimer", unimplementedFunc),
/* 363 */ SyscallDesc("utimes", utimesFunc<Linux>),
/* 364 */ SyscallDesc("getrusage", getrusageFunc<Linux>),
/* 365 */ SyscallDesc("wait4", unimplementedFunc),
/* 366 */ SyscallDesc("adjtimex", unimplementedFunc),
/* 367 */ SyscallDesc("getcwd", unimplementedFunc),
/* 368 */ SyscallDesc("capget", unimplementedFunc),
/* 369 */ SyscallDesc("capset", unimplementedFunc),
/* 370 */ SyscallDesc("sendfile", unimplementedFunc),
/* 371 */ SyscallDesc("setresgid", unimplementedFunc),
/* 372 */ SyscallDesc("getresgid", unimplementedFunc),
/* 373 */ SyscallDesc("dipc", unimplementedFunc),
/* 374 */ SyscallDesc("pivot_root", unimplementedFunc),
/* 375 */ SyscallDesc("mincore", unimplementedFunc),
/* 376 */ SyscallDesc("pciconfig_iobase", unimplementedFunc),
/* 377 */ SyscallDesc("getdents64", unimplementedFunc),
/* 378 */ SyscallDesc("gettid", unimplementedFunc),
/* 379 */ SyscallDesc("readahead", unimplementedFunc),
/* 380 */ SyscallDesc("security", unimplementedFunc),
/* 381 */ SyscallDesc("tkill", unimplementedFunc),
/* 382 */ SyscallDesc("setxattr", unimplementedFunc),
/* 383 */ SyscallDesc("lsetxattr", unimplementedFunc),
/* 384 */ SyscallDesc("fsetxattr", unimplementedFunc),
/* 385 */ SyscallDesc("getxattr", unimplementedFunc),
/* 386 */ SyscallDesc("lgetxattr", unimplementedFunc),
/* 387 */ SyscallDesc("fgetxattr", unimplementedFunc),
/* 388 */ SyscallDesc("listxattr", unimplementedFunc),
/* 389 */ SyscallDesc("llistxattr", unimplementedFunc),
/* 390 */ SyscallDesc("flistxattr", unimplementedFunc),
/* 391 */ SyscallDesc("removexattr", unimplementedFunc),
/* 392 */ SyscallDesc("lremovexattr", unimplementedFunc),
/* 393 */ SyscallDesc("fremovexattr", unimplementedFunc),
/* 394 */ SyscallDesc("futex", unimplementedFunc),
/* 395 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
/* 396 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
/* 397 */ SyscallDesc("tuxcall", unimplementedFunc),
/* 398 */ SyscallDesc("io_setup", unimplementedFunc),
/* 399 */ SyscallDesc("io_destroy", unimplementedFunc),
/* 400 */ SyscallDesc("io_getevents", unimplementedFunc),
/* 401 */ SyscallDesc("io_submit", unimplementedFunc),
/* 402 */ SyscallDesc("io_cancel", unimplementedFunc),
/* 403 */ SyscallDesc("unknown #403", unimplementedFunc),
/* 404 */ SyscallDesc("unknown #404", unimplementedFunc),
/* 405 */ SyscallDesc("exit_group", exitFunc), // exit all threads...
/* 406 */ SyscallDesc("lookup_dcookie", unimplementedFunc),
/* 407 */ SyscallDesc("sys_epoll_create", unimplementedFunc),
/* 408 */ SyscallDesc("sys_epoll_ctl", unimplementedFunc),
/* 409 */ SyscallDesc("sys_epoll_wait", unimplementedFunc),
/* 410 */ SyscallDesc("remap_file_pages", unimplementedFunc),
/* 411 */ SyscallDesc("set_tid_address", unimplementedFunc),
/* 412 */ SyscallDesc("restart_syscall", unimplementedFunc),
/* 413 */ SyscallDesc("fadvise64", unimplementedFunc),
/* 414 */ SyscallDesc("timer_create", unimplementedFunc),
/* 415 */ SyscallDesc("timer_settime", unimplementedFunc),
/* 416 */ SyscallDesc("timer_gettime", unimplementedFunc),
/* 417 */ SyscallDesc("timer_getoverrun", unimplementedFunc),
/* 418 */ SyscallDesc("timer_delete", unimplementedFunc),
/* 419 */ SyscallDesc("clock_settime", unimplementedFunc),
/* 420 */ SyscallDesc("clock_gettime", unimplementedFunc),
/* 421 */ SyscallDesc("clock_getres", unimplementedFunc),
/* 422 */ SyscallDesc("clock_nanosleep", unimplementedFunc),
/* 423 */ SyscallDesc("semtimedop", unimplementedFunc),
/* 424 */ SyscallDesc("tgkill", unimplementedFunc),
/* 425 */ SyscallDesc("stat64", unimplementedFunc),
/* 426 */ SyscallDesc("lstat64", lstat64Func<Linux>),
/* 427 */ SyscallDesc("fstat64", fstat64Func<Linux>),
/* 428 */ SyscallDesc("vserver", unimplementedFunc),
/* 429 */ SyscallDesc("mbind", unimplementedFunc),
/* 430 */ SyscallDesc("get_mempolicy", unimplementedFunc),
/* 431 */ SyscallDesc("set_mempolicy", unimplementedFunc),
/* 432 */ SyscallDesc("mq_open", unimplementedFunc),
/* 433 */ SyscallDesc("mq_unlink", unimplementedFunc),
/* 434 */ SyscallDesc("mq_timedsend", unimplementedFunc),
/* 435 */ SyscallDesc("mq_timedreceive", unimplementedFunc),
/* 436 */ SyscallDesc("mq_notify", unimplementedFunc),
/* 437 */ SyscallDesc("mq_getsetattr", unimplementedFunc),
/* 438 */ SyscallDesc("waitid", unimplementedFunc),
/* 439 */ SyscallDesc("add_key", unimplementedFunc),
/* 440 */ SyscallDesc("request_key", unimplementedFunc),
/* 441 */ SyscallDesc("keyctl", unimplementedFunc)
};
AlphaLinuxProcess::AlphaLinuxProcess(const std::string &name,
ObjectFile *objFile,
int stdin_fd,
int stdout_fd,
int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp)
: LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
{
init_regs->intRegFile[0] = 0;
}
SyscallDesc*
AlphaLinuxProcess::getDesc(int callnum)
{
if (callnum < 0 || callnum > Num_Syscall_Descs)
return NULL;
return &syscallDescs[callnum];
}

11
arch/alpha/alpha_linux_process.hh → arch/alpha/linux/process.hh
View file

@ -44,8 +44,15 @@ class AlphaLinuxProcess : public LiveProcess
std::vector<std::string> &argv,
std::vector<std::string> &envp);
/// Syscall emulation function.
virtual void syscall(ExecContext *xc);
virtual SyscallDesc* getDesc(int callnum);
/// The target system's hostname.
static const char *hostname;
/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
const int Num_Syscall_Descs;
};

69
kern/linux/linux_system.cc → arch/alpha/linux/system.cc
View file

@ -35,23 +35,28 @@
* up boot time.
*/
#include "arch/arguments.hh"
#include "arch/vtophys.hh"
#include "arch/alpha/linux/system.hh"
#include "arch/alpha/linux/threadinfo.hh"
#include "arch/alpha/system.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
#include "kern/linux/linux_system.hh"
#include "kern/linux/linux_threadinfo.hh"
#include "dev/platform.hh"
#include "kern/linux/printk.hh"
#include "kern/linux/events.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/builder.hh"
#include "dev/platform.hh"
#include "targetarch/arguments.hh"
#include "targetarch/vtophys.hh"
#include "sim/byteswap.hh"
using namespace std;
using namespace AlphaISA;
using namespace Linux;
LinuxSystem::LinuxSystem(Params *p)
: System(p)
LinuxAlphaSystem::LinuxAlphaSystem(Params *p)
: AlphaSystem(p)
{
Addr addr = 0;
Addr paddr = 0;
@ -71,7 +76,7 @@ LinuxSystem::LinuxSystem(Params *p)
paddr = vtophys(physmem, CommandLine());
char *commandline = (char *)physmem->dma_addr(paddr, sizeof(uint64_t));
if (commandline)
strncpy(commandline, params->boot_osflags.c_str(), CommandLineSize);
strncpy(commandline, params()->boot_osflags.c_str(), CommandLineSize);
/**
* find the address of the est_cycle_freq variable and insert it
@ -100,7 +105,7 @@ LinuxSystem::LinuxSystem(Params *p)
char *dp264_mv = (char *)physmem->dma_addr(paddr, sizeof(uint64_t));
if (dp264_mv) {
*(uint32_t*)(dp264_mv+0x18) = htog((uint32_t)127);
*(uint32_t*)(dp264_mv+0x18) = LittleEndianGuest::htog((uint32_t)127);
} else
panic("could not translate dp264_mv addr\n");
@ -144,7 +149,7 @@ LinuxSystem::LinuxSystem(Params *p)
printThreadEvent = NULL;
}
if (params->bin_int) {
if (params()->bin_int) {
intStartEvent = addPalFuncEvent<InterruptStartEvent>("sys_int_21");
if (!intStartEvent)
panic("could not find symbol: sys_int_21\n");
@ -163,7 +168,7 @@ LinuxSystem::LinuxSystem(Params *p)
}
}
LinuxSystem::~LinuxSystem()
LinuxAlphaSystem::~LinuxAlphaSystem()
{
#ifndef NDEBUG
delete kernelPanicEvent;
@ -181,7 +186,7 @@ LinuxSystem::~LinuxSystem()
void
LinuxSystem::setDelayLoop(ExecContext *xc)
LinuxAlphaSystem::setDelayLoop(ExecContext *xc)
{
Addr addr = 0;
if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
@ -190,38 +195,24 @@ LinuxSystem::setDelayLoop(ExecContext *xc)
uint8_t *loops_per_jiffy =
physmem->dma_addr(paddr, sizeof(uint32_t));
Tick cpuFreq = xc->cpu->frequency();
Tick cpuFreq = xc->getCpuPtr()->frequency();
Tick intrFreq = platform->intrFrequency();
*(uint32_t *)loops_per_jiffy =
(uint32_t)((cpuFreq / intrFreq) * 0.9988);
}
}
void
LinuxSystem::SkipDelayLoopEvent::process(ExecContext *xc)
LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc)
{
SkipFuncEvent::process(xc);
// calculate and set loops_per_jiffy
((LinuxSystem *)xc->system)->setDelayLoop(xc);
((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc);
}
void
LinuxSystem::DebugPrintkEvent::process(ExecContext *xc)
{
if (DTRACE(DebugPrintf)) {
if (!raw) {
StringWrap name(xc->system->name() + ".dprintk");
DPRINTFN("");
}
AlphaArguments args(xc);
Printk(args);
SkipFuncEvent::process(xc);
}
}
void
LinuxSystem::PrintThreadInfo::process(ExecContext *xc)
LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc)
{
Linux::ThreadInfo ti(xc);
@ -230,7 +221,7 @@ LinuxSystem::PrintThreadInfo::process(ExecContext *xc)
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<MemoryController *> memctrl;
@ -251,9 +242,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem)
VectorParam<string> binned_fns;
Param<bool> bin_int;
END_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem)
END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(memctrl, "memory controller"),
@ -271,11 +262,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxSystem)
INIT_PARAM(binned_fns, "functions to be broken down and binned"),
INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
END_INIT_SIM_OBJECT_PARAMS(LinuxSystem)
END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
CREATE_SIM_OBJECT(LinuxSystem)
CREATE_SIM_OBJECT(LinuxAlphaSystem)
{
System::Params *p = new System::Params;
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->memctrl = memctrl;
@ -291,8 +282,8 @@ CREATE_SIM_OBJECT(LinuxSystem)
p->bin = bin;
p->binned_fns = binned_fns;
p->bin_int = bin_int;
return new LinuxSystem(p);
return new LinuxAlphaSystem(p);
}
REGISTER_SIM_OBJECT("LinuxSystem", LinuxSystem)
REGISTER_SIM_OBJECT("LinuxAlphaSystem", LinuxAlphaSystem)

35
kern/linux/linux_system.hh → arch/alpha/linux/system.hh
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -26,21 +26,27 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __KERN_LINUX_LINUX_SYSTEM_HH__
#define __KERN_LINUX_LINUX_SYSTEM_HH__
#ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__
#define __ARCH_ALPHA_LINUX_SYSTEM_HH__
class ExecContext;
class BreakPCEvent;
class IdleStartEvent;
class PrintThreadInfo;
#include "arch/alpha/system.hh"
#include "kern/linux/events.hh"
using namespace AlphaISA;
using namespace Linux;
using namespace std;
/**
* This class contains linux specific system code (Loading, Events, Binning).
* It points to objects that are the system binaries to load and patches them
* appropriately to work in simulator.
*/
class LinuxSystem : public System
class LinuxAlphaSystem : public AlphaSystem
{
private:
class SkipDelayLoopEvent : public SkipFuncEvent
@ -51,18 +57,6 @@ class LinuxSystem : public System
virtual void process(ExecContext *xc);
};
class DebugPrintkEvent : public SkipFuncEvent
{
private:
bool raw;
public:
DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr,
bool r = false)
: SkipFuncEvent(q, desc, addr), raw(r) {}
virtual void process(ExecContext *xc);
};
class PrintThreadInfo : public PCEvent
{
public:
@ -71,6 +65,7 @@ class LinuxSystem : public System
virtual void process(ExecContext *xc);
};
/**
* Addresses defining where the kernel bootloader places various
* elements. Details found in include/asm-alpha/system.h
@ -142,10 +137,10 @@ class LinuxSystem : public System
IdleStartEvent *idleStartEvent;
public:
LinuxSystem(Params *p);
~LinuxSystem();
LinuxAlphaSystem(Params *p);
~LinuxAlphaSystem();
void setDelayLoop(ExecContext *xc);
};
#endif // __KERN_LINUX_LINUX_SYSTEM_HH__
#endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__

8
kern/linux/thread_info.hh → arch/alpha/linux/thread_info.hh
View file

@ -26,10 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __KERN_LINUX_THREAD_INFO_H__
#define __KERN_LINUX_THREAD_INFO_H__
#ifndef __ARCH_ALPHA_LINUX_THREAD_INFO_H__
#define __ARCH_ALPHA_LINUX_THREAD_INFO_H__
#include "kern/linux/hwrpb.hh"
#include "arch/alpha/linux/hwrpb.hh"
namespace Linux {
struct thread_info {
@ -38,4 +38,4 @@ namespace Linux {
};
}
#endif // __KERN_LINUX_THREAD_INFO_H__
#endif // __ARCH_ALPHA_LINUX_THREAD_INFO_H__

13
kern/linux/linux_threadinfo.hh → arch/alpha/linux/threadinfo.hh
View file

@ -26,12 +26,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __KERN_LINUX_LINUX_TREADNIFO_HH__
#define __KERN_LINUX_LINUX_TREADNIFO_HH__
#ifndef __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__
#define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__
#include "kern/linux/thread_info.hh"
#include "arch/alpha/linux/thread_info.hh"
#include "cpu/exec_context.hh"
#include "kern/linux/sched.hh"
#include "targetarch/vptr.hh"
#include "sim/vptr.hh"
namespace Linux {
@ -53,7 +54,7 @@ class ThreadInfo
* thread_info struct. So we can get the address by masking off
* the lower 14 bits.
*/
current = xc->regs.intRegFile[StackPointerReg] & ~0x3fff;
current = xc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
return VPtr<thread_info>(xc, current);
}
@ -85,4 +86,4 @@ class ThreadInfo
/* namespace Linux */ }
#endif // __KERN_LINUX_LINUX_THREADINFO_HH__
#endif // __ARCH_ALPHA_LINUX_LINUX_THREADINFO_HH__

61
arch/alpha/process.cc Normal file
View file

@ -0,0 +1,61 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/alpha/process.hh"
namespace AlphaISA
{
LiveProcess *
createProcess(const std::string &nm, ObjectFile * objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &envp)
{
LiveProcess * process = NULL;
if (objFile->getArch() != ObjectFile::Alpha)
fatal("Object file does not match architecture.");
switch (objFile->getOpSys()) {
case ObjectFile::Tru64:
process = new AlphaTru64Process(nm, objFile,
stdin_fd, stdout_fd, stderr_fd,
argv, envp);
break;
case ObjectFile::Linux:
process = new AlphaLinuxProcess(nm, objFile,
stdin_fd, stdout_fd, stderr_fd,
argv, envp);
break;
default:
fatal("Unknown/unsupported operating system.");
}
return process;
}
} // namespace AlphaISA

48
arch/alpha/process.hh Normal file
View file

@ -0,0 +1,48 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ALPHA_PROCESS_HH__
#define __ALPHA_PROCESS_HH__
#include <string>
#include "arch/alpha/linux/process.hh"
#include "arch/alpha/tru64/process.hh"
#include "base/loader/object_file.hh"
namespace AlphaISA
{
LiveProcess *
createProcess(const std::string &nm, ObjectFile * objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &envp);
} // namespace AlphaISA
#endif // __ALPHA_PROCESS_HH__

47
arch/alpha/stacktrace.cc
View file

@ -35,31 +35,33 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "sim/system.hh"
using namespace std;
using namespace AlphaISA;
ProcessInfo::ProcessInfo(ExecContext *_xc)
: xc(_xc)
{
Addr addr = 0;
if (!xc->system->kernelSymtab->findAddress("thread_info_size", addr))
if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
panic("thread info not compiled into kernel\n");
thread_info_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
if (!xc->system->kernelSymtab->findAddress("task_struct_size", addr))
if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
panic("thread info not compiled into kernel\n");
task_struct_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
if (!xc->system->kernelSymtab->findAddress("thread_info_task", addr))
if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
panic("thread info not compiled into kernel\n");
task_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
if (!xc->system->kernelSymtab->findAddress("task_struct_pid", addr))
if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
panic("thread info not compiled into kernel\n");
pid_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
if (!xc->system->kernelSymtab->findAddress("task_struct_comm", addr))
if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
panic("thread info not compiled into kernel\n");
name_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
}
@ -108,7 +110,7 @@ StackTrace::StackTrace()
{
}
StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr<TheISA> inst)
StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
: xc(0), stack(64)
{
trace(_xc, inst);
@ -123,10 +125,11 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
{
xc = _xc;
bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
Addr pc = xc->regs.npc;
bool kernel = xc->system->kernelStart <= pc && pc <= xc->system->kernelEnd;
Addr pc = xc->readNextPC();
bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
pc <= xc->getSystemPtr()->kernelEnd;
if (usermode) {
stack.push_back(user);
@ -138,8 +141,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
return;
}
SymbolTable *symtab = xc->system->kernelSymtab;
Addr ksp = xc->regs.intRegFile[TheISA::StackPointerReg];
SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
Addr ksp = xc->readIntReg(TheISA::StackPointerReg);
Addr bottom = ksp & ~0x3fff;
Addr addr;
@ -148,7 +151,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
panic("could not find address %#x", pc);
stack.push_back(addr);
pc = xc->regs.pc;
pc = xc->readPC();
}
Addr ra;
@ -180,8 +183,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
return;
}
bool kernel = xc->system->kernelStart <= pc &&
pc <= xc->system->kernelEnd;
bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
pc <= xc->getSystemPtr()->kernelEnd;
if (!kernel)
return;
@ -195,22 +198,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
bool
StackTrace::isEntry(Addr addr)
{
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp12])
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12))
return true;
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp7])
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7))
return true;
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp11])
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11))
return true;
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp21])
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21))
return true;
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp9])
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9))
return true;
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp2])
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2))
return true;
return false;
@ -322,8 +325,8 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
void
StackTrace::dump()
{
StringWrap name(xc->cpu->name());
SymbolTable *symtab = xc->system->kernelSymtab;
StringWrap name(xc->getCpuPtr()->name());
SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
DPRINTFN("------ Stack ------\n");

8
arch/alpha/stacktrace.hh
View file

@ -56,6 +56,8 @@ class ProcessInfo
class StackTrace
{
protected:
typedef TheISA::MachInst MachInst;
private:
ExecContext *xc;
std::vector<Addr> stack;
@ -70,7 +72,7 @@ class StackTrace
public:
StackTrace();
StackTrace(ExecContext *xc, StaticInstPtr<TheISA> inst);
StackTrace(ExecContext *xc, StaticInstPtr inst);
~StackTrace();
void clear()
@ -80,7 +82,7 @@ class StackTrace
}
bool valid() const { return xc != NULL; }
bool trace(ExecContext *xc, StaticInstPtr<TheISA> inst);
bool trace(ExecContext *xc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@ -102,7 +104,7 @@ class StackTrace
};
inline bool
StackTrace::trace(ExecContext *xc, StaticInstPtr<TheISA> inst)
StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;

299
arch/alpha/system.cc Normal file
View file

@ -0,0 +1,299 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/alpha/system.hh"
#include "arch/vtophys.hh"
#include "base/remote_gdb.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/byteswap.hh"
#include "sim/builder.hh"
using namespace LittleEndianGuest;
AlphaSystem::AlphaSystem(Params *p)
: System(p)
{
consoleSymtab = new SymbolTable;
palSymtab = new SymbolTable;
/**
* Load the pal, and console code into memory
*/
// Load Console Code
console = createObjectFile(params()->console_path);
if (console == NULL)
fatal("Could not load console file %s", params()->console_path);
// Load pal file
pal = createObjectFile(params()->palcode);
if (pal == NULL)
fatal("Could not load PALcode file %s", params()->palcode);
// Load program sections into memory
pal->loadSections(physmem, true);
console->loadSections(physmem, true);
// load symbols
if (!console->loadGlobalSymbols(consoleSymtab))
panic("could not load console symbols\n");
if (!pal->loadGlobalSymbols(palSymtab))
panic("could not load pal symbols\n");
if (!pal->loadLocalSymbols(palSymtab))
panic("could not load pal symbols\n");
if (!console->loadGlobalSymbols(debugSymbolTable))
panic("could not load console symbols\n");
if (!pal->loadGlobalSymbols(debugSymbolTable))
panic("could not load pal symbols\n");
if (!pal->loadLocalSymbols(debugSymbolTable))
panic("could not load pal symbols\n");
Addr addr = 0;
#ifndef NDEBUG
consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
#endif
/**
* Copy the osflags (kernel arguments) into the consoles
* memory. (Presently Linux does not use the console service
* routine to get these command line arguments, but Tru64 and
* others do.)
*/
if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
Addr paddr = vtophys(physmem, addr);
char *osflags = (char *)physmem->dma_addr(paddr, sizeof(uint32_t));
if (osflags)
strcpy(osflags, params()->boot_osflags.c_str());
}
/**
* Set the hardware reset parameter block system type and revision
* information to Tsunami.
*/
if (consoleSymtab->findAddress("m5_rpb", addr)) {
Addr paddr = vtophys(physmem, addr);
char *hwrpb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t));
if (!hwrpb)
panic("could not translate hwrpb addr\n");
*(uint64_t*)(hwrpb+0x50) = htog(params()->system_type);
*(uint64_t*)(hwrpb+0x58) = htog(params()->system_rev);
} else
panic("could not find hwrpb\n");
}
AlphaSystem::~AlphaSystem()
{
delete consoleSymtab;
delete console;
delete pal;
#ifdef DEBUG
delete consolePanicEvent;
#endif
}
/**
* This function fixes up addresses that are used to match PCs for
* hooking simulator events on to target function executions.
*
* Alpha binaries may have multiple global offset table (GOT)
* sections. A function that uses the GOT starts with a
* two-instruction prolog which sets the global pointer (gp == r29) to
* the appropriate GOT section. The proper gp value is calculated
* based on the function address, which must be passed by the caller
* in the procedure value register (pv aka t12 == r27). This sequence
* looks like the following:
*
* opcode Ra Rb offset
* ldah gp,X(pv) 09 29 27 X
* lda gp,Y(gp) 08 29 29 Y
*
* for some constant offsets X and Y. The catch is that the linker
* (or maybe even the compiler, I'm not sure) may recognize that the
* caller and callee are using the same GOT section, making this
* prolog redundant, and modify the call target to skip these
* instructions. If we check for execution of the first instruction
* of a function (the one the symbol points to) to detect when to skip
* it, we'll miss all these modified calls. It might work to
* unconditionally check for the third instruction, but not all
* functions have this prolog, and there's some chance that those
* first two instructions could have undesired consequences. So we do
* the Right Thing and pattern-match the first two instructions of the
* function to decide where to patch.
*
* Eventually this code should be moved into an ISA-specific file.
*/
Addr
AlphaSystem::fixFuncEventAddr(Addr addr)
{
// mask for just the opcode, Ra, and Rb fields (not the offset)
const uint32_t inst_mask = 0xffff0000;
// ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27
const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16);
// lda gp,Y(gp): opcode 8, Ra = 29, rb = 29
const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16);
// instruction size
const int sz = sizeof(uint32_t);
Addr paddr = vtophys(physmem, addr);
uint32_t i1 = *(uint32_t *)physmem->dma_addr(paddr, sz);
uint32_t i2 = *(uint32_t *)physmem->dma_addr(paddr+sz, sz);
if ((i1 & inst_mask) == gp_ldah_pattern &&
(i2 & inst_mask) == gp_lda_pattern) {
Addr new_addr = addr + 2*sz;
DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr);
return new_addr;
} else {
return addr;
}
}
void
AlphaSystem::setAlphaAccess(Addr access)
{
Addr addr = 0;
if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
Addr paddr = vtophys(physmem, addr);
uint64_t *m5AlphaAccess =
(uint64_t *)physmem->dma_addr(paddr, sizeof(uint64_t));
if (!m5AlphaAccess)
panic("could not translate m5AlphaAccess addr\n");
*m5AlphaAccess = htog(EV5::Phys2K0Seg(access));
} else
panic("could not find m5AlphaAccess\n");
}
bool
AlphaSystem::breakpoint()
{
return remoteGDB[0]->trap(ALPHA_KENTRY_INT);
}
void
AlphaSystem::serialize(std::ostream &os)
{
System::serialize(os);
consoleSymtab->serialize("console_symtab", os);
palSymtab->serialize("pal_symtab", os);
}
void
AlphaSystem::unserialize(Checkpoint *cp, const std::string &section)
{
System::unserialize(cp,section);
consoleSymtab->unserialize("console_symtab", cp, section);
palSymtab->unserialize("pal_symtab", cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<MemoryController *> memctrl;
SimObjectParam<PhysicalMemory *> physmem;
Param<std::string> kernel;
Param<std::string> console;
Param<std::string> pal;
Param<std::string> boot_osflags;
Param<std::string> readfile;
Param<unsigned int> init_param;
Param<uint64_t> system_type;
Param<uint64_t> system_rev;
Param<bool> bin;
VectorParam<std::string> binned_fns;
Param<bool> bin_int;
END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(memctrl, "memory controller"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
INIT_PARAM_DFLT(bin, "is this system to be binned", false),
INIT_PARAM(binned_fns, "functions to be broken down and binned"),
INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
CREATE_SIM_OBJECT(AlphaSystem)
{
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->memctrl = memctrl;
p->physmem = physmem;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
p->system_type = system_type;
p->system_rev = system_rev;
p->bin = bin;
p->binned_fns = binned_fns;
p->bin_int = bin_int;
return new AlphaSystem(p);
}
REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem)

109
arch/alpha/system.hh Normal file
View file

@ -0,0 +1,109 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ALPHA_SYSTEM_HH__
#define __ARCH_ALPHA_SYSTEM_HH__
#include <string>
#include <vector>
#include "sim/system.hh"
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
#include "sim/sim_object.hh"
class AlphaSystem : public System
{
public:
struct Params : public System::Params
{
std::string console_path;
std::string palcode;
std::string boot_osflags;
uint64_t system_type;
uint64_t system_rev;
};
AlphaSystem(Params *p);
~AlphaSystem();
virtual bool breakpoint();
/**
* Serialization stuff
*/
public:
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Set the m5AlphaAccess pointer in the console
*/
void setAlphaAccess(Addr access);
/** console symbol table */
SymbolTable *consoleSymtab;
/** pal symbol table */
SymbolTable *palSymtab;
/** Object pointer for the console code */
ObjectFile *console;
/** Object pointer for the PAL code */
ObjectFile *pal;
#ifndef NDEBUG
/** Event to halt the simulator if the console calls panic() */
BreakPCEvent *consolePanicEvent;
#endif
protected:
const Params *params() const { return (const Params *)_params; }
/** Add a function-based event to PALcode. */
template <class T>
T *AlphaSystem::addPalFuncEvent(const char *lbl)
{
return addFuncEvent<T>(palSymtab, lbl);
}
/** Add a function-based event to the console code. */
template <class T>
T *AlphaSystem::addConsoleFuncEvent(const char *lbl)
{
return addFuncEvent<T>(consoleSymtab, lbl);
}
virtual Addr fixFuncEventAddr(Addr addr);
};
#endif

88
arch/alpha/alpha_memory.cc → arch/alpha/tlb.cc
View file

@ -30,7 +30,7 @@
#include <string>
#include <vector>
#include "arch/alpha/alpha_memory.hh"
#include "arch/alpha/tlb.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
@ -293,12 +293,11 @@ AlphaITB::regStats()
void
AlphaITB::fault(Addr pc, ExecContext *xc) const
{
uint64_t *ipr = xc->regs.ipr;
if (!xc->misspeculating()) {
ipr[AlphaISA::IPR_ITB_TAG] = pc;
ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3);
xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
(AlphaISA::VAddr(pc).vpn() << 3));
}
}
@ -306,13 +305,13 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
Fault
AlphaITB::translate(MemReqPtr &req) const
{
InternalProcReg *ipr = req->xc->regs.ipr;
ExecContext *xc = req->xc;
if (AlphaISA::PcPAL(req->vaddr)) {
// strip off PAL PC marker (lsb is 1)
req->paddr = (req->vaddr & ~3) & PAddrImplMask;
hits++;
return No_Fault;
return NoFault;
}
if (req->flags & PHYSICAL) {
@ -322,24 +321,24 @@ AlphaITB::translate(MemReqPtr &req) const
if (!validVirtualAddress(req->vaddr)) {
fault(req->vaddr, req->xc);
acv++;
return ITB_Acv_Fault;
return new ItbAcvFault;
}
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->vaddr) == 2) {
#else
if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
#endif
// only valid in kernel mode
if (ICM_CM(ipr[AlphaISA::IPR_ICM]) !=
if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
AlphaISA::mode_kernel) {
fault(req->vaddr, req->xc);
acv++;
return ITB_Acv_Fault;
return new ItbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@ -354,24 +353,26 @@ AlphaITB::translate(MemReqPtr &req) const
} else {
// not a physical address: need to look up pte
int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
asn);
if (!pte) {
fault(req->vaddr, req->xc);
misses++;
return ITB_Fault_Fault;
return new ItbPageFault;
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
(AlphaISA::VAddr(req->vaddr).offset() & ~3);
// check permissions for this access
if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
if (!(pte->xre &
(1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
// instruction access fault
fault(req->vaddr, req->xc);
acv++;
return ITB_Acv_Fault;
return new ItbAcvFault;
}
hits++;
@ -380,11 +381,11 @@ AlphaITB::translate(MemReqPtr &req) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
return Machine_Check_Fault;
return genMachineCheckFault();
checkCacheability(req);
return No_Fault;
return NoFault;
}
///////////////////////////////////////////////////////////////////////
@ -469,7 +470,6 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
{
ExecContext *xc = req->xc;
AlphaISA::VAddr vaddr = req->vaddr;
uint64_t *ipr = xc->regs.ipr;
// Set fault address and flags. Even though we're modeling an
// EV5, we use the EV6 technique of not latching fault registers
@ -479,29 +479,28 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
if (!xc->misspeculating()
&& !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
// set VA register with faulting address
ipr[AlphaISA::IPR_VA] = req->vaddr;
xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr);
// set MM_STAT register flags
ipr[AlphaISA::IPR_MM_STAT] =
xc->setMiscReg(AlphaISA::IPR_MM_STAT,
(((Opcode(xc->getInst()) & 0x3f) << 11)
| ((Ra(xc->getInst()) & 0x1f) << 6)
| (flags & 0x3f));
| (flags & 0x3f)));
// set VA_FORM register with faulting formatted address
ipr[AlphaISA::IPR_VA_FORM] =
ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3);
xc->setMiscReg(AlphaISA::IPR_VA_FORM,
xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
}
}
Fault
AlphaDTB::translate(MemReqPtr &req, bool write) const
{
RegFile *regs = &req->xc->regs;
Addr pc = regs->pc;
InternalProcReg *ipr = regs->ipr;
ExecContext *xc = req->xc;
Addr pc = xc->readPC();
AlphaISA::mode_type mode =
(AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
(AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
/**
@ -511,12 +510,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, write ? MM_STAT_WR_MASK : 0);
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
req->size);
return Alignment_Fault;
return genAlignmentFault();
}
if (pc & 0x1) {
mode = (req->flags & ALTMODE) ?
(AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
(AlphaISA::mode_type)ALT_MODE_AM(
xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
: AlphaISA::mode_kernel;
}
@ -530,24 +530,24 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK);
if (write) { write_acv++; } else { read_acv++; }
return DTB_Fault_Fault;
return new DtbPageFault;
}
// Check for "superpage" mapping
#if ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->vaddr) == 2) {
#else
if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
#endif
// only valid in kernel mode
if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
AlphaISA::mode_kernel) {
fault(req, ((write ? MM_STAT_WR_MASK : 0) |
MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
return DTB_Acv_Fault;
return new DtbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@ -566,16 +566,20 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
else
read_accesses++;
int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
// not a physical address: need to look up pte
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
asn);
if (!pte) {
// page fault
fault(req, (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
return (req->flags & VPTE) ?
(Fault)(new PDtbMissFault) :
(Fault)(new NDtbMissFault);
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@ -588,25 +592,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK |
(pte->fonw ? MM_STAT_FONW_MASK : 0));
write_acv++;
return DTB_Fault_Fault;
return new DtbPageFault;
}
if (pte->fonw) {
fault(req, MM_STAT_WR_MASK |
MM_STAT_FONW_MASK);
write_acv++;
return DTB_Fault_Fault;
return new DtbPageFault;
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
fault(req, MM_STAT_ACV_MASK |
(pte->fonr ? MM_STAT_FONR_MASK : 0));
read_acv++;
return DTB_Acv_Fault;
return new DtbAcvFault;
}
if (pte->fonr) {
fault(req, MM_STAT_FONR_MASK);
read_acv++;
return DTB_Fault_Fault;
return new DtbPageFault;
}
}
}
@ -619,11 +623,11 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
return Machine_Check_Fault;
return genMachineCheckFault();
checkCacheability(req);
return No_Fault;
return NoFault;
}
AlphaISA::PTE &

1
arch/alpha/alpha_memory.hh → arch/alpha/tlb.hh
View file

@ -32,6 +32,7 @@
#include <map>
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/faults.hh"
#include "base/statistics.hh"
#include "mem/mem_req.hh"
#include "sim/sim_object.hh"

543
arch/alpha/tru64/process.cc Normal file
View file

@ -0,0 +1,543 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/tru64/process.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64.hh"
#include "mem/functional/functional.hh"
#include "sim/fake_syscall.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
using namespace std;
using namespace AlphaISA;
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
TypedBufferArg<Tru64::utsname> name(xc->getSyscallArg(0));
strcpy(name->sysname, "OSF1");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->release, "V5.1");
strcpy(name->version, "732");
strcpy(name->machine, "alpha");
name.copyOut(xc->getMemPtr());
return 0;
}
/// Target getsysyinfo() handler.
static SyscallReturn
getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
unsigned nbytes = xc->getSyscallArg(2);
switch (op) {
case Tru64::GSI_MAX_CPU: {
TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1));
*max_cpu = htog((uint32_t)process->numCpus());
max_cpu.copyOut(xc->getMemPtr());
return 1;
}
case Tru64::GSI_CPUS_IN_BOX: {
TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1));
*cpus_in_box = htog((uint32_t)process->numCpus());
cpus_in_box.copyOut(xc->getMemPtr());
return 1;
}
case Tru64::GSI_PHYSMEM: {
TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1));
*physmem = htog((uint64_t)1024 * 1024); // physical memory in KB
physmem.copyOut(xc->getMemPtr());
return 1;
}
case Tru64::GSI_CPU_INFO: {
TypedBufferArg<Tru64::cpu_info> infop(xc->getSyscallArg(1));
infop->current_cpu = htog(0);
infop->cpus_in_box = htog(process->numCpus());
infop->cpu_type = htog(57);
infop->ncpus = htog(process->numCpus());
uint64_t cpumask = (1 << process->numCpus()) - 1;
infop->cpus_present = infop->cpus_running = htog(cpumask);
infop->cpu_binding = htog(0);
infop->cpu_ex_binding = htog(0);
infop->mhz = htog(667);
infop.copyOut(xc->getMemPtr());
return 1;
}
case Tru64::GSI_PROC_TYPE: {
TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1));
*proc_type = htog((uint64_t)11);
proc_type.copyOut(xc->getMemPtr());
return 1;
}
case Tru64::GSI_PLATFORM_NAME: {
BufferArg bufArg(xc->getSyscallArg(1), nbytes);
strncpy((char *)bufArg.bufferPtr(),
"COMPAQ Professional Workstation XP1000",
nbytes);
bufArg.copyOut(xc->getMemPtr());
return 1;
}
case Tru64::GSI_CLK_TCK: {
TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1));
*clk_hz = htog((uint64_t)1024);
clk_hz.copyOut(xc->getMemPtr());
return 1;
}
default:
warn("getsysinfo: unknown op %d\n", op);
break;
}
return 0;
}
/// Target setsysyinfo() handler.
static SyscallReturn
setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
switch (op) {
case Tru64::SSI_IEEE_FP_CONTROL:
warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n",
xc->getSyscallArg(1));
break;
default:
warn("setsysinfo: unknown op %d\n", op);
break;
}
return 0;
}
SyscallDesc AlphaTru64Process::syscallDescs[] = {
/* 0 */ SyscallDesc("syscall (#0)", Tru64::indirectSyscallFunc,
SyscallDesc::SuppressReturnValue),
/* 1 */ SyscallDesc("exit", exitFunc),
/* 2 */ SyscallDesc("fork", unimplementedFunc),
/* 3 */ SyscallDesc("read", readFunc),
/* 4 */ SyscallDesc("write", writeFunc),
/* 5 */ SyscallDesc("old_open", unimplementedFunc),
/* 6 */ SyscallDesc("close", closeFunc),
/* 7 */ SyscallDesc("wait4", unimplementedFunc),
/* 8 */ SyscallDesc("old_creat", unimplementedFunc),
/* 9 */ SyscallDesc("link", unimplementedFunc),
/* 10 */ SyscallDesc("unlink", unlinkFunc),
/* 11 */ SyscallDesc("execv", unimplementedFunc),
/* 12 */ SyscallDesc("chdir", unimplementedFunc),
/* 13 */ SyscallDesc("fchdir", unimplementedFunc),
/* 14 */ SyscallDesc("mknod", unimplementedFunc),
/* 15 */ SyscallDesc("chmod", unimplementedFunc),
/* 16 */ SyscallDesc("chown", unimplementedFunc),
/* 17 */ SyscallDesc("obreak", obreakFunc),
/* 18 */ SyscallDesc("pre_F64_getfsstat", unimplementedFunc),
/* 19 */ SyscallDesc("lseek", lseekFunc),
/* 20 */ SyscallDesc("getpid", getpidPseudoFunc),
/* 21 */ SyscallDesc("mount", unimplementedFunc),
/* 22 */ SyscallDesc("unmount", unimplementedFunc),
/* 23 */ SyscallDesc("setuid", setuidFunc),
/* 24 */ SyscallDesc("getuid", getuidPseudoFunc),
/* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc),
/* 26 */ SyscallDesc("ptrace", unimplementedFunc),
/* 27 */ SyscallDesc("recvmsg", unimplementedFunc),
/* 28 */ SyscallDesc("sendmsg", unimplementedFunc),
/* 29 */ SyscallDesc("recvfrom", unimplementedFunc),
/* 30 */ SyscallDesc("accept", unimplementedFunc),
/* 31 */ SyscallDesc("getpeername", unimplementedFunc),
/* 32 */ SyscallDesc("getsockname", unimplementedFunc),
/* 33 */ SyscallDesc("access", unimplementedFunc),
/* 34 */ SyscallDesc("chflags", unimplementedFunc),
/* 35 */ SyscallDesc("fchflags", unimplementedFunc),
/* 36 */ SyscallDesc("sync", unimplementedFunc),
/* 37 */ SyscallDesc("kill", unimplementedFunc),
/* 38 */ SyscallDesc("old_stat", unimplementedFunc),
/* 39 */ SyscallDesc("setpgid", unimplementedFunc),
/* 40 */ SyscallDesc("old_lstat", unimplementedFunc),
/* 41 */ SyscallDesc("dup", unimplementedFunc),
/* 42 */ SyscallDesc("pipe", unimplementedFunc),
/* 43 */ SyscallDesc("set_program_attributes", unimplementedFunc),
/* 44 */ SyscallDesc("profil", unimplementedFunc),
/* 45 */ SyscallDesc("open", openFunc<Tru64>),
/* 46 */ SyscallDesc("obsolete osigaction", unimplementedFunc),
/* 47 */ SyscallDesc("getgid", getgidPseudoFunc),
/* 48 */ SyscallDesc("sigprocmask", ignoreFunc),
/* 49 */ SyscallDesc("getlogin", unimplementedFunc),
/* 50 */ SyscallDesc("setlogin", unimplementedFunc),
/* 51 */ SyscallDesc("acct", unimplementedFunc),
/* 52 */ SyscallDesc("sigpending", unimplementedFunc),
/* 53 */ SyscallDesc("classcntl", unimplementedFunc),
/* 54 */ SyscallDesc("ioctl", ioctlFunc<Tru64>),
/* 55 */ SyscallDesc("reboot", unimplementedFunc),
/* 56 */ SyscallDesc("revoke", unimplementedFunc),
/* 57 */ SyscallDesc("symlink", unimplementedFunc),
/* 58 */ SyscallDesc("readlink", unimplementedFunc),
/* 59 */ SyscallDesc("execve", unimplementedFunc),
/* 60 */ SyscallDesc("umask", unimplementedFunc),
/* 61 */ SyscallDesc("chroot", unimplementedFunc),
/* 62 */ SyscallDesc("old_fstat", unimplementedFunc),
/* 63 */ SyscallDesc("getpgrp", unimplementedFunc),
/* 64 */ SyscallDesc("getpagesize", getpagesizeFunc),
/* 65 */ SyscallDesc("mremap", unimplementedFunc),
/* 66 */ SyscallDesc("vfork", unimplementedFunc),
/* 67 */ SyscallDesc("pre_F64_stat", statFunc<Tru64::PreF64>),
/* 68 */ SyscallDesc("pre_F64_lstat", lstatFunc<Tru64::PreF64>),
/* 69 */ SyscallDesc("sbrk", unimplementedFunc),
/* 70 */ SyscallDesc("sstk", unimplementedFunc),
/* 71 */ SyscallDesc("mmap", mmapFunc<Tru64>),
/* 72 */ SyscallDesc("ovadvise", unimplementedFunc),
/* 73 */ SyscallDesc("munmap", munmapFunc),
/* 74 */ SyscallDesc("mprotect", ignoreFunc),
/* 75 */ SyscallDesc("madvise", unimplementedFunc),
/* 76 */ SyscallDesc("old_vhangup", unimplementedFunc),
/* 77 */ SyscallDesc("kmodcall", unimplementedFunc),
/* 78 */ SyscallDesc("mincore", unimplementedFunc),
/* 79 */ SyscallDesc("getgroups", unimplementedFunc),
/* 80 */ SyscallDesc("setgroups", unimplementedFunc),
/* 81 */ SyscallDesc("old_getpgrp", unimplementedFunc),
/* 82 */ SyscallDesc("setpgrp", unimplementedFunc),
/* 83 */ SyscallDesc("setitimer", unimplementedFunc),
/* 84 */ SyscallDesc("old_wait", unimplementedFunc),
/* 85 */ SyscallDesc("table", Tru64::tableFunc),
/* 86 */ SyscallDesc("getitimer", unimplementedFunc),
/* 87 */ SyscallDesc("gethostname", gethostnameFunc),
/* 88 */ SyscallDesc("sethostname", unimplementedFunc),
/* 89 */ SyscallDesc("getdtablesize", unimplementedFunc),
/* 90 */ SyscallDesc("dup2", unimplementedFunc),
/* 91 */ SyscallDesc("pre_F64_fstat", fstatFunc<Tru64::PreF64>),
/* 92 */ SyscallDesc("fcntl", fcntlFunc),
/* 93 */ SyscallDesc("select", unimplementedFunc),
/* 94 */ SyscallDesc("poll", unimplementedFunc),
/* 95 */ SyscallDesc("fsync", unimplementedFunc),
/* 96 */ SyscallDesc("setpriority", unimplementedFunc),
/* 97 */ SyscallDesc("socket", unimplementedFunc),
/* 98 */ SyscallDesc("connect", unimplementedFunc),
/* 99 */ SyscallDesc("old_accept", unimplementedFunc),
/* 100 */ SyscallDesc("getpriority", unimplementedFunc),
/* 101 */ SyscallDesc("old_send", unimplementedFunc),
/* 102 */ SyscallDesc("old_recv", unimplementedFunc),
/* 103 */ SyscallDesc("sigreturn", Tru64::sigreturnFunc,
SyscallDesc::SuppressReturnValue),
/* 104 */ SyscallDesc("bind", unimplementedFunc),
/* 105 */ SyscallDesc("setsockopt", unimplementedFunc),
/* 106 */ SyscallDesc("listen", unimplementedFunc),
/* 107 */ SyscallDesc("plock", unimplementedFunc),
/* 108 */ SyscallDesc("old_sigvec", unimplementedFunc),
/* 109 */ SyscallDesc("old_sigblock", unimplementedFunc),
/* 110 */ SyscallDesc("old_sigsetmask", unimplementedFunc),
/* 111 */ SyscallDesc("sigsuspend", unimplementedFunc),
/* 112 */ SyscallDesc("sigstack", ignoreFunc),
/* 113 */ SyscallDesc("old_recvmsg", unimplementedFunc),
/* 114 */ SyscallDesc("old_sendmsg", unimplementedFunc),
/* 115 */ SyscallDesc("obsolete vtrace", unimplementedFunc),
/* 116 */ SyscallDesc("gettimeofday", gettimeofdayFunc<Tru64>),
/* 117 */ SyscallDesc("getrusage", getrusageFunc<Tru64>),
/* 118 */ SyscallDesc("getsockopt", unimplementedFunc),
/* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc),
/* 120 */ SyscallDesc("readv", unimplementedFunc),
/* 121 */ SyscallDesc("writev", unimplementedFunc),
/* 122 */ SyscallDesc("settimeofday", unimplementedFunc),
/* 123 */ SyscallDesc("fchown", unimplementedFunc),
/* 124 */ SyscallDesc("fchmod", unimplementedFunc),
/* 125 */ SyscallDesc("old_recvfrom", unimplementedFunc),
/* 126 */ SyscallDesc("setreuid", unimplementedFunc),
/* 127 */ SyscallDesc("setregid", unimplementedFunc),
/* 128 */ SyscallDesc("rename", renameFunc),
/* 129 */ SyscallDesc("truncate", truncateFunc),
/* 130 */ SyscallDesc("ftruncate", ftruncateFunc),
/* 131 */ SyscallDesc("flock", unimplementedFunc),
/* 132 */ SyscallDesc("setgid", unimplementedFunc),
/* 133 */ SyscallDesc("sendto", unimplementedFunc),
/* 134 */ SyscallDesc("shutdown", unimplementedFunc),
/* 135 */ SyscallDesc("socketpair", unimplementedFunc),
/* 136 */ SyscallDesc("mkdir", unimplementedFunc),
/* 137 */ SyscallDesc("rmdir", unimplementedFunc),
/* 138 */ SyscallDesc("utimes", unimplementedFunc),
/* 139 */ SyscallDesc("obsolete 4.2 sigreturn", unimplementedFunc),
/* 140 */ SyscallDesc("adjtime", unimplementedFunc),
/* 141 */ SyscallDesc("old_getpeername", unimplementedFunc),
/* 142 */ SyscallDesc("gethostid", unimplementedFunc),
/* 143 */ SyscallDesc("sethostid", unimplementedFunc),
/* 144 */ SyscallDesc("getrlimit", getrlimitFunc<Tru64>),
/* 145 */ SyscallDesc("setrlimit", ignoreFunc),
/* 146 */ SyscallDesc("old_killpg", unimplementedFunc),
/* 147 */ SyscallDesc("setsid", unimplementedFunc),
/* 148 */ SyscallDesc("quotactl", unimplementedFunc),
/* 149 */ SyscallDesc("oldquota", unimplementedFunc),
/* 150 */ SyscallDesc("old_getsockname", unimplementedFunc),
/* 151 */ SyscallDesc("pread", unimplementedFunc),
/* 152 */ SyscallDesc("pwrite", unimplementedFunc),
/* 153 */ SyscallDesc("pid_block", unimplementedFunc),
/* 154 */ SyscallDesc("pid_unblock", unimplementedFunc),
/* 155 */ SyscallDesc("signal_urti", unimplementedFunc),
/* 156 */ SyscallDesc("sigaction", ignoreFunc),
/* 157 */ SyscallDesc("sigwaitprim", unimplementedFunc),
/* 158 */ SyscallDesc("nfssvc", unimplementedFunc),
/* 159 */ SyscallDesc("getdirentries", Tru64::getdirentriesFunc),
/* 160 */ SyscallDesc("pre_F64_statfs", statfsFunc<Tru64::PreF64>),
/* 161 */ SyscallDesc("pre_F64_fstatfs", fstatfsFunc<Tru64::PreF64>),
/* 162 */ SyscallDesc("unknown #162", unimplementedFunc),
/* 163 */ SyscallDesc("async_daemon", unimplementedFunc),
/* 164 */ SyscallDesc("getfh", unimplementedFunc),
/* 165 */ SyscallDesc("getdomainname", unimplementedFunc),
/* 166 */ SyscallDesc("setdomainname", unimplementedFunc),
/* 167 */ SyscallDesc("unknown #167", unimplementedFunc),
/* 168 */ SyscallDesc("unknown #168", unimplementedFunc),
/* 169 */ SyscallDesc("exportfs", unimplementedFunc),
/* 170 */ SyscallDesc("unknown #170", unimplementedFunc),
/* 171 */ SyscallDesc("unknown #171", unimplementedFunc),
/* 172 */ SyscallDesc("unknown #172", unimplementedFunc),
/* 173 */ SyscallDesc("unknown #173", unimplementedFunc),
/* 174 */ SyscallDesc("unknown #174", unimplementedFunc),
/* 175 */ SyscallDesc("unknown #175", unimplementedFunc),
/* 176 */ SyscallDesc("unknown #176", unimplementedFunc),
/* 177 */ SyscallDesc("unknown #177", unimplementedFunc),
/* 178 */ SyscallDesc("unknown #178", unimplementedFunc),
/* 179 */ SyscallDesc("unknown #179", unimplementedFunc),
/* 180 */ SyscallDesc("unknown #180", unimplementedFunc),
/* 181 */ SyscallDesc("alt_plock", unimplementedFunc),
/* 182 */ SyscallDesc("unknown #182", unimplementedFunc),
/* 183 */ SyscallDesc("unknown #183", unimplementedFunc),
/* 184 */ SyscallDesc("getmnt", unimplementedFunc),
/* 185 */ SyscallDesc("unknown #185", unimplementedFunc),
/* 186 */ SyscallDesc("unknown #186", unimplementedFunc),
/* 187 */ SyscallDesc("alt_sigpending", unimplementedFunc),
/* 188 */ SyscallDesc("alt_setsid", unimplementedFunc),
/* 189 */ SyscallDesc("unknown #189", unimplementedFunc),
/* 190 */ SyscallDesc("unknown #190", unimplementedFunc),
/* 191 */ SyscallDesc("unknown #191", unimplementedFunc),
/* 192 */ SyscallDesc("unknown #192", unimplementedFunc),
/* 193 */ SyscallDesc("unknown #193", unimplementedFunc),
/* 194 */ SyscallDesc("unknown #194", unimplementedFunc),
/* 195 */ SyscallDesc("unknown #195", unimplementedFunc),
/* 196 */ SyscallDesc("unknown #196", unimplementedFunc),
/* 197 */ SyscallDesc("unknown #197", unimplementedFunc),
/* 198 */ SyscallDesc("unknown #198", unimplementedFunc),
/* 199 */ SyscallDesc("swapon", unimplementedFunc),
/* 200 */ SyscallDesc("msgctl", unimplementedFunc),
/* 201 */ SyscallDesc("msgget", unimplementedFunc),
/* 202 */ SyscallDesc("msgrcv", unimplementedFunc),
/* 203 */ SyscallDesc("msgsnd", unimplementedFunc),
/* 204 */ SyscallDesc("semctl", unimplementedFunc),
/* 205 */ SyscallDesc("semget", unimplementedFunc),
/* 206 */ SyscallDesc("semop", unimplementedFunc),
/* 207 */ SyscallDesc("uname", unameFunc),
/* 208 */ SyscallDesc("lchown", unimplementedFunc),
/* 209 */ SyscallDesc("shmat", unimplementedFunc),
/* 210 */ SyscallDesc("shmctl", unimplementedFunc),
/* 211 */ SyscallDesc("shmdt", unimplementedFunc),
/* 212 */ SyscallDesc("shmget", unimplementedFunc),
/* 213 */ SyscallDesc("mvalid", unimplementedFunc),
/* 214 */ SyscallDesc("getaddressconf", unimplementedFunc),
/* 215 */ SyscallDesc("msleep", unimplementedFunc),
/* 216 */ SyscallDesc("mwakeup", unimplementedFunc),
/* 217 */ SyscallDesc("msync", unimplementedFunc),
/* 218 */ SyscallDesc("signal", unimplementedFunc),
/* 219 */ SyscallDesc("utc_gettime", unimplementedFunc),
/* 220 */ SyscallDesc("utc_adjtime", unimplementedFunc),
/* 221 */ SyscallDesc("unknown #221", unimplementedFunc),
/* 222 */ SyscallDesc("security", unimplementedFunc),
/* 223 */ SyscallDesc("kloadcall", unimplementedFunc),
/* 224 */ SyscallDesc("stat", statFunc<Tru64::F64>),
/* 225 */ SyscallDesc("lstat", lstatFunc<Tru64::F64>),
/* 226 */ SyscallDesc("fstat", fstatFunc<Tru64::F64>),
/* 227 */ SyscallDesc("statfs", statfsFunc<Tru64::F64>),
/* 228 */ SyscallDesc("fstatfs", fstatfsFunc<Tru64::F64>),
/* 229 */ SyscallDesc("getfsstat", unimplementedFunc),
/* 230 */ SyscallDesc("gettimeofday64", unimplementedFunc),
/* 231 */ SyscallDesc("settimeofday64", unimplementedFunc),
/* 232 */ SyscallDesc("unknown #232", unimplementedFunc),
/* 233 */ SyscallDesc("getpgid", unimplementedFunc),
/* 234 */ SyscallDesc("getsid", unimplementedFunc),
/* 235 */ SyscallDesc("sigaltstack", ignoreFunc),
/* 236 */ SyscallDesc("waitid", unimplementedFunc),
/* 237 */ SyscallDesc("priocntlset", unimplementedFunc),
/* 238 */ SyscallDesc("sigsendset", unimplementedFunc),
/* 239 */ SyscallDesc("set_speculative", unimplementedFunc),
/* 240 */ SyscallDesc("msfs_syscall", unimplementedFunc),
/* 241 */ SyscallDesc("sysinfo", unimplementedFunc),
/* 242 */ SyscallDesc("uadmin", unimplementedFunc),
/* 243 */ SyscallDesc("fuser", unimplementedFunc),
/* 244 */ SyscallDesc("proplist_syscall", unimplementedFunc),
/* 245 */ SyscallDesc("ntp_adjtime", unimplementedFunc),
/* 246 */ SyscallDesc("ntp_gettime", unimplementedFunc),
/* 247 */ SyscallDesc("pathconf", unimplementedFunc),
/* 248 */ SyscallDesc("fpathconf", unimplementedFunc),
/* 249 */ SyscallDesc("sync2", unimplementedFunc),
/* 250 */ SyscallDesc("uswitch", unimplementedFunc),
/* 251 */ SyscallDesc("usleep_thread", unimplementedFunc),
/* 252 */ SyscallDesc("audcntl", unimplementedFunc),
/* 253 */ SyscallDesc("audgen", unimplementedFunc),
/* 254 */ SyscallDesc("sysfs", unimplementedFunc),
/* 255 */ SyscallDesc("subsys_info", unimplementedFunc),
/* 256 */ SyscallDesc("getsysinfo", getsysinfoFunc),
/* 257 */ SyscallDesc("setsysinfo", setsysinfoFunc),
/* 258 */ SyscallDesc("afs_syscall", unimplementedFunc),
/* 259 */ SyscallDesc("swapctl", unimplementedFunc),
/* 260 */ SyscallDesc("memcntl", unimplementedFunc),
/* 261 */ SyscallDesc("fdatasync", unimplementedFunc),
/* 262 */ SyscallDesc("oflock", unimplementedFunc),
/* 263 */ SyscallDesc("F64_readv", unimplementedFunc),
/* 264 */ SyscallDesc("F64_writev", unimplementedFunc),
/* 265 */ SyscallDesc("cdslxlate", unimplementedFunc),
/* 266 */ SyscallDesc("sendfile", unimplementedFunc),
};
SyscallDesc AlphaTru64Process::machSyscallDescs[] = {
/* 0 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 1 */ SyscallDesc("m5_mutex_lock", Tru64::m5_mutex_lockFunc),
/* 2 */ SyscallDesc("m5_mutex_trylock", Tru64::m5_mutex_trylockFunc),
/* 3 */ SyscallDesc("m5_mutex_unlock", Tru64::m5_mutex_unlockFunc),
/* 4 */ SyscallDesc("m5_cond_signal", Tru64::m5_cond_signalFunc),
/* 5 */ SyscallDesc("m5_cond_broadcast", Tru64::m5_cond_broadcastFunc),
/* 6 */ SyscallDesc("m5_cond_wait", Tru64::m5_cond_waitFunc),
/* 7 */ SyscallDesc("m5_thread_exit", Tru64::m5_thread_exitFunc),
/* 8 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 9 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 10 */ SyscallDesc("task_self", unimplementedFunc),
/* 11 */ SyscallDesc("thread_reply", unimplementedFunc),
/* 12 */ SyscallDesc("task_notify", unimplementedFunc),
/* 13 */ SyscallDesc("thread_self", unimplementedFunc),
/* 14 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 15 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 16 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 17 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 18 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 19 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 20 */ SyscallDesc("msg_send_trap", unimplementedFunc),
/* 21 */ SyscallDesc("msg_receive_trap", unimplementedFunc),
/* 22 */ SyscallDesc("msg_rpc_trap", unimplementedFunc),
/* 23 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 24 */ SyscallDesc("nxm_block", Tru64::nxm_blockFunc),
/* 25 */ SyscallDesc("nxm_unblock", Tru64::nxm_unblockFunc),
/* 26 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 27 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 28 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 29 */ SyscallDesc("nxm_thread_destroy", unimplementedFunc),
/* 30 */ SyscallDesc("lw_wire", unimplementedFunc),
/* 31 */ SyscallDesc("lw_unwire", unimplementedFunc),
/* 32 */ SyscallDesc("nxm_thread_create", Tru64::nxm_thread_createFunc),
/* 33 */ SyscallDesc("nxm_task_init", Tru64::nxm_task_initFunc),
/* 34 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 35 */ SyscallDesc("nxm_idle", Tru64::nxm_idleFunc),
/* 36 */ SyscallDesc("nxm_wakeup_idle", unimplementedFunc),
/* 37 */ SyscallDesc("nxm_set_pthid", unimplementedFunc),
/* 38 */ SyscallDesc("nxm_thread_kill", unimplementedFunc),
/* 39 */ SyscallDesc("nxm_thread_block", Tru64::nxm_thread_blockFunc),
/* 40 */ SyscallDesc("nxm_thread_wakeup", unimplementedFunc),
/* 41 */ SyscallDesc("init_process", unimplementedFunc),
/* 42 */ SyscallDesc("nxm_get_binding", unimplementedFunc),
/* 43 */ SyscallDesc("map_fd", unimplementedFunc),
/* 44 */ SyscallDesc("nxm_resched", unimplementedFunc),
/* 45 */ SyscallDesc("nxm_set_cancel", unimplementedFunc),
/* 46 */ SyscallDesc("nxm_set_binding", unimplementedFunc),
/* 47 */ SyscallDesc("stack_create", Tru64::stack_createFunc),
/* 48 */ SyscallDesc("nxm_get_state", unimplementedFunc),
/* 49 */ SyscallDesc("nxm_thread_suspend", unimplementedFunc),
/* 50 */ SyscallDesc("nxm_thread_resume", unimplementedFunc),
/* 51 */ SyscallDesc("nxm_signal_check", unimplementedFunc),
/* 52 */ SyscallDesc("htg_unix_syscall", unimplementedFunc),
/* 53 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 54 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 55 */ SyscallDesc("host_self", unimplementedFunc),
/* 56 */ SyscallDesc("host_priv_self", unimplementedFunc),
/* 57 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 58 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 59 */ SyscallDesc("swtch_pri", Tru64::swtch_priFunc),
/* 60 */ SyscallDesc("swtch", unimplementedFunc),
/* 61 */ SyscallDesc("thread_switch", unimplementedFunc),
/* 62 */ SyscallDesc("semop_fast", unimplementedFunc),
/* 63 */ SyscallDesc("nxm_pshared_init", unimplementedFunc),
/* 64 */ SyscallDesc("nxm_pshared_block", unimplementedFunc),
/* 65 */ SyscallDesc("nxm_pshared_unblock", unimplementedFunc),
/* 66 */ SyscallDesc("nxm_pshared_destroy", unimplementedFunc),
/* 67 */ SyscallDesc("nxm_swtch_pri", Tru64::swtch_priFunc),
/* 68 */ SyscallDesc("lw_syscall", unimplementedFunc),
/* 69 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 70 */ SyscallDesc("mach_sctimes_0", unimplementedFunc),
/* 71 */ SyscallDesc("mach_sctimes_1", unimplementedFunc),
/* 72 */ SyscallDesc("mach_sctimes_2", unimplementedFunc),
/* 73 */ SyscallDesc("mach_sctimes_3", unimplementedFunc),
/* 74 */ SyscallDesc("mach_sctimes_4", unimplementedFunc),
/* 75 */ SyscallDesc("mach_sctimes_5", unimplementedFunc),
/* 76 */ SyscallDesc("mach_sctimes_6", unimplementedFunc),
/* 77 */ SyscallDesc("mach_sctimes_7", unimplementedFunc),
/* 78 */ SyscallDesc("mach_sctimes_8", unimplementedFunc),
/* 79 */ SyscallDesc("mach_sctimes_9", unimplementedFunc),
/* 80 */ SyscallDesc("mach_sctimes_10", unimplementedFunc),
/* 81 */ SyscallDesc("mach_sctimes_11", unimplementedFunc),
/* 82 */ SyscallDesc("mach_sctimes_port_alloc_dealloc", unimplementedFunc)
};
SyscallDesc*
AlphaTru64Process::getDesc(int callnum)
{
if (callnum < -Num_Mach_Syscall_Descs || callnum > Num_Syscall_Descs)
return NULL;
if (callnum < 0)
return &machSyscallDescs[-callnum];
else
return &syscallDescs[callnum];
}
AlphaTru64Process::AlphaTru64Process(const std::string &name,
ObjectFile *objFile,
int stdin_fd,
int stdout_fd,
int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp)
: LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)),
Num_Mach_Syscall_Descs(sizeof(machSyscallDescs) / sizeof(SyscallDesc))
{
}

12
arch/alpha/alpha_tru64_process.hh → arch/alpha/tru64/process.hh
View file

@ -43,8 +43,16 @@ class AlphaTru64Process : public LiveProcess
std::vector<std::string> &argv,
std::vector<std::string> &envp);
/// Syscall emulation function.
virtual void syscall(ExecContext *xc);
/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
/// Array of mach syscall descriptors, indexed by call number.
static SyscallDesc machSyscallDescs[];
const int Num_Syscall_Descs;
const int Num_Mach_Syscall_Descs;
virtual SyscallDesc* getDesc(int callnum);
};

28
kern/tru64/tru64_system.cc → arch/alpha/tru64/system.cc
View file

@ -26,23 +26,23 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/alpha/tru64/system.hh"
#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64_events.hh"
#include "kern/tru64/tru64_system.hh"
#include "kern/system_events.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/builder.hh"
#include "targetarch/isa_traits.hh"
#include "targetarch/vtophys.hh"
using namespace std;
Tru64System::Tru64System(Tru64System::Params *p)
: System(p)
Tru64AlphaSystem::Tru64AlphaSystem(Tru64AlphaSystem::Params *p)
: AlphaSystem(p)
{
Addr addr = 0;
if (kernelSymtab->findAddress("enable_async_printf", addr)) {
@ -77,7 +77,7 @@ Tru64System::Tru64System(Tru64System::Params *p)
#endif
}
Tru64System::~Tru64System()
Tru64AlphaSystem::~Tru64AlphaSystem()
{
#ifdef DEBUG
delete kernelPanicEvent;
@ -93,7 +93,7 @@ Tru64System::~Tru64System()
#endif
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<MemoryController *> memctrl;
@ -113,9 +113,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
Param<bool> bin;
VectorParam<string> binned_fns;
END_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64System)
BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
INIT_PARAM(memctrl, "memory controller"),
@ -132,11 +132,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64System)
INIT_PARAM_DFLT(bin, "is this system to be binned", false),
INIT_PARAM(binned_fns, "functions to be broken down and binned")
END_INIT_SIM_OBJECT_PARAMS(Tru64System)
END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
CREATE_SIM_OBJECT(Tru64System)
CREATE_SIM_OBJECT(Tru64AlphaSystem)
{
System::Params *p = new System::Params;
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->memctrl = memctrl;
@ -153,7 +153,7 @@ CREATE_SIM_OBJECT(Tru64System)
p->binned_fns = binned_fns;
p->bin_int = false;
return new Tru64System(p);
return new Tru64AlphaSystem(p);
}
REGISTER_SIM_OBJECT("Tru64System", Tru64System)
REGISTER_SIM_OBJECT("Tru64AlphaSystem", Tru64AlphaSystem)

16
kern/tru64/tru64_system.hh → arch/alpha/tru64/system.hh
View file

@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __KERN_TRU64_TRU64_SYSTEM_HH__
#define __KERN_TRU64_TRU64_SYSTEM_HH__
#ifndef __ARCH_ALPHA_TRU64_SYSTEM_HH__
#define __ARCH_ALPHA_TRU64_SYSTEM_HH__
#include "arch/alpha/system.hh"
#include "arch/isa_traits.hh"
#include "sim/system.hh"
#include "targetarch/isa_traits.hh"
class ExecContext;
@ -39,10 +40,11 @@ class BadAddrEvent;
class SkipFuncEvent;
class PrintfEvent;
class DebugPrintfEvent;
class DebugPrintfrEvent;
class DumpMbufEvent;
class AlphaArguments;
class Tru64System : public System
class Tru64AlphaSystem : public AlphaSystem
{
private:
#ifdef DEBUG
@ -59,11 +61,11 @@ class Tru64System : public System
DumpMbufEvent *dumpMbufEvent;
public:
Tru64System(Params *p);
~Tru64System();
Tru64AlphaSystem(Params *p);
~Tru64AlphaSystem();
static void Printf(AlphaArguments args);
static void DumpMbuf(AlphaArguments args);
};
#endif // __KERN_TRU64_TRU64_SYSTEM_HH__
#endif // __ARCH_ALPHA_TRU64_SYSTEM_HH__

30
arch/alpha/vtophys.cc
View file

@ -34,6 +34,7 @@
#include "mem/functional/physical.hh"
using namespace std;
using namespace AlphaISA;
AlphaISA::PageTableEntry
kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
@ -81,7 +82,7 @@ Addr
vtophys(ExecContext *xc, Addr addr)
{
AlphaISA::VAddr vaddr = addr;
Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
@ -94,7 +95,7 @@ vtophys(ExecContext *xc, Addr addr)
paddr = vaddr;
} else {
AlphaISA::PageTableEntry pte =
kernel_pte_lookup(xc->physmem, ptbr, vaddr);
kernel_pte_lookup(xc->getPhysMemPtr(), ptbr, vaddr);
if (pte.valid())
paddr = pte.paddr() | vaddr.offset();
}
@ -109,14 +110,14 @@ vtophys(ExecContext *xc, Addr addr)
uint8_t *
ptomem(ExecContext *xc, Addr paddr, size_t len)
{
return xc->physmem->dma_addr(paddr, len);
return xc->getPhysMemPtr()->dma_addr(paddr, len);
}
uint8_t *
vtomem(ExecContext *xc, Addr vaddr, size_t len)
{
Addr paddr = vtophys(xc, vaddr);
return xc->physmem->dma_addr(paddr, len);
return xc->getPhysMemPtr()->dma_addr(paddr, len);
}
void
@ -130,7 +131,7 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
paddr = vtophys(xc, src);
len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
(int)cplen);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len);
assert(dmaaddr);
memcpy(dst, dmaaddr, len);
@ -143,7 +144,8 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
while (cplen > AlphaISA::PageBytes) {
paddr = vtophys(xc, src);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr,
AlphaISA::PageBytes);
assert(dmaaddr);
memcpy(dst, dmaaddr, AlphaISA::PageBytes);
@ -154,7 +156,7 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
if (cplen > 0) {
paddr = vtophys(xc, src);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, cplen);
assert(dmaaddr);
memcpy(dst, dmaaddr, cplen);
@ -172,7 +174,7 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
paddr = vtophys(xc, dest);
len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
(int)cplen);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len);
assert(dmaaddr);
memcpy(dmaaddr, src, len);
@ -185,7 +187,8 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
while (cplen > AlphaISA::PageBytes) {
paddr = vtophys(xc, dest);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr,
AlphaISA::PageBytes);
assert(dmaaddr);
memcpy(dmaaddr, src, AlphaISA::PageBytes);
@ -196,7 +199,7 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
if (cplen > 0) {
paddr = vtophys(xc, dest);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, cplen);
assert(dmaaddr);
memcpy(dmaaddr, src, cplen);
@ -213,7 +216,7 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
paddr = vtophys(xc, vaddr);
len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
(int)maxlen);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len);
assert(dmaaddr);
char *term = (char *)memchr(dmaaddr, 0, len);
@ -231,7 +234,8 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
while (maxlen > AlphaISA::PageBytes) {
paddr = vtophys(xc, vaddr);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr,
AlphaISA::PageBytes);
assert(dmaaddr);
char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
@ -248,7 +252,7 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
if (maxlen > 0) {
paddr = vtophys(xc, vaddr);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, maxlen);
dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, maxlen);
assert(dmaaddr);
char *term = (char *)memchr(dmaaddr, 0, maxlen);

1126
arch/isa_parser.py
View file

File diff suppressed because it is too large Load diff

62
arch/isa_specific.hh Normal file
View file

@ -0,0 +1,62 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ISA_SPECIFIC_HH__
#define __ARCH_ISA_SPECIFIC_HH__
//This file provides a mechanism for other source code to bring in
//files from the ISA being compiled with
//These are constants so you can selective compile code based on the isa
//To use them, do something like
//
//#if THE_ISA == YOUR_FAVORITE_ISA
// conditional_code
//#endif
//
//Note that this is how this file sets up the other isa "hooks"
//These macros have numerical values because otherwise the preprocessor
//would treat them as 0 in comparisons.
#define ALPHA_ISA 21064
#define SPARC_ISA 42
#define MIPS_ISA 1337
//These tell the preprocessor where to find the files of a particular
//ISA, and set the "TheISA" macro for use elsewhere.
#if THE_ISA == ALPHA_ISA
#define TheISA AlphaISA
#elif THE_ISA == SPARC_ISA
#define TheISA SparcISA
#elif THE_ISA == MIPS_ISA
#define TheISA MipsISA
#else
#error "THE_ISA not set"
#endif
#endif

83
arch/mips/SConscript Normal file
View file

@ -0,0 +1,83 @@
# -*- mode:python -*-
# Copyright (c) 2004-2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import sys
from os.path import isdir
# Import build environment variable from SConstruct.
Import('env')
###################################################
#
# Define needed sources.
#
###################################################
# Base sources used by all configurations.
base_sources = Split('''
faults.cc
isa_traits.cc
''')
# Full-system sources
full_system_sources = Split('''
memory.cc
arguments.cc
mips34k.cc
osfpal.cc
stacktrace.cc
vtophys.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
common_syscall_emul.cc
linux_process.cc
tru64_process.cc
''')
# Set up complete list of sources based on configuration.
sources = base_sources
if env['FULL_SYSTEM']:
sources += full_system_sources
else:
sources += syscall_emulation_sources
# Convert file names to SCons File objects. This takes care of the
# path relative to the top of the directory tree.
sources = [File(s) for s in sources]
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
# Only non-header files need to be compiled.
isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
sources += isa_desc_sources
Return('sources')

80
arch/mips/faults.cc Normal file
View file

@ -0,0 +1,80 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/mips/faults.hh"
ResetFaultType * const ResetFault =
new ResetFaultType("reset", 1, 0x0001);
ArithmeticFaultType * const ArithmeticFault =
new ArithmeticFaultType("arith", 3, 0x0501);
InterruptFaultType * const InterruptFault =
new InterruptFaultType("interrupt", 4, 0x0101);
NDtbMissFaultType * const NDtbMissFault =
new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
PDtbMissFaultType * const PDtbMissFault =
new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
DtbPageFaultType * const DtbPageFault =
new DtbPageFaultType("dfault", 8, 0x0381);
DtbAcvFaultType * const DtbAcvFault =
new DtbAcvFaultType("dfault", 9, 0x0381);
ItbMissFaultType * const ItbMissFault =
new ItbMissFaultType("itbmiss", 10, 0x0181);
ItbPageFaultType * const ItbPageFault =
new ItbPageFaultType("itbmiss", 11, 0x0181);
ItbAcvFaultType * const ItbAcvFault =
new ItbAcvFaultType("iaccvio", 12, 0x0081);
UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault =
new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
FloatEnableFaultType * const FloatEnableFault =
new FloatEnableFaultType("fen", 14, 0x0581);
PalFaultType * const PalFault =
new PalFaultType("pal", 15, 0x2001);
IntegerOverflowFaultType * const IntegerOverflowFault =
new IntegerOverflowFaultType("intover", 16, 0x0501);
Fault ** ListOfFaults[] = {
(Fault **)&NoFault,
(Fault **)&ResetFault,
(Fault **)&MachineCheckFault,
(Fault **)&ArithmeticFault,
(Fault **)&InterruptFault,
(Fault **)&NDtbMissFault,
(Fault **)&PDtbMissFault,
(Fault **)&AlignmentFault,
(Fault **)&DtbPageFault,
(Fault **)&DtbAcvFault,
(Fault **)&ItbMissFault,
(Fault **)&ItbPageFault,
(Fault **)&ItbAcvFault,
(Fault **)&UnimplementedOpcodeFault,
(Fault **)&FloatEnableFault,
(Fault **)&PalFault,
(Fault **)&IntegerOverflowFault,
};
int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);

160
arch/mips/faults.hh Normal file
View file

@ -0,0 +1,160 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MIPS_FAULTS_HH__
#define __MIPS_FAULTS_HH__
#include "sim/faults.hh"
#include "arch/isa_traits.hh" //For the Addr type
class MipsFault : public FaultBase
{
public:
MipsFault(char * newName, int newId, Addr newVect)
: FaultBase(newName, newId), vect(newVect)
{;}
Addr vect;
};
extern class ResetFaultType : public MipsFault
{
public:
ResetFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const ResetFault;
extern class ArithmeticFaultType : public MipsFault
{
public:
ArithmeticFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const ArithmeticFault;
extern class InterruptFaultType : public MipsFault
{
public:
InterruptFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const InterruptFault;
extern class NDtbMissFaultType : public MipsFault
{
public:
NDtbMissFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const NDtbMissFault;
extern class PDtbMissFaultType : public MipsFault
{
public:
PDtbMissFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const PDtbMissFault;
extern class DtbPageFaultType : public MipsFault
{
public:
DtbPageFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const DtbPageFault;
extern class DtbAcvFaultType : public MipsFault
{
public:
DtbAcvFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const DtbAcvFault;
extern class ItbMissFaultType : public MipsFault
{
public:
ItbMissFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const ItbMissFault;
extern class ItbPageFaultType : public MipsFault
{
public:
ItbPageFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const ItbPageFault;
extern class ItbAcvFaultType : public MipsFault
{
public:
ItbAcvFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const ItbAcvFault;
extern class UnimplementedOpcodeFaultType : public MipsFault
{
public:
UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const UnimplementedOpcodeFault;
extern class FloatEnableFaultType : public MipsFault
{
public:
FloatEnableFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const FloatEnableFault;
extern class PalFaultType : public MipsFault
{
public:
PalFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const PalFault;
extern class IntegerOverflowFaultType : public MipsFault
{
public:
IntegerOverflowFaultType(char * newName, int newId, Addr newVect)
: MipsFault(newName, newId, newVect)
{;}
} * const IntegerOverflowFault;
extern Fault ** ListOfFaults[];
extern int NumFaults;
#endif // __FAULTS_HH__

96
arch/mips/isa/base.isa Normal file
View file

@ -0,0 +1,96 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Base class for MIPS instructions, and some support functions
//
//Outputs to decoder.hh
output header {{
#define R31 31
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
using namespace MipsISA;
/**
* Base class for all MIPS static instructions.
*/
class MipsStaticInst : public StaticInst
{
protected:
/// Make MipsISA register dependence tags directly visible in
/// this class and derived classes. Maybe these should really
/// live here and not in the MipsISA namespace.
/*enum DependenceTags {
FP_Base_DepTag = MipsISA::FP_Base_DepTag,
Fpcr_DepTag = MipsISA::Fpcr_DepTag,
Uniq_DepTag = MipsISA::Uniq_DepTag,
IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
};*/
// Constructor
MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
: StaticInst(mnem, _machInst, __opClass)
{
}
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void printReg(std::ostream &os, int reg) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
//Ouputs to decoder.cc
output decoder {{
void MipsStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
}
else {
ccprintf(os, "f%d", reg - FP_Base_DepTag);
}
}
std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if(_numSrcRegs > 0)
{
printReg(ss, _srcRegIdx[0]);
}
if(_numSrcRegs > 1)
{
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
// just print the first dest... if there's a second one,
// it's generally implicit
if(_numDestRegs > 0)
{
if(_numSrcRegs > 0)
ss << ",";
printReg(ss, _destRegIdx[0]);
}
return ss.str();
}
}};

67
arch/mips/isa/bitfields.isa Normal file
View file

@ -0,0 +1,67 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
def bitfield OPCODE <31:26>;
def bitfield OPCODE_HI <31:29>;
def bitfield OPCODE_LO <28:26>;
def bitfield REGIMM <20:16>;
def bitfield REGIMM_HI <20:19>;
def bitfield REGIMM_LO <18:16>;
def bitfield FUNCTION < 5: 0>;
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
// Integer operate format
def bitfield RT <20:16>;
def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
def bitfield RS <25:21>;
def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
def bitfield RD <15:11>;
def bitfield INTIMM <15: 0>; // integer immediate (literal)
// Floating-point operate format
def bitfield FMT <25:21>;
def bitfield FR <25:21>;
def bitfield FT <20:16>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
def bitfield CC <20:18>;
def bitfield ND <17:17>;
def bitfield TF <16:16>;
def bitfield MOVCI <16:16>;
def bitfield MOVCF <16:16>;
def bitfield SRL <21:21>;
def bitfield SRLV < 6: 6>;
def bitfield SA <10: 6>;
// CP0 Register Select
def bitfield SEL < 2: 0>;
// Interrupts
def bitfield SC < 5: 5>;
// Branch format
def bitfield OFFSET <15: 0>; // displacement
// Jmp format
def bitfield JMPTARG <25: 0>;
def bitfield HINT <10: 6>;
def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>;
// M5 instructions
def bitfield M5FUNC <7:0>;

930
arch/mips/isa/decoder.isa Normal file
View file

@ -0,0 +1,930 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// The actual MIPS32 ISA decoder
// -----------------------------
// The following instructions are specified in the MIPS32 ISA
// Specification. Decoding closely follows the style specified
// in the MIPS32 ISAthe specification document starting with Table
// A-2 (document available @ www.mips.com)
//
//@todo: Distinguish "unknown/future" use insts from "reserved"
// ones
decode OPCODE_HI default Unknown::unknown() {
// Derived From ... Table A-2 MIPS32 ISA Manual
0x0: decode OPCODE_LO {
0x0: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format BasicOp {
0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}});
1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}});
}
}
format BasicOp {
//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
0x0: decode RS {
0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
0x0: decode RD{
0x0: decode HINT {
0x0:nop({{}}); //really sll r0,r0,0
0x1:ssnop({{}});//really sll r0,r0,1
0x3:ehb({{}}); //really sll r0,r0,3
}
}
}
}
0x2: decode SRL {
0: srl({{ Rd = Rt.uw >> SA; }});
//Hardcoded assuming 32-bit ISA, probably need parameter here
1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
}
0x3: sra({{ Rd = Rt.sw >> SA; }});
0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
0x6: decode SRLV {
0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
//Hardcoded assuming 32-bit ISA, probably need parameter here
1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
}
0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
}
}
0x1: decode FUNCTION_LO {
//Table A-3 Note: "Specific encodings of the hint field are used
//to distinguish JR from JR.HB and JALR from JALR.HB"
format Jump {
0x0: decode HINT {
0:jr({{ NNPC = Rs & ~1; }},IsReturn);
1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
}
0x1: decode HINT {
0: jalr({{ NNPC = Rs; }},IsCall,IsReturn);
1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn);
}
}
format BasicOp {
0x2: movz({{ if (Rt == 0) Rd = Rs; }});
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
format WarnUnimpl {
0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
0x5: break();
0x7: sync();
}
}
0x2: decode FUNCTION_LO {
format BasicOp {
0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
}
}
0x3: decode FUNCTION_LO {
format IntOp {
0x0: mult({{
int64_t temp1 = Rs.sw * Rt.sw;
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: multu({{
int64_t temp1 = Rs.uw * Rt.uw;
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
0x2: div({{
xc->setMiscReg(Hi,Rs.sw % Rt.sw);
xc->setMiscReg(Lo,Rs.sw / Rt.sw);
}});
0x3: divu({{
xc->setMiscReg(Hi,Rs.uw % Rt.uw);
xc->setMiscReg(Lo,Rs.uw / Rt.uw);
}});
}
}
0x4: decode FUNCTION_LO {
format IntOp {
0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}});
0x4: and({{ Rd = Rs & Rt;}});
0x5: or({{ Rd = Rs | Rt;}});
0x6: xor({{ Rd = Rs ^ Rt;}});
0x7: nor({{ Rd = ~(Rs | Rt);}});
}
}
0x5: decode FUNCTION_LO {
format IntOp{
0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
}
}
0x6: decode FUNCTION_LO {
format Trap {
0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
}
}
}
0x1: decode REGIMM_HI {
0x0: decode REGIMM_LO {
format Branch {
0x0: bltz({{ cond = (Rs.sw < 0); }});
0x1: bgez({{ cond = (Rs.sw >= 0); }});
}
format BranchLikely {
//MIPS obsolete instructions
0x2: bltzl({{ cond = (Rs.sw < 0); }});
0x3: bgezl({{ cond = (Rs.sw >= 0); }});
}
}
0x1: decode REGIMM_LO {
format Trap {
0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
}
}
0x2: decode REGIMM_LO {
format Branch {
0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
}
format BranchLikely {
//Will be removed in future MIPS releases
0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
}
}
0x3: decode REGIMM_LO {
format WarnUnimpl {
0x7: synci();
}
}
}
format Jump {
0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
}
format Branch {
0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
0x6: blez({{ cond = (Rs.sw <= 0); }});
0x7: bgtz({{ cond = (Rs.sw > 0); }});
}
}
0x1: decode OPCODE_LO {
format IntOp {
0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }});
0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
0x7: lui({{ Rt = INTIMM << 16}});
}
}
0x2: decode OPCODE_LO {
//Table A-11 MIPS32 COP0 Encoding of rs Field
0x0: decode RS_MSB {
0x0: decode RS {
format System {
0x0: mfc0({{
//uint64_t reg_num = Rd.uw;
Rt = xc->readMiscReg(RD << 5 | SEL);
}});
0x4: mtc0({{
//uint64_t reg_num = Rd.uw;
xc->setMiscReg(RD << 5 | SEL,Rt);
}});
0x8: mftr({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
//sel field. In those instances, the sel field must be zero.
//MT Code Needed Here
}});
0xC: mttr({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
//sel field. In those instances, the sel field must be zero.
//MT Code Needed Here
}});
0xA: rdpgpr({{
//Accessing Previous Shadow Set Register Number
//uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
//uint64_t reg_num = Rt.uw;
//Rd = xc->regs.IntRegFile[prev];
//Rd = xc->shadowIntRegFile[prev][reg_num];
}});
0xB: decode RD {
0x0: decode SC {
0x0: dvpe({{
int idx;
int sel;
getMiscRegIdx(MVPControl,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
xc->setMiscReg(idx,sel);
}});
0x1: evpe({{
int idx;
int sel;
getMiscRegIdx(MVPControl,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
xc->setMiscReg(idx,sel,1);
}});
}
0x1: decode SC {
0x0: dmt({{
int idx;
int sel;
getMiscRegIdx(VPEControl,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
xc->setMiscReg(idx,sel);
}});
0x1: emt({{
int idx;
int sel;
getMiscRegIdx(VPEControl,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
xc->setMiscReg(idx,sel,1);
}});
}
0xC: decode SC {
0x0: di({{
int idx;
int sel;
getMiscRegIdx(Status,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
xc->setMiscReg(idx,sel);
}});
0x1: ei({{
int idx;
int sel;
getMiscRegIdx(Status,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
xc->setMiscReg(idx,sel,1);
}});
}
}
0xE: wrpgpr({{
//Accessing Previous Shadow Set Register Number
//uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
//uint64_t reg_num = Rd.uw;
//xc->regs.IntRegFile[prev];
//xc->shadowIntRegFile[prev][reg_num] = Rt;
}});
}
}
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
format System {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
0x08: tlbp({{ }});
}
format WarnUnimpl {
0x18: eret();
0x1F: deret();
0x20: wait();
}
}
}
//Table A-13 MIPS32 COP1 Encoding of rs Field
0x1: decode RS_MSB {
0x0: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }});
0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}});
0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}});
0x4: mtc1({{ /*Fs = Rt.uw*/}});
0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}});
0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}});
}
}
0x1: decode ND {
0x0: decode TF {
format Branch {
0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }});
0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }});
}
}
0x1: decode TF {
format BranchLikely {
0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }});
0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }});
}
}
}
}
0x1: decode RS_HI {
0x2: decode RS_LO {
//Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
//(( single-word ))
0x0: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
0x5: abss({{ Fd.sf = fabs(Fs.sf);}});
0x6: movs({{ Fd.sf = Fs.sf;}});
0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
}
}
0x1: decode RS_LO {
//only legal for 64 bit-FP
format Float64Op {
0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
}
format FloatOp {
0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
}
}
format BasicOp {
0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
0x3: movns({{ if (Rt != 0) Fd = Fs; }});
}
format Float64Op {
0x5: recips({{ Fd = 1 / Fs; }});
0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}});
}
}
0x4: decode RS_LO {
format FloatOp {
0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
}});
0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
}
}
}
//Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
0x1: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
0x5: absd({{ Fd.df = fabs(Fs.df);}});
0x6: movd({{ Fd.df = Fs.df;}});
0x7: negd({{ Fd.df = -1 * Fs.df;}});
}
}
0x1: decode RS_LO {
//only legal for 64 bit
format Float64Op {
0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
}
format FloatOp {
0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }});
0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }});
}
}
format BasicOp {
0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }});
0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }});
}
format Float64Op {
0x5: recipd({{ Fd.df = 1 / Fs.df}});
0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
}
}
0x4: decode RS_LO {
format FloatOp {
0x0: cvt_s_d({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
}});
0x4: cvt_w_d({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
}});
}
//only legal for 64 bit
format Float64Op {
0x5: cvt_l_d({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
}});
}
}
}
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
0x4: decode FUNCTION {
format FloatOp {
0x20: cvt_s({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
0x21: cvt_d({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
}
}
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
//Note: "1. Format type L is legal only if 64-bit floating point operations
//are enabled."
0x5: decode FUNCTION_HI {
format FloatOp {
0x10: cvt_s_l({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
}});
0x11: cvt_d_l({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
}});
}
}
//Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
//Note: "1. Format type PS is legal only if 64-bit floating point operations
//are enabled. "
0x6: decode RS_HI {
0x0: decode RS_LO {
format Float64Op {
0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = Fs.df + Ft.df;
}});
0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = Fs.df - Ft.df;
}});
0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = Fs.df * Ft.df;
}});
0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = fabs(Fs.df);
}});
0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
//Fd.df = Fs<31:0> | Ft<31:0>;
}});
0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = -1 * Fs.df;
}});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format Float64Op {
0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}});
0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
}
}
format BasicOp {
0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }});
}
}
0x4: decode RS_LO {
0x0: Float64Op::cvt_s_pu({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
}});
}
0x5: decode RS_LO {
format Float64Op {
0x0: cvt_s_pl({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
}});
0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}});
0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}});
0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}});
0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}});
}
}
}
}
}
}
//Table A-19 MIPS32 COP2 Encoding of rs Field
0x2: decode RS_MSB {
0x0: decode RS_HI {
0x0: decode RS_LO {
format WarnUnimpl {
0x0: mfc2();
0x2: cfc2();
0x3: mfhc2();
0x4: mtc2();
0x6: ctc2();
0x7: mftc2();
}
}
0x1: decode ND {
0x0: decode TF {
format WarnUnimpl {
0x0: bc2f();
0x1: bc2t();
}
}
0x1: decode TF {
format WarnUnimpl {
0x0: bc2fl();
0x1: bc2tl();
}
}
}
}
}
//Table A-20 MIPS64 COP1X Encoding of Function Field 1
//Note: "COP1X instructions are legal only if 64-bit floating point
//operations are enabled."
0x3: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format LoadMemory2 {
0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}});
0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }});
0x5: luxc1({{ //Need to make EA<2:0> = 0
EA = Rs + Rt;
}},
{{ /*F_t<31:0> = Mem.df; */}});
}
}
0x1: decode FUNCTION_LO {
format StoreMemory2 {
0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}});
0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}});
0x5: suxc1({{ //Need to make EA<2:0> = 0
EA = Rs + Rt;
}},
{{ /*Mem.df = F_t<63:0>;*/}});
}
0x7: WarnUnimpl::prefx();
}
format FloatOp {
0x3: WarnUnimpl::alnv_ps();
format BasicOp {
0x4: decode FUNCTION_LO {
0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
0x6: madd_ps({{
//Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = (Fs.df * Fs.df) + Fr.df;
}});
}
0x5: decode FUNCTION_LO {
0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
0x6: msub_ps({{
//Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = (Fs.df * Fs.df) - Fr.df;
}});
}
0x6: decode FUNCTION_LO {
0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
0x6: nmadd_ps({{
//Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
}});
}
0x7: decode FUNCTION_LO {
0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
0x6: nmsub_ps({{
//Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
}});
}
}
}
}
//MIPS obsolete instructions
format BranchLikely {
0x4: beql({{ cond = (Rs.sw == 0); }});
0x5: bnel({{ cond = (Rs.sw != 0); }});
0x6: blezl({{ cond = (Rs.sw <= 0); }});
0x7: bgtzl({{ cond = (Rs.sw > 0); }});
}
}
0x3: decode OPCODE_LO default FailUnimpl::reserved() {
//Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
0x4: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: maddu({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
0x5: msubu({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
}
}
0x4: decode FUNCTION_LO {
format BasicOp {
0x0: clz({{
/*int cnt = 0;
int idx = 0;
while ( Rs.uw<idx> != 1) {
cnt++;
idx--;
}
Rd.uw = cnt;*/
}});
0x1: clo({{
/*int cnt = 0;
int idx = 0;
while ( Rs.uw<idx> != 0) {
cnt++;
idx--;
}
Rd.uw = cnt;*/
}});
}
}
0x7: decode FUNCTION_LO {
0x7: WarnUnimpl::sdbbp();
}
}
//Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
0x7: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format WarnUnimpl {
0x1: ext();
0x4: ins();
}
}
0x1: decode FUNCTION_LO {
format WarnUnimpl {
0x0: fork();
0x1: yield();
}
}
//Table A-10 MIPS32 BSHFL Encoding of sa Field
0x4: decode SA {
0x02: WarnUnimpl::wsbh();
format BasicOp {
0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
}
}
0x6: decode FUNCTION_LO {
0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }});
}
}
}
0x4: decode OPCODE_LO default FailUnimpl::reserved() {
format LoadMemory {
0x0: lb({{ Rt.sw = Mem.sb; }});
0x1: lh({{ Rt.sw = Mem.sh; }});
0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign);
0x3: lw({{ Rt.sw = Mem.sb; }});
0x4: lbu({{ Rt.uw = Mem.ub; }});
0x5: lhu({{ Rt.uw = Mem.uh; }});
0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign);
}
0x7: FailUnimpl::reserved();
}
0x5: decode OPCODE_LO default FailUnimpl::reserved() {
format StoreMemory {
0x0: sb({{ Mem.ub = Rt<7:0>; }});
0x1: sh({{ Mem.uh = Rt<15:0>; }});
0x2: swl({{ Mem.ub = Rt<31:0>; }});//,WordAlign);
0x3: sw({{ Mem.ub = Rt<31:0>; }});
0x6: swr({{ Mem.ub = Rt<31:0>; }});//,WordAlign);
}
format WarnUnimpl {
0x7: cache();
}
}
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
0x0: WarnUnimpl::ll();
format LoadMemory {
0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}});
}
}
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
0x0: WarnUnimpl::sc();
format StoreMemory {
0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
0x5: sdc1({{ //Mem.df = Ft<63:0>; }});
}
}
}

35
arch/mips/isa/formats.isa Normal file
View file

@ -0,0 +1,35 @@
// -*- mode:c++ -*-
//Templates from this format are used later
//Include the basic format
##include "m5/arch/mips/isa/formats/basic.isa"
//Include the basic format
##include "m5/arch/mips/isa/formats/noop.isa"
//Include utility formats/functions
##include "m5/arch/mips/isa/formats/util.isa"
//Include the cop0 formats
##include "m5/arch/mips/isa/formats/cop0.isa"
//Include the integer formats
##include "m5/arch/mips/isa/formats/int.isa"
//Include the floatOp format
##include "m5/arch/mips/isa/formats/fp.isa"
//Include the mem format
##include "m5/arch/mips/isa/formats/mem.isa"
//Include the trap format
##include "m5/arch/mips/isa/formats/trap.isa"
//Include the branch format
##include "m5/arch/mips/isa/formats/branch.isa"
//Include the noop format
##include "m5/arch/mips/isa/formats/unimp.isa"
//Include the noop format
##include "m5/arch/mips/isa/formats/unknown.isa"

66
arch/mips/isa/formats/basic.isa Normal file
View file

@ -0,0 +1,66 @@
// -*- mode:c++ -*-
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
def template BasicDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
%(BasicExecDeclare)s
};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
}
}};
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
// Basic decode template.
def template BasicDecode {{
return new %(class_name)s(machInst);
}};
// Basic decode template, passing mnemonic in as string arg to constructor.
def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
// The most basic instruction format... used only for a few misc. insts
def format BasicOp(code, *flags) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

322
arch/mips/isa/formats/branch.isa Normal file
View file

@ -0,0 +1,322 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Control transfer instructions
//
output header {{
#include <iostream>
using namespace std;
/**
* Base class for instructions whose disassembly is not purely a
* function of the machine instruction (i.e., it depends on the
* PC). This class overrides the disassemble() method to check
* the PC and symbol table values before re-using a cached
* disassembly string. This is necessary for branches and jumps,
* where the disassembly string includes the target address (which
* may depend on the PC and/or symbol table).
*/
class PCDependentDisassembly : public MipsStaticInst
{
protected:
/// Cached program counter from last disassembly
mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly
mutable const SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, MachInst _machInst,
OpClass __opClass)
: MipsStaticInst(mnem, _machInst, __opClass),
cachedPC(0), cachedSymtab(0)
{
}
const std::string &
disassemble(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for branches (PC-relative control transfers),
* conditional or unconditional.
*/
class Branch : public PCDependentDisassembly
{
protected:
/// target address (signed) Displacement .
int32_t disp;
/// Constructor.
Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(OFFSET << 2)
{
//If Bit 17 is 1 then Sign Extend
if ( (disp & 0x00020000) > 0 ) {
disp |= 0xFFFE0000;
}
}
Addr branchTarget(Addr branchPC) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for branch likely branches (PC-relative control transfers),
*/
class BranchLikely : public PCDependentDisassembly
{
protected:
/// target address (signed) Displacement .
int32_t disp;
/// Constructor.
BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(OFFSET << 2)
{
}
Addr branchTarget(Addr branchPC) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for jumps (register-indirect control transfers). In
* the Mips ISA, these are always unconditional.
*/
class Jump : public PCDependentDisassembly
{
protected:
/// Displacement to target address (signed).
int32_t disp;
uint32_t target;
public:
/// Constructor
Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(JMPTARG << 2)
{
}
Addr branchTarget(ExecContext *xc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
Addr
Branch::branchTarget(Addr branchPC) const
{
return branchPC + 4 + disp;
}
Addr
BranchLikely::branchTarget(Addr branchPC) const
{
return branchPC + 4 + disp;
}
Addr
Jump::branchTarget(ExecContext *xc) const
{
Addr NPC = xc->readPC() + 4;
uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}
const std::string &
PCDependentDisassembly::disassemble(Addr pc,
const SymbolTable *symtab) const
{
if (!cachedDisassembly ||
pc != cachedPC || symtab != cachedSymtab)
{
if (cachedDisassembly)
delete cachedDisassembly;
cachedDisassembly =
new std::string(generateDisassembly(pc, symtab));
cachedPC = pc;
cachedSymtab = symtab;
}
return *cachedDisassembly;
}
std::string
Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// There's only one register arg (RA), but it could be
// either a source (the condition for conditional
// branches) or a destination (the link reg for
// unconditional branches)
if (_numSrcRegs == 1) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
} else if(_numSrcRegs == 2) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
printReg(ss, _srcRegIdx[1]);
ss << ",";
}
Addr target = pc + 8 + disp;
std::string str;
if (symtab && symtab->findSymbol(target, str))
ss << str;
else
ccprintf(ss, "0x%x", target);
return ss.str();
}
std::string
BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// There's only one register arg (RA), but it could be
// either a source (the condition for conditional
// branches) or a destination (the link reg for
// unconditional branches)
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
}
else if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
ss << ",";
}
Addr target = pc + 4 + disp;
std::string str;
if (symtab && symtab->findSymbol(target, str))
ss << str;
else
ccprintf(ss, "0x%x", target);
return ss.str();
}
std::string
Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
if ( mnemonic == "jal" ) {
Addr npc = pc + 4;
ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
} else if (_numSrcRegs == 0) {
std::string str;
if (symtab && symtab->findSymbol(disp, str))
ss << str;
else
ccprintf(ss, "0x%x", disp);
} else if (_numSrcRegs == 1) {
printReg(ss, _srcRegIdx[0]);
} else if(_numSrcRegs == 2) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
printReg(ss, _srcRegIdx[1]);
} else {
panic(">= 3 Source Registers!!!");
}
return ss.str();
}
}};
def format Branch(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if name[strlen-2:] == 'al':
code += 'r31 = NNPC;\n'
#Condition code
code = 'bool cond;\n' + code
code += 'if (cond) {\n'
code += ' NNPC = NPC + disp;\n'
code += '} else {\n'
code += ' NNPC = NNPC;\n'
code += '} \n'
code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;'
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl'))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def format BranchLikely(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if name[strlen-3:] == 'all':
code += 'r31 = NNPC;\n'
#Condition code
code = 'bool cond;\n' + code
code += 'if (cond) {'
code += 'NNPC = NPC + disp;\n'
code += '} \n'
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def format Jump(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if strlen > 1 and name[1:] == 'al':
code = 'r31 = NNPC;\n' + code
#code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}'
#code += 'target = NNPC;'
iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
('IsIndirectControl', 'IsUncondControl'))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

49
arch/mips/isa/formats/fp.isa Normal file
View file

@ -0,0 +1,49 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
//
output header {{
/**
* Base class for FP operations.
*/
class FPOp : public MipsStaticInst
{
protected:
/// Constructor
FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
// Primary format for integer operate instructions:
def format FloatOp(code, *flags) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
// Primary format for integer operate instructions:
def format Float64Op(code, *flags) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

130
arch/mips/isa/formats/int.isa Normal file
View file

@ -0,0 +1,130 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//
//Outputs to decoder.hh
output header {{
#include <iostream>
using namespace std;
/**
* Base class for integer operations.
*/
class IntOp : public MipsStaticInst
{
protected:
/// Constructor
IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class IntImmOp : public MipsStaticInst
{
protected:
int32_t imm;
/// Constructor
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
{
//If Bit 15 is 1 then Sign Extend
int32_t temp = imm & 0x00008000;
if (temp > 0 && mnemonic != "lui") {
imm |= 0xFFFF0000;
}
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
//Outputs to decoder.cc
output decoder {{
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// just print the first dest... if there's a second one,
// it's generally implicit
if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
}
ss << ",";
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
}
if (_numSrcRegs > 1) {
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
return ss.str();
}
std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
}
ss << ",";
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
}
if( mnemonic == "lui")
ccprintf(ss, "%08p ", imm);
else
ss << (int) imm;
return ss.str();
}
}};
//Used by decoder.isa
def format IntOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
# Figure out if we are creating a IntImmOp or a IntOp
# by looking at the instruction name
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
strlen = len(name)
if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = OperateNopCheckDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

469
arch/mips/isa/formats/mem.isa Normal file
View file

@ -0,0 +1,469 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Base class for general Mips memory-format instructions.
*/
class Memory : public MipsStaticInst
{
protected:
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
/// Pointer to EAComp object.
const StaticInstPtr eaCompPtr;
/// Pointer to MemAcc object.
const StaticInstPtr memAccPtr;
/// Displacement for EA calculation (signed).
int32_t disp;
/// Constructor
Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: MipsStaticInst(mnem, _machInst, __opClass),
memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
disp(OFFSET)
{
//If Bit 15 is 1 then Sign Extend
int32_t temp = disp & 0x00008000;
if (temp > 0) {
disp |= 0xFFFF0000;
}
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
public:
const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
const StaticInstPtr &memAccInst() const { return memAccPtr; }
};
}};
output decoder {{
std::string
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
}
}};
def format LoadAddress(code) {{
iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def template LoadStoreDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
protected:
/**
* "Fake" effective address computation class for "%(mnemonic)s".
*/
class EAComp : public %(base_class)s
{
public:
/// Constructor
EAComp(MachInst machInst);
%(BasicExecDeclare)s
};
/**
* "Fake" memory access instruction class for "%(mnemonic)s".
*/
class MemAcc : public %(base_class)s
{
public:
/// Constructor
MemAcc(MachInst machInst);
%(BasicExecDeclare)s
};
public:
/// Constructor.
%(class_name)s(MachInst machInst);
%(BasicExecDeclare)s
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
};
}};
def template InitiateAccDeclare {{
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template LoadStoreConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
inline %(class_name)s::EAComp::EAComp(MachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(ea_constructor)s;
}
inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(memacc_constructor)s;
}
inline %(class_name)s::%(class_name)s(MachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
{
%(constructor)s;
}
}};
def template EACompExecute {{
Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
xc->setEA(EA);
}
return fault;
}
}};
def template LoadMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
}
return fault;
}
}};
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
%(op_dest_decl)s;
memcpy(&Mem, data, sizeof(Mem));
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == NoFault) {
%(code)s;
}
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_src_decl)s;
%(op_dest_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
return fault;
}
}};
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_dest_decl)s;
memcpy(&write_result, data, sizeof(write_result));
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
// load instructions use Rt as dest, so check for
// Rt == 31 to detect nops
def template LoadNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
if (RT == 0) {
i = makeNop(i);
}
return i;
}
}};
def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = LoadNopCheckDecode,
exec_template_base = 'Load')
}};
def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
exec_template_base = 'Store')
}};
//FP loads are offloaded to these formats for now ...
def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = LoadNopCheckDecode,
exec_template_base = 'Load')
}};
//FP stores are offloaded to these formats for now ...
def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = LoadNopCheckDecode,
exec_template_base = 'Store')
}};

90
arch/mips/isa/formats/noop.isa Normal file
View file

@ -0,0 +1,90 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Nop
//
output header {{
/**
* Static instruction class for no-ops. This is a leaf class.
*/
class Nop : public MipsStaticInst
{
/// Disassembly of original instruction.
const std::string originalDisassembly;
public:
/// Constructor
Nop(const std::string _originalDisassembly, MachInst _machInst)
: MipsStaticInst("nop", _machInst, No_OpClass),
originalDisassembly(_originalDisassembly)
{
flags[IsNop] = true;
}
~Nop() { }
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
%(BasicExecDeclare)s
};
}};
output decoder {{
std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return originalDisassembly;
#else
return csprintf("%-10s (%s)", "nop", originalDisassembly);
#endif
}
/// Helper function for decoding nops. Substitute Nop object
/// for original inst passed in as arg (and delete latter).
inline
MipsStaticInst *
makeNop(MipsStaticInst *inst)
{
MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
delete inst;
return nop;
}
}};
output exec {{
Fault
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
return NoFault;
}
}};
// integer & FP operate instructions use RT as dest, so check for
// RT == 0 to detect nops
def template OperateNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
//if (RD == 0) {
// i = makeNop(i);
//}
return i;
}
}};
// Like BasicOperate format, but generates NOP if RC/FC == 31
def format BasicOperateWithNopCheck(code, *opt_args) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code),
opt_args)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = OperateNopCheckDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

53
arch/mips/isa/formats/tlbop.isa Normal file
View file

@ -0,0 +1,53 @@
////////////////////////////////////////////////////////////////////
//
// TlbOp instructions
//
output header {{
/**
* Base class for integer operations.
*/
class TlbOp : public MipsStaticInst
{
protected:
/// Constructor
TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
def template TlbOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//Call into the trap handler with the appropriate fault
return No_Fault;
}
//Write the resulting state to the execution context
%(op_wb)s;
return No_Fault;
}
}};
// Primary format for integer operate instructions:
def format TlbOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = TlbOpExecute.subst(iop)
}};

52
arch/mips/isa/formats/trap.isa Normal file
View file

@ -0,0 +1,52 @@
////////////////////////////////////////////////////////////////////
//
// Trap instructions
//
output header {{
/**
* Base class for integer operations.
*/
class Trap : public MipsStaticInst
{
protected:
/// Constructor
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
def template TrapExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//Call into the trap handler with the appropriate fault
return No_Fault;
}
//Write the resulting state to the execution context
%(op_wb)s;
return No_Fault;
}
}};
// Primary format for integer operate instructions:
def format Trap(code, *flags) {{
code = 'bool cond;\n' + code;
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

165
arch/mips/isa/formats/unimp.isa Normal file
View file

@ -0,0 +1,165 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Static instruction class for unimplemented instructions that
* cause simulator termination. Note that these are recognized
* (legal) instructions that the simulator does not support; the
* 'Unknown' class is used for unrecognized/illegal instructions.
* This is a leaf class.
*/
class FailUnimplemented : public MipsStaticInst
{
public:
/// Constructor
FailUnimplemented(const char *_mnemonic, MachInst _machInst)
: MipsStaticInst(_mnemonic, _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for unimplemented instructions that cause a warning
* to be printed (but do not terminate simulation). This
* implementation is a little screwy in that it will print a
* warning for each instance of a particular unimplemented machine
* instruction, not just for each unimplemented opcode. Should
* probably make the 'warned' flag a static member of the derived
* class.
*/
class WarnUnimplemented : public MipsStaticInst
{
private:
/// Have we warned on this instruction yet?
mutable bool warned;
public:
/// Constructor
WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
: MipsStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
FailUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%-10s", mnemonic);
#else
return csprintf("%-10s (unimplemented)", mnemonic);
#endif
}
}};
output exec {{
Fault
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
return UnimplementedOpcodeFault;
}
Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);
warned = true;
}
return NoFault;
}
}};
def format FailUnimpl() {{
iop = InstObjParams(name, 'FailUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
output header {{
/**
* Static instruction class for unknown (illegal) instructions.
* These cause simulator termination if they are executed in a
* non-speculative mode. This is a leaf class.
*/
class Unknown : public MipsStaticInst
{
public:
/// Constructor
Unknown(MachInst _machInst)
: MipsStaticInst("unknown", _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};

52
arch/mips/isa/formats/unknown.isa Normal file
View file

@ -0,0 +1,52 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output decoder {{
std::string
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
"unknown", machInst, OPCODE);
}
}};
output exec {{
Fault
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
return UnimplementedOpcodeFault;
}
}};
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

148
arch/mips/isa/formats/util.isa Normal file
View file

@ -0,0 +1,148 @@
// -*- mode:c++ -*-
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
postacc_code = '', base_class = 'Memory',
decode_template = BasicDecode, exec_template_base = ''):
# Make sure flags are in lists (convert to lists if not).
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
# add hook to get effective addresses into execution trace output.
ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
# generate code block objects
ea_cblk = CodeBlock(ea_code)
memacc_cblk = CodeBlock(memacc_code)
postacc_cblk = CodeBlock(postacc_code)
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
# to generate three StaticInst objects. Note that the latter two
# are nested inside the larger "atomic" one.
# generate InstObjParams for EAComp object
ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
# generate InstObjParams for MemAcc object
memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
# in the split execution model, the MemAcc portion is responsible
# for the post-access code.
memacc_iop.postacc_code = postacc_cblk.code
# generate InstObjParams for InitiateAcc, CompleteAcc object
# The code used depends on the template being used
if (exec_template_base == 'Load'):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(memacc_code + postacc_code)
elif (exec_template_base == 'Store'):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(postacc_code)
else:
initiateacc_cblk = ''
completeacc_cblk = ''
initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
inst_flags)
completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
inst_flags)
if (exec_template_base == 'Load'):
initiateacc_iop.ea_code = ea_cblk.code
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
elif (exec_template_base == 'Store'):
initiateacc_iop.ea_code = ea_cblk.code
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
# generate InstObjParams for unified execution
cblk = CodeBlock(ea_code + memacc_code + postacc_code)
iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
iop.ea_constructor = ea_cblk.constructor
iop.ea_code = ea_cblk.code
iop.memacc_constructor = memacc_cblk.constructor
iop.memacc_code = memacc_cblk.code
iop.postacc_code = postacc_cblk.code
if mem_flags:
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s
memacc_iop.constructor += s
# select templates
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
EACompExecute.subst(ea_iop)
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(initiateacc_iop)
+ completeAccTemplate.subst(completeacc_iop))
}};
output exec {{
using namespace MipsISA;
/// CLEAR ALL CPU INST/EXE HAZARDS
inline void
clear_exe_inst_hazards()
{
//CODE HERE
}
/// Check "FP enabled" machine status bit. Called when executing any FP
/// instruction in full-system mode.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
fault = FloatEnableFault;
}
return fault;
}
#else
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
return NoFault;
}
#endif
double convert_and_round(float w, int x, int y, int z)
{
double temp = .34000;
return temp;
}
enum FPTypes{
FP_SINGLE,
FP_DOUBLE,
FP_LONG,
FP_PS_LO,
FP_PS_HI,
FP_WORD,
RND_NEAREST,
RND_ZERO,
RND_UP,
RND_DOWN
};
}};

39
arch/mips/isa/includes.isa Normal file
View file

@ -0,0 +1,39 @@
////////////////////////////////////////////////////////////////////
//
// Output include file directives.
//
output header {{
#include <sstream>
#include <iostream>
#include <iomanip>
#include "cpu/static_inst.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
}};
output decoder {{
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif
}};
output exec {{
#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif
#ifdef FULL_SYSTEM
//#include "arch/alpha/pseudo_inst.hh"
#endif
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
}};

52
arch/mips/isa/main.isa Normal file
View file

@ -0,0 +1,52 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
##include "m5/arch/mips/isa/includes.isa"
////////////////////////////////////////////////////////////////////
//
// Namespace statement. Everything below this line will be in the
// MipsISAInst namespace.
//
namespace MipsISA;
//Include the bitfield definitions
##include "m5/arch/mips/isa/bitfields.isa"
//Include the operand_types and operand definitions
##include "m5/arch/mips/isa/operands.isa"
//Include the base class for mips instructions, and some support code
##include "m5/arch/mips/isa/base.isa"
//Include the definitions for the instruction formats
##include "m5/arch/mips/isa/formats.isa"
//Include the decoder definition
##include "m5/arch/mips/isa/decoder.isa"

33
arch/mips/isa/operands.isa Normal file
View file

@ -0,0 +1,33 @@
def operand_types {{
'sb' : ('signed int', 8),
'ub' : ('unsigned int', 8),
'sh' : ('signed int', 16),
'uh' : ('unsigned int', 16),
'sw' : ('signed int', 32),
'uw' : ('unsigned int', 32),
'sd' : ('signed int', 64),
'ud' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64),
'qf' : ('float', 128)
}};
def operands {{
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
'r31': ('IntReg', 'uw','R31','IsInteger', 4),
'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
}};

403
arch/mips/isa_traits.cc Normal file
View file

@ -0,0 +1,403 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/mips/isa_traits.hh"
#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "sim/serialize.hh"
using namespace MipsISA;
//Function now Obsolete in current state.
//If anyting this should return the correct miscreg index
//but that is handled implicitly with enums anyway
void
MipsISA::getMiscRegIdx(int reg_name,int &idx, int &sel)
{
switch(reg_name)
{
case Index: idx = 0; sel = 0; break; //0-0 Index into the TLB array
case MVPControl: idx = 0; sel = 1; break; //0-1 Per-processor register containing global
case MVPConf0: idx = 0; sel = 2; break; //0-2 Per-processor register containing global
case MVPConf1: idx = 0; sel = 3; break; //0-3 Per-processor register containing global
case Random: idx = 1; sel = 3; break; //1-0 Randomly generated index into the TLB array
case VPEControl: idx = 1; sel = 1; break; //1-1 Per-VPE register containing relatively volatile
//thread configuration data
case VPEConf0: idx = 1; sel = 2; break; //1-2 Per-VPE multi-thread configuration
//information
case VPEConf1: idx = 1; sel = 3; break; //1-3 Per-VPE multi-thread configuration
//information
case YQMask: idx = 1; sel = 4; break; //Per-VPE register defining which YIELD
//qualifier bits may be used without generating
//an exception
case VPESchedule: idx = 1; sel = 5; break;
case VPEScheFBack: idx = 1; sel = 6; break;
case VPEOpt: idx = 1; sel = 7; break;
case EntryLo0: idx = 1; sel = 5; break;
case TCStatus: idx = 1; sel = 5; break;
case TCBind: idx = 1; sel = 5; break;
case TCRestart: idx = 1; sel = 5; break;
case TCHalt: idx = 1; sel = 5; break;
case TCContext: idx = 1; sel = 5; break;
case TCSchedule: idx = 1; sel = 5; break;
case TCScheFBack: panic("Accessing Unimplemented CP0 Register"); break;
case EntryLo1: panic("Accessing Unimplemented CP0 Register"); break;
case Context: panic("Accessing Unimplemented CP0 Register"); break;
case ContextConfig: panic("Accessing Unimplemented CP0 Register"); break;
//case PageMask: panic("Accessing Unimplemented CP0 Register"); break;
case PageGrain: panic("Accessing Unimplemented CP0 Register"); break;
case Wired: panic("Accessing Unimplemented CP0 Register"); break;
case SRSConf0: panic("Accessing Unimplemented CP0 Register"); break;
case SRSConf1: panic("Accessing Unimplemented CP0 Register"); break;
case SRSConf2: panic("Accessing Unimplemented CP0 Register"); break;
case SRSConf3: panic("Accessing Unimplemented CP0 Register"); break;
case SRSConf4: panic("Accessing Unimplemented CP0 Register"); break;
case BadVAddr: panic("Accessing Unimplemented CP0 Register"); break;
case Count: panic("Accessing Unimplemented CP0 Register"); break;
case EntryHi: panic("Accessing Unimplemented CP0 Register"); break;
case Compare: panic("Accessing Unimplemented CP0 Register"); break;
case Status: idx = 12; sel = 0; break; //12-0 Processor status and control
case IntCtl: idx = 12; sel = 1; break; //12-1 Interrupt system status and control
case SRSCtl: idx = 12; sel = 2; break; //12-2 Shadow register set status and control
case SRSMap: idx = 12; sel = 3; break; //12-3 Shadow set IPL mapping
case Cause: idx = 13; sel = 0; break; //13-0 Cause of last general exception
case EPC: idx = 14; sel = 0; break; //14-0 Program counter at last exception
case PrId: idx = 15; sel = 0; break; //15-0 Processor identification and revision
case EBase: idx = 15; sel = 1; break; //15-1 Exception vector base register
case Config: panic("Accessing Unimplemented CP0 Register"); break;
case Config1: panic("Accessing Unimplemented CP0 Register"); break;
case Config2: panic("Accessing Unimplemented CP0 Register"); break;
case Config3: panic("Accessing Unimplemented CP0 Register"); break;
case LLAddr: panic("Accessing Unimplemented CP0 Register"); break;
case WatchLo: panic("Accessing Unimplemented CP0 Register"); break;
case WatchHi: panic("Accessing Unimplemented CP0 Register"); break;
case Debug: panic("Accessing Unimplemented CP0 Register"); break;
case TraceControl1: panic("Accessing Unimplemented CP0 Register"); break;
case TraceControl2: panic("Accessing Unimplemented CP0 Register"); break;
case UserTraceData: panic("Accessing Unimplemented CP0 Register"); break;
case TraceBPC: panic("Accessing Unimplemented CP0 Register"); break;
case DEPC: panic("Accessing Unimplemented CP0 Register"); break;
case PerfCnt: panic("Accessing Unimplemented CP0 Register"); break;
case ErrCtl: panic("Accessing Unimplemented CP0 Register"); break;
case CacheErr0: panic("Accessing Unimplemented CP0 Register"); break;
case CacheErr1: panic("Accessing Unimplemented CP0 Register"); break;
case CacheErr2: panic("Accessing Unimplemented CP0 Register"); break;
case CacheErr3: panic("Accessing Unimplemented CP0 Register"); break;
case TagLo: panic("Accessing Unimplemented CP0 Register"); break;
case DataLo: panic("Accessing Unimplemented CP0 Register"); break;
case TagHi: panic("Accessing Unimplemented CP0 Register"); break;
case DataHi: panic("Accessing Unimplemented CP0 Register"); break;
case ErrorEPC: panic("Accessing Unimplemented CP0 Register"); break;
default:
panic("Accessing Unimplemented Misc. Register");
}
}
void RegFile::coldReset()
{
//CP0 Random Reg:
//Randomly generated index into the TLB array
miscRegs[Random] = 0x0000003f;
//CP0 Wired Reg.
miscRegs[Wired] = 0x0000000;
//CP0 HWRENA
miscRegs[HWRena] = 0x0000000;
//CP0 Status Reg.
miscRegs[Status] = 0x0400004;
//CP0 INTCNTL
miscRegs[IntCtl] = 0xfc00000;
//CP0 SRSCNTL
miscRegs[SRSCtl] = 0x0c00000;
//CP0 SRSMAP
miscRegs[SRSMap] = 0x0000000;
//CP0 Cause
miscRegs[Cause] = 0x0000000;
//CP0 Processor ID
miscRegs[PrId] = 0x0019300;
//CP0 EBASE
miscRegs[EBase] = 0x8000000;
//CP0 Config Reg.
miscRegs[Config] = 0x80040482;
//CP0 Config 1 Reg.
miscRegs[Config1] = 0xfee3719e;
//CP0 Config 2 Reg.
miscRegs[Config2] = 0x8000000;
//CP0 Config 3 Reg.
miscRegs[Config3] = 0x0000020;
//CP0 Config 7 Reg.
miscRegs[Config7] = 0x0000000;
//CP0 Debug
miscRegs[Debug] = 0x0201800;
//CP0 PERFCNTL1
miscRegs[PerfCnt0] = 0x0000000;
//CP0 PERFCNTL2
miscRegs[PerfCnt1] = 0x0000000;
}
void RegFile::createCP0Regs()
{
//Resize Coprocessor Register Banks to
// the number specified in MIPS32K VOL.III
// Chapter 8
/*
//Cop-0 Regs. Bank 0: Index,
miscRegs[0].resize(4);
//Cop-0 Regs. Bank 1:
miscRegs[1].resize(8);
//Cop-0 Regs. Bank 2:
miscRegs[2].resize(8);
//Cop-0 Regs. Bank 3:
miscRegs[3].resize(1);
//Cop-0 Regs. Bank 4:
miscRegs[4].resize(2);
//Cop-0 Regs. Bank 5:
miscRegs[5].resize(2);
//Cop-0 Regs. Bank 6:
miscRegs[6].resize(6);
//Cop-0 Regs. Bank 7:
miscRegs[7].resize(1);
//Cop-0 Regs. Bank 8:
miscRegs[8].resize(1);
//Cop-0 Regs. Bank 9:
miscRegs[9].resize(1);
//Cop-0 Regs. Bank 10:
miscRegs[10].resize(1);
//Cop-0 Regs. Bank 11:
miscRegs[11].resize(1);
//Cop-0 Regs. Bank 12:
miscRegs[12].resize(4);
//Cop-0 Regs. Bank 13:
miscRegs[13].resize(1);
//Cop-0 Regs. Bank 14:
miscRegs[14].resize(1);
//Cop-0 Regs. Bank 15:
miscRegs[15].resize(2);
//Cop-0 Regs. Bank 16:
miscRegs[16].resize(4);
//Cop-0 Regs. Bank 17:
miscRegs[17].resize(1);
//Cop-0 Regs. Bank 18:
miscRegs[18].resize(8);
//Cop-0 Regs. Bank 19:
miscRegs[19].resize(8);
//Cop-0 Regs. Bank 20:
miscRegs[20].resize(1);
//Cop-0 Regs. Bank 21:
//miscRegs[21].resize(1);
//Reserved for future extensions
//Cop-0 Regs. Bank 22:
//miscRegs[22].resize(4);
//Available for implementation dependent use
//Cop-0 Regs. Bank 23:
miscRegs[23].resize(5);
//Cop-0 Regs. Bank 24:
miscRegs[24].resize(1);
//Cop-0 Regs. Bank 25:
miscRegs[25].resize(8);
//Cop-0 Regs. Bank 26:
miscRegs[26].resize(1);
//Cop-0 Regs. Bank 27:
miscRegs[27].resize(4);
//Cop-0 Regs. Bank 28:
miscRegs[28].resize(8);
//Cop-0 Regs. Bank 29:
miscRegs[29].resize(8);
//Cop-0 Regs. Bank 30:
miscRegs[30].resize(1);
//Cop-0 Regs. Bank 31:
miscRegs[31].resize(1);*/
}
const Addr MipsISA::PageShift = 13;
const Addr MipsISA::PageBytes = ULL(1) << PageShift;
const Addr MipsISA::PageMask = ~(PageBytes - 1);
const Addr MipsISA::PageOffset = PageBytes - 1;
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
// Translation stuff
//
const Addr MipsISA::PteShift = 3;
const Addr MipsISA::NPtePageShift = PageShift - PteShift;
const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift;
const Addr MipsISA::PteMask = NPtePage - 1;
// User Virtual
const Addr MipsISA::USegBase = ULL(0x0);
const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff);
// Kernel Direct Mapped
const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000);
const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff);
// Kernel Virtual
const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000);
const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff);
#endif
// Mips UNOP (sll r0,r0,r0)
const MachInst MipsISA::NoopMachInst = 0x00000000;
static inline Addr
TruncPage(Addr addr)
{ return addr & ~(MipsISA::PageBytes - 1); }
static inline Addr
RoundPage(Addr addr)
{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
void
RegFile::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(intRegFile, NumIntRegs);
SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
//SERIALIZE_SCALAR(miscRegs.fpcr);
//SERIALIZE_SCALAR(miscRegs.uniq);
//SERIALIZE_SCALAR(miscRegs.lock_flag);
//SERIALIZE_SCALAR(miscRegs.lock_addr);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
#if FULL_SYSTEM
SERIALIZE_ARRAY(palregs, NumIntRegs);
SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
SERIALIZE_SCALAR(intrflag);
SERIALIZE_SCALAR(pal_shadow);
#endif
}
void
RegFile::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(intRegFile, NumIntRegs);
UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
//UNSERIALIZE_SCALAR(miscRegs.uniq);
//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
#if FULL_SYSTEM
UNSERIALIZE_ARRAY(palregs, NumIntRegs);
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
UNSERIALIZE_SCALAR(intrflag);
UNSERIALIZE_SCALAR(pal_shadow);
#endif
}
#if FULL_SYSTEM
void
PTE::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(tag);
SERIALIZE_SCALAR(ppn);
SERIALIZE_SCALAR(xre);
SERIALIZE_SCALAR(xwe);
SERIALIZE_SCALAR(asn);
SERIALIZE_SCALAR(asma);
SERIALIZE_SCALAR(fonr);
SERIALIZE_SCALAR(fonw);
SERIALIZE_SCALAR(valid);
}
void
PTE::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(tag);
UNSERIALIZE_SCALAR(ppn);
UNSERIALIZE_SCALAR(xre);
UNSERIALIZE_SCALAR(xwe);
UNSERIALIZE_SCALAR(asn);
UNSERIALIZE_SCALAR(asma);
UNSERIALIZE_SCALAR(fonr);
UNSERIALIZE_SCALAR(fonw);
UNSERIALIZE_SCALAR(valid);
}
#endif //FULL_SYSTEM

546
arch/mips/isa_traits.hh Normal file
View file

@ -0,0 +1,546 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
//#include "arch/mips/misc_regfile.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
#include "sim/faults.hh"
#include <vector>
class FastCPU;
class FullCPU;
class Checkpoint;
namespace LittleEndianGuest {};
using namespace LittleEndianGuest;
#define TARGET_MIPS
class StaticInst;
class StaticInstPtr;
namespace MIPS34K {
int DTB_ASN_ASN(uint64_t reg);
int ITB_ASN_ASN(uint64_t reg);
};
namespace MipsISA
{
typedef uint32_t MachInst;
// typedef uint64_t Addr;
typedef uint8_t RegIndex;
enum {
MemoryEnd = 0xffffffffffffffffULL,
NumIntRegs = 32,
NumFloatRegs = 32,
NumMiscRegs = 258, //account for hi,lo regs
MaxRegsOfAnyType = 32,
// Static instruction parameters
MaxInstSrcRegs = 3,
MaxInstDestRegs = 2,
// semantically meaningful register indices
ZeroReg = 0, // architecturally meaningful
// the rest of these depend on the ABI
StackPointerReg = 30,
GlobalPointerReg = 29,
ProcedureValueReg = 27,
ReturnAddressReg = 26,
ReturnValueReg = 0,
FramePointerReg = 15,
ArgumentReg0 = 16,
ArgumentReg1 = 17,
ArgumentReg2 = 18,
ArgumentReg3 = 19,
ArgumentReg4 = 20,
ArgumentReg5 = 21,
LogVMPageSize = 13, // 8K bytes
VMPageSize = (1 << LogVMPageSize),
BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
WordBytes = 4,
HalfwordBytes = 2,
ByteBytes = 1,
DepNA = 0,
};
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 64,
Fpcr_DepTag = 64, // floating point control register
Uniq_DepTag = 65,
IPR_Base_DepTag = 66,
MiscReg_DepTag = 67
};
typedef uint64_t IntReg;
typedef IntReg IntRegFile[NumIntRegs];
// floating point register file entry type
typedef union {
uint64_t q;
double d;
} FloatReg;
typedef union {
uint64_t q[NumFloatRegs]; // integer qword view
double d[NumFloatRegs]; // double-precision floating point view
} FloatRegFile;
// cop-0/cop-1 system control register file
typedef uint64_t MiscReg;
//typedef MiscReg MiscRegFile[NumMiscRegs];
class MiscRegFile {
public:
MiscReg
protected:
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
MiscReg miscRegFile[NumMiscRegs];
public:
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
MiscReg readReg(int misc_reg)
{ return miscRegFile[misc_reg]; }
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
{ return miscRegFile[misc_reg];}
Fault setReg(int misc_reg, const MiscReg &val)
{ miscRegFile[misc_reg] = val; return NoFault; }
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc)
{ miscRegFile[misc_reg] = val; return NoFault; }
#if FULL_SYSTEM
void clearIprs() { };
protected:
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
#endif
friend class RegFile;
};
enum MiscRegTags {
//Coprocessor 0 Registers
//Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
//(Register Number-Register Select) Summary of Register
//------------------------------------------------------
Index = 0, //0-0 Index into the TLB array
MVPControl = 1, //0-1 Per-processor register containing global
//MIPS® MT configuration data
MVPConf0 = 2, //0-2 Per-processor register containing global
//MIPS® MT configuration data
MVPConf1 = 3, //0-3 Per-processor register containing global
//MIPS® MT configuration data
Random = 8, //1-0 Randomly generated index into the TLB array
VPEControl = 9, //1-1 Per-VPE register containing relatively volatile
//thread configuration data
VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration
//information
VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration
//information
YQMask = 12, //Per-VPE register defining which YIELD
//qualifier bits may be used without generating
//an exception
VPESchedule = 13,
VPEScheFBack = 14,
VPEOpt = 15,
EntryLo0 = 16, // Bank 3: 16 - 23
TCStatus = 17,
TCBind = 18,
TCRestart = 19,
TCHalt = 20,
TCContext = 21,
TCSchedule = 22,
TCScheFBack = 23,
EntryLo1 = 24,// Bank 4: 24 - 31
Context = 32, // Bank 5: 32 - 39
ContextConfig = 33,
//PageMask = 40, //Bank 6: 40 - 47
PageGrain = 41,
Wired = 48, //Bank 7:48 - 55
SRSConf0 = 49,
SRSConf1 = 50,
SRSConf2 = 51,
SRSConf3 = 52,
SRSConf4 = 53,
BadVAddr = 54,
HWRena = 56,//Bank 8:56 - 63
Count = 64, //Bank 9:64 - 71
EntryHi = 72,//Bank 10:72 - 79
Compare = 80,//Bank 11:80 - 87
Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control
IntCtl = 89, //12-1 Interrupt system status and control
SRSCtl = 90, //12-2 Shadow register set status and control
SRSMap = 91, //12-3 Shadow set IPL mapping
Cause = 97,//97-104 //13-0 Cause of last general exception
EPC = 105,//105-112 //14-0 Program counter at last exception
PRId = 113//113-120, //15-0 Processor identification and revision
EBase = 114, //15-1 Exception vector base register
Config = 121,//Bank 16: 121-128
Config1 = 122,
Config2 = 123,
Config3 = 124,
Config6 = 127,
Config7 = 128,
LLAddr = 129,//Bank 17: 129-136
WatchLo0 = 137,//Bank 18: 137-144
WatchLo1 = 138,
WatchLo2 = 139,
WatchLo3 = 140,
WatchLo4 = 141,
WatchLo5 = 142,
WatchLo6 = 143,
WatchLo7 = 144,
WatchHi0 = 145,//Bank 19: 145-152
WatchHi1 = 146,
WatchHi2 = 147,
WatchHi3 = 148,
WatchHi4 = 149,
WatchHi5 = 150,
WatchHi6 = 151,
WatchHi7 = 152,
XCContext64 = 153,//Bank 20: 153-160
//Bank 21: 161-168
//Bank 22: 169-176
Debug = 177, //Bank 23: 177-184
TraceControl1 = 178,
TraceControl2 = 179,
UserTraceData = 180,
TraceBPC = 181,
DEPC = 185,//Bank 24: 185-192
PerfCnt0 = 193,//Bank 25: 193 - 200
PerfCnt1 = 194,
PerfCnt2 = 195,
PerfCnt3 = 196,
PerfCnt4 = 197,
PerfCnt5 = 198,
PerfCnt6 = 199,
PerfCnt7 = 200,
ErrCtl = 201, //Bank 26: 201 - 208
CacheErr0 = 209, //Bank 27: 209 - 216
CacheErr1 = 210,
CacheErr2 = 211,
CacheErr3 = 212,
TagLo0 = 217,//Bank 28: 217 - 224
DataLo1 = 218,
TagLo2 = 219,
DataLo3 = 220,
TagLo4 = 221,
DataLo5 = 222,
TagLo6 = 223,
DataLo7 = 234,
TagHi0 = 233,//Bank 29: 233 - 240
DataHi1 = 234,
TagHi2 = 235,
DataHi3 = 236,
TagHi4 = 237,
DataHi5 = 238,
TagHi6 = 239,
DataHi7 = 240,
ErrorEPC = 249,//Bank 30: 241 - 248
DESAVE = 257,//Bank 31: 249-256
//More Misc. Regs
Hi,
Lo,
FCSR,
FPCR,
//Alpha Regs, but here now, for
//compiling sake
UNIQ,
LockAddr,
LockFlag
};
extern const Addr PageShift;
extern const Addr PageBytes;
extern const Addr PageMask;
extern const Addr PageOffset;
#if FULL_SYSTEM
typedef uint64_t InternalProcReg;
#include "arch/mips/isa_fullsys_traits.hh"
#else
enum {
NumInternalProcRegs = 0
};
#endif
enum {
TotalNumRegs =
NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
};
enum {
TotalDataRegs = NumIntRegs + NumFloatRegs
};
typedef union {
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
} AnyReg;
struct RegFile {
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegs; // control register file
Addr pc; // program counter
Addr npc; // next-cycle program counter
Addr nnpc; // next-next-cycle program counter
// used to implement branch delay slot
// not real register
MiscReg hi; // MIPS HI Register
MiscReg lo; // MIPS LO Register
#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
#endif // FULL_SYSTEM
//void initCP0Regs();
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void createCP0Regs();
void coldReset();
};
StaticInstPtr decodeInst(MachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
enum annotes {
ANNOTE_NONE = 0,
// An impossible number for instruction annotations
ITOUCH_ANNOTE = 0xffffffff,
};
void getMiscRegIdx(int reg_name,int &idx, int &sel);
static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
}
static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return (reg >= 9 && reg <= 15);
}
static inline bool isCallerSaveFloatRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
static inline Addr alignAddress(const Addr &addr,
unsigned int nbytes) {
return (addr & ~(nbytes - 1));
}
// Instruction address compression hooks
static inline Addr realPCToFetchPC(const Addr &addr) {
return addr;
}
static inline Addr fetchPCToRealPC(const Addr &addr) {
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
static inline size_t fetchInstSize() {
return sizeof(MachInst);
}
static inline MachInst makeRegisterCopy(int dest, int src) {
panic("makeRegisterCopy not implemented");
return 0;
}
// Machine operations
void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
int regnum);
void restoreMachineReg(RegFile &regs, const AnyReg &reg,
int regnum);
#if 0
static void serializeSpecialRegs(const Serializable::Proxy &proxy,
const RegFile &regs);
static void unserializeSpecialRegs(const IniFile *db,
const std::string &category,
ConfigNode *node,
RegFile &regs);
#endif
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
void zeroRegisters(XC *xc);
const Addr MaxAddr = (Addr)-1;
};
#if !FULL_SYSTEM
class SyscallReturn {
public:
template <class T>
SyscallReturn(T v, bool s)
{
retval = (uint64_t)v;
success = s;
}
template <class T>
SyscallReturn(T v)
{
success = (v >= 0);
retval = (uint64_t)v;
}
~SyscallReturn() {}
SyscallReturn& operator=(const SyscallReturn& s) {
retval = s.retval;
success = s.success;
return *this;
}
bool successful() { return success; }
uint64_t value() { return retval; }
private:
uint64_t retval;
bool success;
};
#endif
#if FULL_SYSTEM
//typedef TheISA::InternalProcReg InternalProcReg;
//const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
//const int NumInterruptLevels = TheISA::NumInterruptLevels;
#include "arch/mips/mips34k.hh"
#endif
#endif // __ARCH_MIPS_ISA_TRAITS_HH__

539
arch/alpha/alpha_linux_process.cc → arch/mips/linux_process.cc
View file

@ -26,457 +26,97 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dirent.h>
#include <errno.h>
#include <fcntl.h> // for host open() flags
#include <string.h> // for memset()
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "mem/translating_port.hh"
#include "sim/fake_syscall.hh"
#include "sim/host.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "arch/alpha/alpha_common_syscall_emul.hh"
#include "sim/syscall_emul.hh"
#include "sim/root.hh" // for curTick & ticksPerSecond
#include "arch/alpha/alpha_linux_process.hh"
#include "arch/mips/common_syscall_emul.hh"
#include "arch/mips/linux_process.hh"
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "kern/linux/linux.hh"
#include "mem/functional/functional.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
using namespace std;
using namespace MipsISA;
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Alpha Linux
/// syscall interface.
///
class Linux {
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
public:
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->release, "2.4.20");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "mips");
//@{
/// Basic Linux types.
typedef uint64_t size_t;
typedef uint64_t off_t;
typedef int64_t time_t;
typedef uint32_t uid_t;
typedef uint32_t gid_t;
//@}
name.copyOut(xc->mem);
return 0;
}
//@{
/// open(2) flag values.
static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY
static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY
static const int TGT_O_RDWR = 00000002; //!< O_RDWR
static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK
static const int TGT_O_APPEND = 00000010; //!< O_APPEND
static const int TGT_O_CREAT = 00001000; //!< O_CREAT
static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC
static const int TGT_O_EXCL = 00004000; //!< O_EXCL
static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY
static const int TGT_O_SYNC = 00040000; //!< O_SYNC
static const int TGT_O_DRD = 00100000; //!< O_DRD
static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO
static const int TGT_O_CACHE = 00400000; //!< O_CACHE
static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC
static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC
//@}
/// Target osf_getsysyinfo() handler. Even though this call is
/// borrowed from Tru64, the subcases that get used appear to be
/// different in practice from those used by Tru64 processes.
static SyscallReturn
osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
// unsigned nbytes = xc->getSyscallArg(2);
/// This table maps the target open() flags to the corresponding
/// host open() flags.
static OpenFlagTransTable openFlagTable[];
switch (op) {
/// Number of entries in openFlagTable[].
static const int NUM_OPEN_FLAGS;
case 45: { // GSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
fpcr.copyOut(xc->mem);
return 0;
}
/// Stat buffer. Note that we can't call it 'stat' since that
/// gets #defined to something else on some systems.
struct tgt_stat {
uint32_t st_dev; //!< device
uint32_t st_ino; //!< inode
uint32_t st_mode; //!< mode
uint32_t st_nlink; //!< link count
uint32_t st_uid; //!< owner's user ID
uint32_t st_gid; //!< owner's group ID
uint32_t st_rdev; //!< device number
int32_t _pad1; //!< for alignment
int64_t st_size; //!< file size in bytes
uint64_t st_atimeX; //!< time of last access
uint64_t st_mtimeX; //!< time of last modification
uint64_t st_ctimeX; //!< time of last status change
uint32_t st_blksize; //!< optimal I/O block size
int32_t st_blocks; //!< number of blocks allocated
uint32_t st_flags; //!< flags
uint32_t st_gen; //!< unknown
};
// same for stat64
struct tgt_stat64 {
uint64_t st_dev;
uint64_t st_ino;
uint64_t st_rdev;
int64_t st_size;
uint64_t st_blocks;
uint32_t st_mode;
uint32_t st_uid;
uint32_t st_gid;
uint32_t st_blksize;
uint32_t st_nlink;
uint32_t __pad0;
uint64_t tgt_st_atime;
uint64_t st_atime_nsec;
uint64_t tgt_st_mtime;
uint64_t st_mtime_nsec;
uint64_t tgt_st_ctime;
uint64_t st_ctime_nsec;
int64_t __unused[3];
};
/// Length of strings in struct utsname (plus 1 for null char).
static const int _SYS_NMLN = 65;
/// Interface struct for uname().
struct utsname {
char sysname[_SYS_NMLN]; //!< System name.
char nodename[_SYS_NMLN]; //!< Node name.
char release[_SYS_NMLN]; //!< OS release.
char version[_SYS_NMLN]; //!< OS version.
char machine[_SYS_NMLN]; //!< Machine type.
};
//@{
/// ioctl() command codes.
static const unsigned TIOCGETP = 0x40067408;
static const unsigned TIOCSETP = 0x80067409;
static const unsigned TIOCSETN = 0x8006740a;
static const unsigned TIOCSETC = 0x80067411;
static const unsigned TIOCGETC = 0x40067412;
static const unsigned FIONREAD = 0x4004667f;
static const unsigned TIOCISATTY = 0x2000745e;
static const unsigned TIOCGETS = 0x402c7413;
static const unsigned TIOCGETA = 0x40127417;
//@}
/// Resource enumeration for getrlimit().
enum rlimit_resources {
RLIMIT_CPU = 0,
RLIMIT_FSIZE = 1,
RLIMIT_DATA = 2,
RLIMIT_STACK = 3,
RLIMIT_CORE = 4,
RLIMIT_RSS = 5,
RLIMIT_NOFILE = 6,
RLIMIT_AS = 7,
RLIMIT_VMEM = 7,
RLIMIT_NPROC = 8,
RLIMIT_MEMLOCK = 9,
RLIMIT_LOCKS = 10
};
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
uint64_t rlim_cur; //!< soft limit
uint64_t rlim_max; //!< hard limit
};
/// For mmap().
static const unsigned TGT_MAP_ANONYMOUS = 0x10;
/// For gettimeofday().
struct timeval {
int64_t tv_sec; //!< seconds
int64_t tv_usec; //!< microseconds
};
// For writev/readv
struct tgt_iovec {
uint64_t iov_base; // void *
uint64_t iov_len;
};
//@{
/// For getrusage().
static const int RUSAGE_SELF = 0;
static const int RUSAGE_CHILDREN = -1;
static const int RUSAGE_BOTH = -2;
//@}
/// For getrusage().
struct rusage {
struct timeval ru_utime; //!< user time used
struct timeval ru_stime; //!< system time used
int64_t ru_maxrss; //!< max rss
int64_t ru_ixrss; //!< integral shared memory size
int64_t ru_idrss; //!< integral unshared data "
int64_t ru_isrss; //!< integral unshared stack "
int64_t ru_minflt; //!< page reclaims - total vmfaults
int64_t ru_majflt; //!< page faults
int64_t ru_nswap; //!< swaps
int64_t ru_inblock; //!< block input operations
int64_t ru_oublock; //!< block output operations
int64_t ru_msgsnd; //!< messages sent
int64_t ru_msgrcv; //!< messages received
int64_t ru_nsignals; //!< signals received
int64_t ru_nvcsw; //!< voluntary context switches
int64_t ru_nivcsw; //!< involuntary "
};
/// Helper function to convert a host stat buffer to a target stat
/// buffer. Also copies the target buffer out to the simulated
/// memory space. Used by stat(), fstat(), and lstat().
static void
copyOutStatBuf(TranslatingPort *memPort, Addr addr, struct stat *host)
{
TypedBufferArg<Linux::tgt_stat> tgt(addr);
tgt->st_dev = host->st_dev;
tgt->st_ino = host->st_ino;
tgt->st_mode = host->st_mode;
tgt->st_nlink = host->st_nlink;
tgt->st_uid = host->st_uid;
tgt->st_gid = host->st_gid;
tgt->st_rdev = host->st_rdev;
tgt->st_size = host->st_size;
tgt->st_atimeX = host->st_atime;
tgt->st_mtimeX = host->st_mtime;
tgt->st_ctimeX = host->st_ctime;
tgt->st_blksize = host->st_blksize;
tgt->st_blocks = host->st_blocks;
tgt.copyOut(memPort);
default:
cerr << "osf_getsysinfo: unknown op " << op << endl;
abort();
break;
}
// Same for stat64
static void
copyOutStat64Buf(TranslatingPort *memPort, Addr addr, struct stat64 *host)
{
TypedBufferArg<Linux::tgt_stat64> tgt(addr);
return 1;
}
// XXX byteswaps
tgt->st_dev = host->st_dev;
// XXX What about STAT64_HAS_BROKEN_ST_INO ???
tgt->st_ino = host->st_ino;
tgt->st_rdev = host->st_rdev;
tgt->st_size = host->st_size;
tgt->st_blocks = host->st_blocks;
/// Target osf_setsysinfo() handler.
static SyscallReturn
osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
// unsigned nbytes = xc->getSyscallArg(2);
tgt->st_mode = host->st_mode;
tgt->st_uid = host->st_uid;
tgt->st_gid = host->st_gid;
tgt->st_blksize = host->st_blksize;
tgt->st_nlink = host->st_nlink;
tgt->tgt_st_atime = host->st_atime;
tgt->tgt_st_mtime = host->st_mtime;
tgt->tgt_st_ctime = host->st_ctime;
#ifdef STAT_HAVE_NSEC
tgt->st_atime_nsec = host->st_atime_nsec;
tgt->st_mtime_nsec = host->st_mtime_nsec;
tgt->st_ctime_nsec = host->st_ctime_nsec;
#else
tgt->st_atime_nsec = 0;
tgt->st_mtime_nsec = 0;
tgt->st_ctime_nsec = 0;
#endif
tgt.copyOut(memPort);
switch (op) {
case 14: { // SSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
fpcr.copyIn(xc->mem);
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
}
default:
cerr << "osf_setsysinfo: unknown op " << op << endl;
abort();
break;
}
/// The target system's hostname.
static const char *hostname;
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, hostname);
strcpy(name->release, "2.4.20");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
name.copyOut(xc->port);
return 0;
}
/// Target osf_getsysyinfo() handler. Even though this call is
/// borrowed from Tru64, the subcases that get used appear to be
/// different in practice from those used by Tru64 processes.
static SyscallReturn
osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
// unsigned nbytes = xc->getSyscallArg(2);
switch (op) {
case 45: { // GSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
fpcr.copyOut(xc->port);
return 0;
}
default:
cerr << "osf_getsysinfo: unknown op " << op << endl;
abort();
break;
}
return 1;
}
/// Target osf_setsysinfo() handler.
static SyscallReturn
osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
unsigned op = xc->getSyscallArg(0);
// unsigned nbytes = xc->getSyscallArg(2);
switch (op) {
case 14: { // SSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
fpcr.copyIn(xc->port);
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", *(uint64_t*)fpcr);
return 0;
}
default:
cerr << "osf_setsysinfo: unknown op " << op << endl;
abort();
break;
}
return 1;
}
/// Target fnctl() handler.
static SyscallReturn
fcntlFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
int fd = xc->getSyscallArg(0);
if (fd < 0 || process->sim_fd(fd) < 0)
return -EBADF;
int cmd = xc->getSyscallArg(1);
switch (cmd) {
case 0: // F_DUPFD
// if we really wanted to support this, we'd need to do it
// in the target fd space.
warn("fcntl(%d, F_DUPFD) not supported, error returned\n", fd);
return -EMFILE;
case 1: // F_GETFD (get close-on-exec flag)
case 2: // F_SETFD (set close-on-exec flag)
return 0;
case 3: // F_GETFL (get file flags)
case 4: // F_SETFL (set file flags)
// not sure if this is totally valid, but we'll pass it through
// to the underlying OS
warn("fcntl(%d, %d) passed through to host\n", fd, cmd);
return fcntl(process->sim_fd(fd), cmd);
// return 0;
case 7: // F_GETLK (get lock)
case 8: // F_SETLK (set lock)
case 9: // F_SETLKW (set lock and wait)
// don't mess with file locking... just act like it's OK
warn("File lock call (fcntl(%d, %d)) ignored.\n", fd, cmd);
return 0;
default:
warn("Unknown fcntl command %d\n", cmd);
return 0;
}
}
/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
/// Number of syscalls in syscallDescs[].
static const int Num_Syscall_Descs;
/// Max supported syscall number.
static const int Max_Syscall_Desc;
/// Do the specified syscall. Just looks the call number up in
/// the table and invokes the appropriate handler.
static void
doSyscall(int callnum, Process *process, ExecContext *xc)
{
if (callnum < 0 || callnum > Max_Syscall_Desc) {
fatal("Syscall %d out of range", callnum);
}
SyscallDesc *desc = &syscallDescs[callnum];
desc->doSyscall(callnum, process, xc);
}
}; // class Linux
return 1;
}
// open(2) flags translation table
OpenFlagTransTable Linux::openFlagTable[] = {
#ifdef _MSC_VER
{ Linux::TGT_O_RDONLY, _O_RDONLY },
{ Linux::TGT_O_WRONLY, _O_WRONLY },
{ Linux::TGT_O_RDWR, _O_RDWR },
{ Linux::TGT_O_APPEND, _O_APPEND },
{ Linux::TGT_O_CREAT, _O_CREAT },
{ Linux::TGT_O_TRUNC, _O_TRUNC },
{ Linux::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
{ Linux::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
{ Linux::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
{ Linux::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
{ Linux::TGT_O_RDONLY, O_RDONLY },
{ Linux::TGT_O_WRONLY, O_WRONLY },
{ Linux::TGT_O_RDWR, O_RDWR },
{ Linux::TGT_O_APPEND, O_APPEND },
{ Linux::TGT_O_CREAT, O_CREAT },
{ Linux::TGT_O_TRUNC, O_TRUNC },
{ Linux::TGT_O_EXCL, O_EXCL },
{ Linux::TGT_O_NONBLOCK, O_NONBLOCK },
{ Linux::TGT_O_NOCTTY, O_NOCTTY },
#ifdef O_SYNC
{ Linux::TGT_O_SYNC, O_SYNC },
#endif
#endif /* _MSC_VER */
};
const int Linux::NUM_OPEN_FLAGS =
(sizeof(Linux::openFlagTable)/sizeof(Linux::openFlagTable[0]));
const char *Linux::hostname = "m5.eecs.umich.edu";
SyscallDesc Linux::syscallDescs[] = {
SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 0 */ SyscallDesc("osf_syscall", unimplementedFunc),
/* 1 */ SyscallDesc("exit", exitFunc),
/* 2 */ SyscallDesc("fork", unimplementedFunc),
@ -924,32 +564,25 @@ SyscallDesc Linux::syscallDescs[] = {
/* 441 */ SyscallDesc("keyctl", unimplementedFunc)
};
const int Linux::Num_Syscall_Descs =
sizeof(Linux::syscallDescs) / sizeof(SyscallDesc);
const int Linux::Max_Syscall_Desc = Linux::Num_Syscall_Descs - 1;
void
AlphaLinuxProcess::syscall(ExecContext *xc)
{
num_syscalls++;
int64_t callnum = xc->regs.intRegFile[ReturnValueReg];
Linux::doSyscall(callnum, this, xc);
}
AlphaLinuxProcess::AlphaLinuxProcess(const std::string &name,
MipsLinuxProcess::MipsLinuxProcess(const std::string &name,
ObjectFile *objFile,
System *system,
int stdin_fd,
int stdout_fd,
int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp)
: LiveProcess(name, objFile, system, stdin_fd, stdout_fd, stderr_fd,
argv, envp)
: LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
{
init_regs->intRegFile[0] = 0;
}
SyscallDesc*
MipsLinuxProcess::getDesc(int callnum)
{
if (callnum < 0 || callnum > Num_Syscall_Descs)
return NULL;
return &syscallDescs[callnum];
}

58
arch/mips/linux_process.hh Normal file
View file

@ -0,0 +1,58 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MIPS_LINUX_PROCESS_HH__
#define __MIPS_LINUX_PROCESS_HH__
#include "sim/process.hh"
/// A process with emulated Mips/Linux syscalls.
class MipsLinuxProcess : public LiveProcess
{
public:
/// Constructor.
MipsLinuxProcess(const std::string &name,
ObjectFile *objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp);
virtual SyscallDesc* getDesc(int callnum);
/// The target system's hostname.
static const char *hostname;
/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
const int Num_Syscall_Descs;
};
#endif // __MIPS_LINUX_PROCESS_HH__

56
arch/mips/process.cc Normal file
View file

@ -0,0 +1,56 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/mips/process.hh"
namespace MipsISA
{
LiveProcess *
createProcess(const string &nm, ObjectFile * objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
vector<string> &argv, vector<string> &envp)
{
LiveProcess * process = NULL;
if (objFile->getArch() != ObjectFile::MIPS)
fatal("Object file does not match architecture.");
switch (objFile->getOpSys()) {
case ObjectFile::Linux:
process = new MipsLinuxProcess(nm, objFile,
stdin_fd, stdout_fd, stderr_fd,
argv, envp);
break;
default:
fatal("Unknown/unsupported operating system.");
}
return process;
}
} // namespace MipsISA

45
arch/mips/process.hh Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MIPS_PROCESS_HH__
#define __MIPS_PROCESS_HH__
#include "arch/mips/linux_process.hh"
#include "base/loader/object_file.hh"
namespace MipsISA
{
LiveProcess *
createProcess(const string &nm, ObjectFile * objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
vector<string> &argv, vector<string> &envp);
} // namespace MipsISA
#endif // __MIPS_PROCESS_HH__

119
arch/mips/stacktrace.hh Normal file
View file

@ -0,0 +1,119 @@
/*
* Copyright (c) 2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ALPHA_STACKTRACE_HH__
#define __ARCH_ALPHA_STACKTRACE_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
class ExecContext;
class StackTrace;
class ProcessInfo
{
private:
ExecContext *xc;
int thread_info_size;
int task_struct_size;
int task_off;
int pid_off;
int name_off;
public:
ProcessInfo(ExecContext *_xc);
Addr task(Addr ksp) const;
int pid(Addr ksp) const;
std::string name(Addr ksp) const;
};
class StackTrace
{
protected:
typedef TheISA::MachInst MachInst;
private:
ExecContext *xc;
std::vector<Addr> stack;
private:
bool isEntry(Addr addr);
bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
bool decodeSave(MachInst inst, int &reg, int &disp);
bool decodeStack(MachInst inst, int &disp);
void trace(ExecContext *xc, bool is_call);
public:
StackTrace();
StackTrace(ExecContext *xc, StaticInstPtr inst);
~StackTrace();
void clear()
{
xc = 0;
stack.clear();
}
bool valid() const { return xc != NULL; }
bool trace(ExecContext *xc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
static const int user = 1;
static const int console = 2;
static const int unknown = 3;
#if TRACING_ON
private:
void dump();
public:
void dprintf() { if (DTRACE(Stack)) dump(); }
#else
public:
void dprintf() {}
#endif
};
inline bool
StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
if (valid())
clear();
trace(xc, !inst->isReturn());
return true;
}
#endif // __ARCH_ALPHA_STACKTRACE_HH__

82
arch/sparc/SConscript Normal file
View file

@ -0,0 +1,82 @@
# -*- mode:python -*-
# Copyright (c) 2004-2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import sys
from os.path import isdir
# Import build environment variable from SConstruct.
Import('env')
###################################################
#
# Define needed sources.
#
###################################################
# Base sources used by all configurations.
base_sources = Split('''
faults.cc
isa_traits.cc
''')
# Full-system sources
full_system_sources = Split('''
tlb.cc
arguments.cc
ev5.cc
osfpal.cc
stacktrace.cc
vtophys.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
common_syscall_emul.cc
linux_process.cc
process.cc
''')
sources = base_sources
if env['FULL_SYSTEM']:
sources += full_system_sources
else:
sources += syscall_emulation_sources
# Convert file names to SCons File objects. This takes care of the
# path relative to the top of the directory tree.
sources = [File(s) for s in sources]
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
# Only non-header files need to be compiled.
isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
sources += isa_desc_sources
Return('sources')

248
arch/sparc/faults.cc Normal file
View file

@ -0,0 +1,248 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/sparc/faults.hh"
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
namespace SparcISA
{
FaultName InternalProcessorError::_name = "intprocerr";
TrapType InternalProcessorError::_trapType = 0x029;
FaultPriority InternalProcessorError::_priority = 4;
FaultStat InternalProcessorError::_count;
FaultName MemAddressNotAligned::_name = "unalign";
TrapType MemAddressNotAligned::_trapType = 0x034;
FaultPriority MemAddressNotAligned::_priority = 10;
FaultStat MemAddressNotAligned::_count;
FaultName PowerOnReset::_name = "pow_reset";
TrapType PowerOnReset::_trapType = 0x001;
FaultPriority PowerOnReset::_priority = 0;
FaultStat PowerOnReset::_count;
FaultName WatchDogReset::_name = "watch_dog_reset";
TrapType WatchDogReset::_trapType = 0x002;
FaultPriority WatchDogReset::_priority = 1;
FaultStat WatchDogReset::_count;
FaultName ExternallyInitiatedReset::_name = "extern_reset";
TrapType ExternallyInitiatedReset::_trapType = 0x003;
FaultPriority ExternallyInitiatedReset::_priority = 1;
FaultStat ExternallyInitiatedReset::_count;
FaultName SoftwareInitiatedReset::_name = "software_reset";
TrapType SoftwareInitiatedReset::_trapType = 0x004;
FaultPriority SoftwareInitiatedReset::_priority = 1;
FaultStat SoftwareInitiatedReset::_count;
FaultName REDStateException::_name = "red_counte";
TrapType REDStateException::_trapType = 0x005;
FaultPriority REDStateException::_priority = 1;
FaultStat REDStateException::_count;
FaultName InstructionAccessException::_name = "inst_access";
TrapType InstructionAccessException::_trapType = 0x008;
FaultPriority InstructionAccessException::_priority = 5;
FaultStat InstructionAccessException::_count;
FaultName InstructionAccessMMUMiss::_name = "inst_mmu";
TrapType InstructionAccessMMUMiss::_trapType = 0x009;
FaultPriority InstructionAccessMMUMiss::_priority = 2;
FaultStat InstructionAccessMMUMiss::_count;
FaultName InstructionAccessError::_name = "inst_error";
TrapType InstructionAccessError::_trapType = 0x00A;
FaultPriority InstructionAccessError::_priority = 3;
FaultStat InstructionAccessError::_count;
FaultName IllegalInstruction::_name = "illegal_inst";
TrapType IllegalInstruction::_trapType = 0x010;
FaultPriority IllegalInstruction::_priority = 7;
FaultStat IllegalInstruction::_count;
FaultName PrivelegedOpcode::_name = "priv_opcode";
TrapType PrivelegedOpcode::_trapType = 0x011;
FaultPriority PrivelegedOpcode::_priority = 6;
FaultStat PrivelegedOpcode::_count;
FaultName UnimplementedLDD::_name = "unimp_ldd";
TrapType UnimplementedLDD::_trapType = 0x012;
FaultPriority UnimplementedLDD::_priority = 6;
FaultStat UnimplementedLDD::_count;
FaultName UnimplementedSTD::_name = "unimp_std";
TrapType UnimplementedSTD::_trapType = 0x013;
FaultPriority UnimplementedSTD::_priority = 6;
FaultStat UnimplementedSTD::_count;
FaultName FpDisabled::_name = "fp_disabled";
TrapType FpDisabled::_trapType = 0x020;
FaultPriority FpDisabled::_priority = 8;
FaultStat FpDisabled::_count;
FaultName FpExceptionIEEE754::_name = "fp_754";
TrapType FpExceptionIEEE754::_trapType = 0x021;
FaultPriority FpExceptionIEEE754::_priority = 11;
FaultStat FpExceptionIEEE754::_count;
FaultName FpExceptionOther::_name = "fp_other";
TrapType FpExceptionOther::_trapType = 0x022;
FaultPriority FpExceptionOther::_priority = 11;
FaultStat FpExceptionOther::_count;
FaultName TagOverflow::_name = "tag_overflow";
TrapType TagOverflow::_trapType = 0x023;
FaultPriority TagOverflow::_priority = 14;
FaultStat TagOverflow::_count;
FaultName DivisionByZero::_name = "div_by_zero";
TrapType DivisionByZero::_trapType = 0x028;
FaultPriority DivisionByZero::_priority = 15;
FaultStat DivisionByZero::_count;
FaultName DataAccessException::_name = "data_access";
TrapType DataAccessException::_trapType = 0x030;
FaultPriority DataAccessException::_priority = 12;
FaultStat DataAccessException::_count;
FaultName DataAccessMMUMiss::_name = "data_mmu";
TrapType DataAccessMMUMiss::_trapType = 0x031;
FaultPriority DataAccessMMUMiss::_priority = 12;
FaultStat DataAccessMMUMiss::_count;
FaultName DataAccessError::_name = "data_error";
TrapType DataAccessError::_trapType = 0x032;
FaultPriority DataAccessError::_priority = 12;
FaultStat DataAccessError::_count;
FaultName DataAccessProtection::_name = "data_protection";
TrapType DataAccessProtection::_trapType = 0x033;
FaultPriority DataAccessProtection::_priority = 12;
FaultStat DataAccessProtection::_count;
FaultName LDDFMemAddressNotAligned::_name = "unalign_lddf";
TrapType LDDFMemAddressNotAligned::_trapType = 0x035;
FaultPriority LDDFMemAddressNotAligned::_priority = 10;
FaultStat LDDFMemAddressNotAligned::_count;
FaultName STDFMemAddressNotAligned::_name = "unalign_stdf";
TrapType STDFMemAddressNotAligned::_trapType = 0x036;
FaultPriority STDFMemAddressNotAligned::_priority = 10;
FaultStat STDFMemAddressNotAligned::_count;
FaultName PrivelegedAction::_name = "priv_action";
TrapType PrivelegedAction::_trapType = 0x037;
FaultPriority PrivelegedAction::_priority = 11;
FaultStat PrivelegedAction::_count;
FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf";
TrapType LDQFMemAddressNotAligned::_trapType = 0x038;
FaultPriority LDQFMemAddressNotAligned::_priority = 10;
FaultStat LDQFMemAddressNotAligned::_count;
FaultName STQFMemAddressNotAligned::_name = "unalign_stqf";
TrapType STQFMemAddressNotAligned::_trapType = 0x039;
FaultPriority STQFMemAddressNotAligned::_priority = 10;
FaultStat STQFMemAddressNotAligned::_count;
FaultName AsyncDataError::_name = "async_data";
TrapType AsyncDataError::_trapType = 0x040;
FaultPriority AsyncDataError::_priority = 2;
FaultStat AsyncDataError::_count;
//The enumerated faults
FaultName CleanWindow::_name = "clean_win";
TrapType CleanWindow::_baseTrapType = 0x024;
FaultPriority CleanWindow::_priority = 10;
FaultStat CleanWindow::_count;
FaultName InterruptLevelN::_name = "interrupt_n";
TrapType InterruptLevelN::_baseTrapType = 0x041;
FaultStat InterruptLevelN::_count;
FaultName SpillNNormal::_name = "spill_n_normal";
TrapType SpillNNormal::_baseTrapType = 0x080;
FaultPriority SpillNNormal::_priority = 9;
FaultStat SpillNNormal::_count;
FaultName SpillNOther::_name = "spill_n_other";
TrapType SpillNOther::_baseTrapType = 0x0A0;
FaultPriority SpillNOther::_priority = 9;
FaultStat SpillNOther::_count;
FaultName FillNNormal::_name = "fill_n_normal";
TrapType FillNNormal::_baseTrapType = 0x0C0;
FaultPriority FillNNormal::_priority = 9;
FaultStat FillNNormal::_count;
FaultName FillNOther::_name = "fill_n_other";
TrapType FillNOther::_baseTrapType = 0x0E0;
FaultPriority FillNOther::_priority = 9;
FaultStat FillNOther::_count;
FaultName TrapInstruction::_name = "trap_inst_n";
TrapType TrapInstruction::_baseTrapType = 0x100;
FaultPriority TrapInstruction::_priority = 16;
FaultStat TrapInstruction::_count;
#if FULL_SYSTEM
void SparcFault::invoke(ExecContext * xc)
{
FaultBase::invoke(xc);
countStat()++;
//Use the SPARC trap state machine
/*// exception restart address
if (setRestartAddress() || !xc->inPalMode())
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
if (!xc->inPalMode())
AlphaISA::swap_palshadow(&(xc->regs), true);
xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
}
#endif
} // namespace SparcISA

587
arch/sparc/faults.hh Normal file
View file

@ -0,0 +1,587 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
namespace SparcISA
{
typedef const uint32_t TrapType;
typedef const uint32_t FaultPriority;
class SparcFault : public FaultBase
{
public:
#if FULL_SYSTEM
void invoke(ExecContext * xc);
#endif
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
};
class InternalProcessorError : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
bool isMachineCheckFault() {return true;}
};
class MemAddressNotAligned : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
bool isAlignmentFault() {return true;}
};
static inline Fault genMachineCheckFault()
{
return new InternalProcessorError;
}
static inline Fault genAlignmentFault()
{
return new MemAddressNotAligned;
}
class PowerOnReset : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class WatchDogReset : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class ExternallyInitiatedReset : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class SoftwareInitiatedReset : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class REDStateException : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class InstructionAccessException : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class InstructionAccessMMUMiss : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class InstructionAccessError : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class IllegalInstruction : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class PrivelegedOpcode : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class UnimplementedLDD : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class UnimplementedSTD : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class FpDisabled : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class FpExceptionIEEE754 : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class FpExceptionOther : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class TagOverflow : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class DivisionByZero : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class DataAccessException : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class DataAccessMMUMiss : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class DataAccessError : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class DataAccessProtection : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class LDDFMemAddressNotAligned : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class STDFMemAddressNotAligned : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class PrivelegedAction : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class LDQFMemAddressNotAligned : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class STQFMemAddressNotAligned : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class AsyncDataError : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
public:
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class EnumeratedFault : public SparcFault
{
protected:
uint32_t _n;
virtual TrapType baseTrapType() = 0;
public:
EnumeratedFault(uint32_t n) : SparcFault() {_n = n;}
TrapType trapType() {return baseTrapType() + _n;}
};
class CleanWindow : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultPriority _priority;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
CleanWindow(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class InterruptLevelN : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
InterruptLevelN(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return 32 - _n;}
FaultStat & countStat() {return _count;}
};
class SpillNNormal : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultPriority _priority;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
SpillNNormal(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class SpillNOther : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultPriority _priority;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
SpillNOther(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class FillNNormal : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultPriority _priority;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
FillNNormal(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class FillNOther : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultPriority _priority;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
FillNOther(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
class TrapInstruction : public EnumeratedFault
{
private:
static FaultName _name;
static TrapType _baseTrapType;
static FaultPriority _priority;
static FaultStat _count;
TrapType baseTrapType() {return _baseTrapType;}
public:
TrapInstruction(uint32_t n) : EnumeratedFault(n) {;}
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
};
} // SparcISA namespace
#endif // __FAULTS_HH__

129
arch/sparc/isa/base.isa Normal file
View file

@ -0,0 +1,129 @@
////////////////////////////////////////////////////////////////////
//
// Base class for sparc instructions, and some support functions
//
output header {{
struct condCodes
{
uint8_t c:1;
uint8_t v:1;
uint8_t z:1;
uint8_t n:1;
}
enum condTest
{
Always=0x8,
Never=0x0,
NotEqual=0x9,
Equal=0x1,
Greater=0xA,
LessOrEqual=0x2,
GreaterOrEqual=0xB,
Less=0x3,
GreaterUnsigned=0xC,
LessOrEqualUnsigned=0x4,
CarryClear=0xD,
CarrySet=0x5,
Positive=0xE,
Negative=0x6,
OverflowClear=0xF,
OverflowSet=0x7
}
/**
* Base class for all SPARC static instructions.
*/
class SparcStaticInst : public StaticInst
{
protected:
// Constructor.
SparcStaticInst(const char *mnem,
MachInst _machInst, OpClass __opClass)
: StaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
bool passesCondition(condCodes codes, condTest condition);
}};
output decoder {{
std::string SparcStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if(_numSrcRegs > 0)
{
printReg(ss, _srcRegIdx[0]);
}
if(_numSrcRegs > 1)
{
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
// just print the first dest... if there's a second one,
// it's generally implicit
if(_numDestRegs > 0)
{
if(_numSrcRegs > 0)
ss << ",";
printReg(ss, _destRegIdx[0]);
}
return ss.str();
}
bool passesCondition(condCodes codes, condTest condition)
{
switch(condition)
{
case Always:
return true;
case Never:
return false;
case NotEqual:
return !codes.z;
case Equal:
return codes.z;
case Greater:
return !(codes.z | (codes.n ^ codes.v));
case LessOrEqual:
return codes.z | (codes.n ^ codes.v);
case GreaterOrEqual:
return !(codes.n ^ codes.v);
case Less:
return (codes.n ^ codes.v);
case GreaterUnsigned:
return !(codes.c | codes.z);
case LessOrEqualUnsigned:
return (codes.c | codes.z);
case CarryClear:
return !codes.c;
case CarrySet:
return codes.c;
case Positive:
return !codes.n;
case Negative:
return codes.n;
case OverflowClear:
return !codes.v;
case OverflowSet:
return codes.v;
}
}
}};

50
arch/sparc/isa/bitfields.isa Normal file
View file

@ -0,0 +1,50 @@
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
// Bitfields are shared liberally between instruction formats, so they are
// simply defined alphabetically
def bitfield A <29>;
def bitfield CC02 <20>;
def bitfield CC03 <25>;
def bitfield CC04 <11>;
def bitfield CC12 <21>;
def bitfield CC13 <26>;
def bitfield CC14 <12>;
def bitfield CC2 <18>;
def bitfield CMASK <6:4>;
def bitfield COND2 <28:25>;
def bitfield COND4 <17:14>;
def bitfield D16HI <21:20>;
def bitfield D16LO <13:0>;
def bitfield DISP19 <18:0>;
def bitfield DISP22 <21:0>;
def bitfield DISP30 <29:0>;
def bitfield FCN <29:26>;
def bitfield I <13>;
def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>;
def bitfield MMASK <3:0>;
def bitfield OP <31:30>;
def bitfield OP2 <24:22>;
def bitfield OP3 <24:19>;
def bitfield OPF <13:5>;
def bitfield OPF_CC <13:11>;
def bitfield OPF_LOW5 <9:5>;
def bitfield OPF_LOW6 <10:5>;
def bitfield P <19>;
def bitfield RCOND2 <27:25>;
def bitfield RCOND3 <12:10>;
def bitfield RCOND4 <12:10>;
def bitfield RD <29:25>;
def bitfield RS1 <18:14>;
def bitfield RS2 <4:0>;
def bitfield SHCNT32 <4:0>;
def bitfield SHCNT64 <5:0>;
def bitfield SIMM10 <9:0>;
def bitfield SIMM11 <10:0>;
def bitfield SIMM13 <12:0>;
def bitfield SW_TRAP <6:0>;
def bitfield X <12>;

662
arch/sparc/isa/decoder.isa Normal file
View file

@ -0,0 +1,662 @@
////////////////////////////////////////////////////////////////////
//
// The actual decoder specification
//
decode OP default Trap::unknown({{IllegalInstruction}}) {
0x0: decode OP2 {
0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP
0x1: Branch::bpcc({{
switch((CC12 << 1) | CC02)
{
case 1:
case 3:
fault = new IllegalInstruction;
case 0:
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
;//branchHere
break;
case 2:
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
;//branchHere
break;
}
}});//BPcc
0x2: Branch::bicc({{
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
;//branchHere
}});//Bicc
0x3: Branch::bpr({{
switch(RCOND)
{
case 0:
case 4:
fault = new IllegalInstruction;
case 1:
if(Rs1 == 0)
;//branchHere
break;
case 2:
if(Rs1 <= 0)
;//branchHere
break;
case 3:
if(Rs1 < 0)
;//branchHere
break;
case 5:
if(Rs1 != 0)
;//branchHere
break;
case 6:
if(Rs1 > 0)
;//branchHere
break;
case 7:
if(Rs1 >= 0)
;//branchHere
break;
}
}}); //BPr
//SETHI (or NOP if rd == 0 and imm == 0)
0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc
}
0x1: Branch::call({{
//branch here
Rd = xc->pc;
}});
0x2: decode OP3 {
format IntegerOp {
0x00: add({{
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
Rd = Rs1.sdw + val2;
}});//ADD
0x01: and({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = Rs1.udw & val2;
}});//AND
0x02: or({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = Rs1.udw | val2;
}});//OR
0x03: xor({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = Rs1.udw ^ val2;
}});//XOR
0x04: sub({{
int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
Rd = Rs1.sdw + val2;
}});//SUB
0x05: andn({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = Rs1.udw & ~val2;
}});//ANDN
0x06: orn({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = Rs1.udw | ~val2;
}});//ORN
0x07: xnor({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = ~(Rs1.udw ^ val2);
}});//XNOR
0x08: addc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
Rd = Rs1.sdw + val2 + carryin;
}});//ADDC
0x09: mulx({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = Rs1 * val2;
}});//MULX
0x0A: umul({{
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
}});//UMUL
0x0B: smul({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
}});//SMUL
0x0C: subc({{
int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
Rd.sdw = Rs1.sdw + val2 + carryin;
}});//SUBC
0x0D: udivx({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
if(val2 == 0) throw division_by_zero;
Rd.udw = Rs1.udw / val2;
}});//UDIVX
0x0E: udiv({{
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
if(val2 == 0)
fault = new DivisionByZero;
resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32)
| Rs1.udw<31:0>) / val2;
int32_t overflow = (resTemp<63:32> != 0);
if(overflow)
rd.udw = resTemp = 0xFFFFFFFF;
else
rd.udw = resTemp;
}}); //UDIV
0x0F: sdiv({{
int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
if(val2 == 0)
fault = new DivisionByZero;
Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) |
Rs1.sdw<31:0>) / val2;
resTemp = Rd.sdw;
int32_t overflow = (resTemp<63:31> != 0);
int32_t underflow =
(resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
if(overflow)
rd.udw = resTemp = 0x7FFFFFFF;
else if(underflow)
rd.udw = resTemp = 0xFFFFFFFF80000000;
else
rd.udw = resTemp;
}});//SDIV
}
format IntegerOpCc {
0x10: addcc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//ADDcc
0x11: andcc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = Rs1 & val2;}},
{{0}},{{0}},{{0}},{{0}});//ANDcc
0x12: orcc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = Rs1 | val2;}},
{{0}},{{0}},{{0}},{{0}});//ORcc
0x13: xorcc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = Rs1 ^ val2;}},
{{0}},{{0}},{{0}},{{0}});//XORcc
0x14: subcc({{
int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 - val2;}},
{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (~val2) >> 1) +
((Rs1 | ~val2) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);//SUBcc
0x15: andncc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = Rs1 & ~val2;}},
{{0}},{{0}},{{0}},{{0}});//ANDNcc
0x16: orncc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = Rs1 | ~val2;}},
{{0}},{{0}},{{0}},{{0}});//ORNcc
0x17: xnorcc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2);
Rd = ~(Rs1 ^ val2);}},
{{0}},{{0}},{{0}},{{0}});//XNORcc
0x18: addccc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
Rd = resTemp = Rs1 + val2 + carryin;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
+ carryin)}},
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (val2 >> 1) +
((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//ADDCcc
0x1A: umulcc({{
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}},
{{0}},{{0}},{{0}},{{0}});//UMULcc
0x1B: smulcc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
,{{0}},{{0}},{{0}},{{0}});//SMULcc
0x1C: subccc({{
int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);//SUBCcc
0x1D: udivxcc({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
if(val2 == 0) throw division_by_zero;
Rd.udw = Rs1.udw / val2;}}
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
0x1E: udivcc({{
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
if(val2 == 0) throw division_by_zero;
resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
int32_t overflow = (resTemp<63:32> != 0);
if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
else rd.udw = resTemp;}},
{{0}},
{{overflow}},
{{0}},
{{0}}
);//UDIVcc
0x1F: sdivcc({{
int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
if(val2 == 0) throw division_by_zero;
Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
int32_t overflow = (resTemp<63:31> != 0);
int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
else rd.udw = resTemp;}},
{{0}},
{{overflow || underflow}},
{{0}},
{{0}}
);//SDIVcc
0x20: taddcc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TADDcc
0x21: tsubcc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TSUBcc
0x22: taddcctv({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) throw tag_overflow;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TADDccTV
0x23: tsubcctv({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) throw tag_overflow;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TSUBccTV
0x24: mulscc({{
int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
int32_t multiplier = Rs1<31:0>;
int32_t savedLSB = Rs1<0:>;
multiplier = multipler<31:1> |
((xc->regs.MiscRegs.ccrFields.iccFields.n
^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
if(!xc->regs.MiscRegs.yFields.value<0:>)
multiplicand = 0;
Rd = resTemp = multiplicand + multiplier;
xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
);//MULScc
}
format IntegerOp
{
0x25: decode X {
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
}
0x26: decode X {
0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
}
0x27: decode X {
0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
}
0x28: decode RS1 {
0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
0x4: rdtick({{
if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
xc->regs.MiscRegs.tickFields.npt == 1)
throw privileged_action;
Rd = xc->regs.MiscRegs.tick;
}});//RDTICK
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
0xF: decode I {
0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
}
}
0x2A: decode RS1 {
0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
}
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
0x2C: movcc({{
ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
switch(ccBank)
{
case 0: case 1: case 2: case 3:
throw fp_disabled;
break;
case 5: case 7:
throw illegal_instruction;
break;
case 4:
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
Rd = (I ? SIMM11.sdw : RS2);
break;
case 6:
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
Rd = (I ? SIMM11.sdw : RS2);
break;
}
}});//MOVcc
0x2D: sdivx({{
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
if(val2 == 0) throw division_by_zero;
Rd.sdw = Rs1.sdw / val2;
}});//SDIVX
0x2E: decode RS1 {
0x0: IntegerOp::popc({{
int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
for(unsigned int x = 0; x < 16; x++)
{
count += oneBits[val2 & 0xF];
val2 >> 4;
}
}});//POPC
}
0x2F: movr({{
uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
switch(RCOND)
{
case 0: case 4:
throw illegal_instruction;
break;
case 1:
if(Rs1 == 0) Rd = val2;
break;
case 2:
if(Rs1 <= 0) Rd = val2;
break;
case 3:
if(Rs1 = 0) Rd = val2;
break;
case 5:
if(Rs1 != 0) Rd = val2;
break;
case 6:
if(Rs1 > 0) Rd = val2;
break;
case 7:
if(Rs1 >= 0) Rd = val2;
break;
}
}});//MOVR
0x30: decode RD {
0x0: wry({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.y = Rs1 ^ val2;
}});//WRY
0x2: wrccr({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.ccr = Rs1 ^ val2;
}});//WRCCR
0x3: wrasi({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.asi = Rs1 ^ val2;
}});//WRASI
0x6: wrfprs({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.asi = Rs1 ^ val2;
}});//WRFPRS
0xF: Trap::sir({{software_initiated_reset}}); //SIR
}
0x31: decode FCN {
0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
}
0x32: decode RD {
0x0: wrprtpc({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
}});
0x1: wrprtnpc({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
}});
0x2: wrprtstate({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
}});
0x3: wrprtt({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
}});
0x4: wrprtick({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tick = Rs1 ^ val2;
}});
0x5: wrprtba({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tba = Rs1 ^ val2;
}});
0x6: wrprpstate({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.pstate = Rs1 ^ val2;
}});
0x7: wrprtl({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tl = Rs1 ^ val2;
}});
0x8: wrprpil({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.pil = Rs1 ^ val2;
}});
0x9: wrprcwp({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.cwp = Rs1 ^ val2;
}});
0xA: wrprcansave({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.cansave = Rs1 ^ val2;
}});
0xB: wrprcanrestore({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
}});
0xC: wrprcleanwin({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
}});
0xD: wrprotherwin({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
}});
0xE: wrprwstate({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.wstate = Rs1 ^ val2;
}});
}
0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
0x38: Branch::jmpl({{//Stuff}}); //JMPL
0x39: Branch::return({{//Other Stuff}}); //RETURN
0x3A: Trap::tcc({{
switch((CC14 << 1) | (CC04 << 0))
{
case 1: case 3:
throw illegal_instruction;
case 0:
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
throw trap_instruction;
break;
case 2:
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
throw trap_instruction;
break;
}
}}); //Tcc
0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
0x3C: BasicOperate::save({{//leprechauns); //SAVE
0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
0x3E: decode FCN {
0x1: BasicOperate::done({{//Done thing}}); //DONE
0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
}
}
}
0x3: decode OP3 {
format Mem {
0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
0x03: ldd({{
uint64_t val = Mem.udw;
setIntReg(RD & (~1), val<31:0>);
setIntReg(RD | 1, val<63:32>);
}});//LDD
0x04: stw({{Mem.sw = Rd.sw;}}); //STW
0x05: stb({{Mem.sb = Rd.sb;}}); //STB
0x06: sth({{Mem.shw = Rd.shw;}}); //STH
0x07: std({{
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
}});//STD
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
0x0D: ldstub({{
Rd.ub = Mem.ub;
Mem.ub = 0xFF;
}}); //LDSTUB
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
0x0F: swap({{
uint32_t temp = Rd.uw;
Rd.uw = Mem.uw;
Mem.uw = temp;
}}); //SWAP
0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
0x13: ldda({{
uint64_t val = Mem.udw;
setIntReg(RD & (~1), val<31:0>);
setIntReg(RD | 1, val<63:32>);
}}); //LDDA
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
0x17: stda({{
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
}}); //STDA
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
0x1D: ldstuba({{
Rd.ub = Mem.ub;
Mem.ub = 0xFF;
}}); //LDSTUBA
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
0x1F: swapa({{
uint32_t temp = Rd.uw;
Rd.uw = Mem.uw;
Mem.uw = temp;
}}); //SWAPA
0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
0x21: decode X {
0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
}
0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
0x24: Trap::stf({{throw fp_disabled;}}); //STF
0x25: decode X {
0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
}
0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
0x2D: Noop::prefetch({{ }}); //PREFETCH
0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
0x3C: Cas::casa(
{{uint64_t val = Mem.uw;
if(Rs2.uw == val)
Mem.uw = Rd.uw;
Rd.uw = val;
}}); //CASA
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
0x3E: Cas::casxa(
{{uint64_t val = Mem.udw;
if(Rs2 == val)
Mem.udw = Rd;
Rd = val;
}}); //CASXA
}
}
}

19
arch/sparc/isa/formats.isa Normal file
View file

@ -0,0 +1,19 @@
//Include the basic format
//Templates from this format are used later
##include "m5/arch/sparc/isa/formats/basic.isa"
//Include the integerOp and integerOpCc format
##include "m5/arch/sparc/isa/formats/integerop.isa"
//Include the mem format
##include "m5/arch/sparc/isa/formats/mem.isa"
//Include the trap format
##include "m5/arch/sparc/isa/formats/trap.isa"
//Include the branch format
##include "m5/arch/sparc/isa/formats/branch.isa"
//Include the noop format
##include "m5/arch/sparc/isa/formats/noop.isa"

68
arch/sparc/isa/formats/basic.isa Normal file
View file

@ -0,0 +1,68 @@
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
def template BasicDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
// Constructor.
%(class_name)s(MachInst machInst);
%(BasicExecDeclare)s
};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
inline %(class_name)s::%(class_name)s(MachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
}
}};
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
// Basic decode template.
def template BasicDecode {{
return new %(class_name)s(machInst);
}};
// Basic decode template, passing mnemonic in as string arg to constructor.
def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst',
CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

62
arch/sparc/isa/formats/branch.isa Normal file
View file

@ -0,0 +1,62 @@
////////////////////////////////////////////////////////////////////
//
// Branch instructions
//
output header {{
/**
* Base class for integer operations.
*/
class Branch : public SparcStaticInst
{
protected:
// Constructor
Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Branch instruction\n";
}
}};
def template BranchExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//Attempt to execute the instruction
Fault fault = NoFault;
checkPriv;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if(fault == NoFault)
{
//Write the resulting state to the execution context
%(op_wb)s;
}
return fault;
}
}};
// Primary format for integer operate instructions:
def format Branch(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = BranchExecute.subst(iop)
}};

112
arch/sparc/isa/formats/integerop.isa Normal file
View file

@ -0,0 +1,112 @@
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//
output header {{
/**
* Base class for integer operations.
*/
class IntegerOp : public SparcStaticInst
{
protected:
// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string IntegerOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Integer instruction\n";
}
}};
def template IntegerExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//These are set to constants when the execute method
//is generated
bool useCc = ;
bool checkPriv = ;
//Attempt to execute the instruction
try
{
checkPriv;
%(op_decl)s;
%(op_rd)s;
%(code)s;
}
//If we have an exception for some reason,
//deal with it
catch(SparcException except)
{
//Deal with exception
return No_Fault;
}
//Write the resulting state to the execution context
%(op_wb)s;
if(useCc)
{
xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
}
return No_Fault;
}
}};
// Primary format for integer operate instructions:
def format IntegerOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
('xvValue', '0'), ('xcValue', '0')):
code.replace(marker, value)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = IntegerExecute.subst(iop)
}};
// Primary format for integer operate instructions:
def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
('xvValue', xvValue), ('xcValue', xcValue)):
code.replace(marker, value)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = IntegerExecute.subst(iop)
}};

73
arch/sparc/isa/formats/mem.isa Normal file
View file

@ -0,0 +1,73 @@
////////////////////////////////////////////////////////////////////
//
// Mem instructions
//
output header {{
/**
* Base class for integer operations.
*/
class Mem : public SparcStaticInst
{
protected:
// Constructor
Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Memory instruction\n";
}
}};
def template MemExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
ea_code
%(code)s;
if(fault == NoFault)
{
//Write the resulting state to the execution context
%(op_wb)s;
}
return fault;
}
}};
// Primary format for integer operate instructions:
def format Mem(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = MemExecute.subst(iop)
exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
}};
def format Cas(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = MemExecute.subst(iop)
exec_output.replace('ea_code', 'EA = R1;');
}};

50
arch/sparc/isa/formats/noop.isa Normal file
View file

@ -0,0 +1,50 @@
////////////////////////////////////////////////////////////////////
//
// Noop instruction
//
output header {{
/**
* Noop class.
*/
class Noop : public SparcStaticInst
{
protected:
// Constructor
Noop(const char *mnem, MachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Noop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Noop\n";
}
}};
def template NoopExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//Nothing to see here, move along
return NoFault;
}
}};
// Primary format for integer operate instructions:
def format Noop(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = NoopExecute.subst(iop)
}};

51
arch/sparc/isa/formats/trap.isa Normal file
View file

@ -0,0 +1,51 @@
////////////////////////////////////////////////////////////////////
//
// Trap instructions
//
output header {{
/**
* Base class for integer operations.
*/
class Trap : public SparcStaticInst
{
protected:
// Constructor
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Trap::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Trap instruction\n";
}
}};
def template TrapExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//TODO: set up a software fault and return it.
return NoFault;
}
}};
// Primary format for integer operate instructions:
def format Trap(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = TrapExecute.subst(iop)
}};

43
arch/sparc/isa/includes.isa Normal file
View file

@ -0,0 +1,43 @@
////////////////////////////////////////////////////////////////////
//
// Output include file directives.
//
output header {{
#include <sstream>
#include <iostream>
#include <iomanip>
#include "cpu/static_inst.hh"
#include "arch/sparc/faults.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
#include "arch/sparc/isa_traits.hh"
}};
output decoder {{
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif
using namespace SparcISA;
}};
output exec {{
#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif
#ifdef FULL_SYSTEM
//#include "arch/alpha/pseudo_inst.hh"
#endif
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
}};

52
arch/sparc/isa/main.isa Normal file
View file

@ -0,0 +1,52 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
##include "m5/arch/sparc/isa/includes.isa"
////////////////////////////////////////////////////////////////////
//
// Namespace statement. Everything below this line will be in the
// SparcISAInst namespace.
//
namespace SparcISA;
//Include the bitfield definitions
##include "m5/arch/sparc/isa/bitfields.isa"
//Include the operand_types and operand definitions
##include "m5/arch/sparc/isa/operands.isa"
//Include the base class for sparc instructions, and some support code
##include "m5/arch/sparc/isa/base.isa"
//Include the definitions for the instruction formats
##include "m5/arch/sparc/isa/formats.isa"
//Include the decoder definition
##include "m5/arch/sparc/isa/decoder.isa"

31
arch/sparc/isa/operands.isa Normal file
View file

@ -0,0 +1,31 @@
def operand_types {{
'sb' : ('signed int', 8),
'ub' : ('unsigned int', 8),
'shw' : ('signed int', 16),
'uhw' : ('unsigned int', 16),
'sw' : ('signed int', 32),
'uw' : ('unsigned int', 32),
'sdw' : ('signed int', 64),
'udw' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64),
'qf' : ('float', 128)
}};
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 1),
'R16': ('IntReg', 'udw', '16', None, 1)
}};

527
arch/sparc/isa_traits.hh Normal file
View file

@ -0,0 +1,527 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
#define __ARCH_SPARC_ISA_TRAITS_HH__
#include "arch/sparc/faults.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
//This makes sure the big endian versions of certain functions are used.
namespace BigEndianGuest {}
using namespace BigEndianGuest;
class ExecContext;
class FastCPU;
//class FullCPU;
class Checkpoint;
#define TARGET_SPARC
class StaticInst;
class StaticInstPtr;
//namespace EV5
//{
// int DTB_ASN_ASN(uint64_t reg);
// int ITB_ASN_ASN(uint64_t reg);
//}
namespace SparcISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
const int NumFloatRegs = 32;
const int NumMiscRegs = 32;
const int // Maximum trap level
const int MaxTL = 4;
const int
const int // semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
const int // the rest of these depend on the ABI
const int StackPointerReg = 14;
const int ReturnAddressReg = 31; // post call, precall is 15
const int ReturnValueReg = 8; // Post return, 24 is pre-return.
const int FramePointerReg = 30;
const int ArgumentReg0 = 8;
const int ArgumentReg1 = 9;
const int ArgumentReg2 = 10;
const int ArgumentReg3 = 11;
const int ArgumentReg4 = 12;
const int ArgumentReg5 = 13;
// Some OS syscall sue a second register (o1) to return a second value
const int SyscallPseudoReturnReg = ArgumentReg1;
//8K. This value is implmentation specific; and should probably
//be somewhere else.
const int LogVMPageSize = 13;
const int VMPageSize = (1 << LogVMPageSize);
typedef uint64_t IntReg;
class IntRegFile
{
private:
//For right now, let's pretend the register file is static
IntReg regs[32];
public:
IntReg & operator [] (RegIndex index)
{
//Don't allow indexes outside of the 32 registers
index &= 0x1F;
return regs[index];
}
};
void serialize(std::ostream & os);
void unserialize(Checkpoint *cp, const std::string &section);
typedef float float32_t;
typedef double float64_t;
//FIXME This actually usually refers to a 10 byte float, rather than a
//16 byte float as required. This data type may have to be emulated.
typedef long double float128_t;
class FloatRegFile
{
private:
//By using the largest data type, we ensure everything
//is aligned correctly in memory
union
{
float128_t rawRegs[16];
uint64_t regDump[32];
};
class QuadRegs
{
private:
FloatRegFile * parent;
public:
QuadRegs(FloatRegFile * p) : parent(p) {;}
float128_t & operator [] (RegIndex index)
{
//Quad floats are index by the single
//precision register the start on,
//and only 16 should be accessed
index = (index >> 2) & 0xF;
return parent->rawRegs[index];
}
};
class DoubleRegs
{
private:
FloatRegFile * parent;
public:
DoubleRegs(FloatRegFile * p) : parent(p) {;}
float64_t & operator [] (RegIndex index)
{
//Double floats are index by the single
//precision register the start on,
//and only 32 should be accessed
index = (index >> 1) & 0x1F;
return ((float64_t *)parent->rawRegs)[index];
}
};
class SingleRegs
{
private:
FloatRegFile * parent;
public:
SingleRegs(FloatRegFile * p) : parent(p) {;}
float32_t & operator [] (RegIndex index)
{
//Only 32 single floats should be accessed
index &= 0x1F;
return ((float32_t *)parent->rawRegs)[index];
}
};
public:
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, std::string & section);
QuadRegs quadRegs;
DoubleRegs doubleRegs;
SingleRegs singleRegs;
FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
{;}
};
// control register file contents
typedef uint64_t MiscReg;
// The control registers, broken out into fields
class MiscRegFile
{
private:
union
{
uint16_t pstate; // Process State Register
struct
{
uint16_t ag:1; // Alternate Globals
uint16_t ie:1; // Interrupt enable
uint16_t priv:1; // Privelege mode
uint16_t am:1; // Address mask
uint16_t pef:1; // PSTATE enable floating-point
uint16_t red:1; // RED (reset, error, debug) state
uint16_t mm:2; // Memory Model
uint16_t tle:1; // Trap little-endian
uint16_t cle:1; // Current little-endian
} pstateFields;
};
uint64_t tba; // Trap Base Address
union
{
uint64_t y; // Y (used in obsolete multiplication)
struct
{
uint64_t value:32; // The actual value stored in y
uint64_t :32; // reserved bits
} yFields;
};
uint8_t pil; // Process Interrupt Register
uint8_t cwp; // Current Window Pointer
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
// on the previous level)
union
{
uint8_t ccr; // Condition Code Register
struct
{
union
{
uint8_t icc:4; // 32-bit condition codes
struct
{
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} iccFields;
};
union
{
uint8_t xcc:4; // 64-bit condition codes
struct
{
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} xccFields;
};
} ccrFields;
};
uint8_t asi; // Address Space Identifier
uint8_t tl; // Trap Level
uint64_t tpc[MaxTL]; // Trap Program Counter (value from
// previous trap level)
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
// previous trap level)
union
{
uint64_t tstate[MaxTL]; // Trap State
struct
{
//Values are from previous trap level
uint64_t cwp:5; // Current Window Pointer
uint64_t :2; // Reserved bits
uint64_t pstate:10; // Process State
uint64_t :6; // Reserved bits
uint64_t asi:8; // Address Space Identifier
uint64_t ccr:8; // Condition Code Register
} tstateFields[MaxTL];
};
union
{
uint64_t tick; // Hardware clock-tick counter
struct
{
uint64_t counter:63; // Clock-tick count
uint64_t npt:1; // Non-priveleged trap
} tickFields;
};
uint8_t cansave; // Savable windows
uint8_t canrestore; // Restorable windows
uint8_t otherwin; // Other windows
uint8_t cleanwin; // Clean windows
union
{
uint8_t wstate; // Window State
struct
{
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
// register window trap
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
// register window trap
} wstateFields;
};
union
{
uint64_t ver; // Version
struct
{
uint64_t maxwin:5; // Max CWP value
uint64_t :2; // Reserved bits
uint64_t maxtl:8; // Maximum trap level
uint64_t :8; // Reserved bits
uint64_t mask:8; // Processor mask set revision number
uint64_t impl:16; // Implementation identification number
uint64_t manuf:16; // Manufacturer code
} verFields;
};
union
{
uint64_t fsr; // Floating-Point State Register
struct
{
union
{
uint64_t cexc:5; // Current excpetion
struct
{
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} cexecFields;
};
union
{
uint64_t aexc:5; // Accrued exception
struct
{
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} aexecFields;
};
uint64_t fcc0:2; // Floating-Point condtion codes
uint64_t :1; // Reserved bits
uint64_t qne:1; // Deferred trap queue not empty
// with no queue, it should read 0
uint64_t ftt:3; // Floating-Point trap type
uint64_t ver:3; // Version (of the FPU)
uint64_t :2; // Reserved bits
uint64_t ns:1; // Nonstandard floating point
union
{
uint64_t tem:5; // Trap Enable Mask
struct
{
uint64_t nxm:1; // Inexact
uint64_t dzm:1; // Divide by zero
uint64_t ufm:1; // Underflow
uint64_t ofm:1; // Overflow
uint64_t nvm:1; // Invalid operand
} temFields;
};
uint64_t :2; // Reserved bits
uint64_t rd:2; // Rounding direction
uint64_t fcc1:2; // Floating-Point condition codes
uint64_t fcc2:2; // Floating-Point condition codes
uint64_t fcc3:2; // Floating-Point condition codes
uint64_t :26; // Reserved bits
} fsrFields;
};
union
{
uint8_t fprs; // Floating-Point Register State
struct
{
uint8_t dl:1; // Dirty lower
uint8_t du:1; // Dirty upper
uint8_t fef:1; // FPRS enable floating-Point
} fprsFields;
};
public:
MiscReg readReg(int misc_reg);
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
Fault setReg(int misc_reg, const MiscReg &val);
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc);
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, std::string & section);
};
typedef union
{
float32_t singReg;
float64_t doubReg;
float128_t quadReg;
} FloatReg;
typedef union
{
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
} AnyReg;
struct RegFile
{
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegFile; // control register file
Addr pc; // Program Counter
Addr npc; // Next Program Counter
Addr nnpc;
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
StaticInstPtr decodeInst(MachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
// Instruction address compression hooks
inline Addr realPCToFetchPC(const Addr &addr)
{
return addr;
}
inline Addr fetchPCToRealPC(const Addr &addr)
{
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
inline size_t fetchInstSize()
{
return sizeof(MachInst);
}
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
static inline setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
// check for error condition. SPARC syscall convention is to
// indicate success/failure in reg the carry bit of the ccr
// and put the return value itself in the standard return value reg ().
if (return_value.successful()) {
// no error
regs->miscRegFile.ccrFields.iccFields.c = 0;
regs->intRegFile[ReturnValueReg] = return_value.value();
} else {
// got an error, return details
regs->miscRegFile.ccrFields.iccFields.c = 1;
regs->intRegFile[ReturnValueReg] = -return_value.value();
}
}
};
#if !FULL_SYSTEM
class SyscallReturn
{
public:
template <class T>
SyscallReturn(T v, bool s)
{
retval = (uint64_t)v;
success = s;
}
template <class T>
SyscallReturn(T v)
{
success = (v >= 0);
retval = (uint64_t)v;
}
~SyscallReturn() {}
SyscallReturn& operator=(const SyscallReturn& s)
{
retval = s.retval;
success = s.success;
return *this;
}
bool successful() { return success; }
uint64_t value() { return retval; }
private:
uint64_t retval;
bool success;
};
#endif
#if FULL_SYSTEM
#include "arch/alpha/ev5.hh"
#endif
#endif // __ARCH_SPARC_ISA_TRAITS_HH__

374
arch/sparc/linux/process.cc Normal file
View file

@ -0,0 +1,374 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/sparc/common_syscall_emul.hh"
#include "arch/sparc/linux/process.hh"
#include "arch/sparc/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "kern/linux/linux.hh"
#include "mem/functional/functional.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
using namespace std;
using namespace SparcISA;
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->release, "2.4.20");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "sparc");
name.copyOut(xc->mem);
return 0;
}
SyscallDesc SparcLinuxProcess::syscallDescs[] = {
/* 0 */ SyscallDesc("restart_syscall", unimplementedFunc);
/* 1 */ SyscallDesc("exit", exitFunc);
/* 2 */ SyscallDesc("fork", unimplementedFunc);
/* 3 */ SyscallDesc("read", readFunc);
/* 4 */ SyscallDesc("write", writeFunc);
/* 5 */ SyscallDesc("open", openFunc<Linux>);
/* 6 */ SyscallDesc("close", closeFinc);
/* 7 */ SyscallDesc("wait4", unimplementedFunc);
/* 8 */ SyscallDesc("creat", unimplementedFunc);
/* 9 */ SyscallDesc("link", unimplementedFunc);
/* 10 */ SyscallDesc("unlink", unlinkFunc);
/* 11 */ SyscallDesc("execv", unimplementedFunc);
/* 12 */ SyscallDesc("chdir", unimplementedFunc);
/* 13 */ SyscallDesc("chown", chownFunc);
/* 14 */ SyscallDesc("mknod", unimplementedFunc);
/* 15 */ SyscallDesc("chmod", chmodFunc<Linux>);
/* 16 */ SyscallDesc("lchown", unimplementedFunc);
/* 17 */ SyscallDesc("brk", obreakFunc);
/* 18 */ SyscallDesc("perfctr", unimplementedFunc);
/* 19 */ SyscallDesc("lseek", lseekFunc);
/* 20 */ SyscallDesc("getpid", getpidFunc);
/* 21 */ SyscallDesc("capget", unimplementedFunc);
/* 22 */ SyscallDesc("capset", unimplementedFunc);
/* 23 */ SyscallDesc("setuid", setuidFunc);
/* 24 */ SyscallDesc("getuid", getuidFunc);
/* 25 */ SyscallDesc("time", unimplementedFunc);
/* 26 */ SyscallDesc("ptrace", unimplementedFunc);
/* 27 */ SyscallDesc("alarm", unimplementedFunc);
/* 28 */ SyscallDesc("sigaltstack", unimplementedFunc);
/* 29 */ SyscallDesc("pause", unimplementedFunc);
/* 30 */ SyscallDesc("utime", unimplementedFunc);
/* 31 */ SyscallDesc("lchown32", unimplementedFunc);
/* 32 */ SyscallDesc("fchown32", unimplementedFunc);
/* 33 */ SyscallDesc("access", unimplementedFunc);
/* 34 */ SyscallDesc("nice", unimplementedFunc);
/* 35 */ SyscallDesc("chown32", unimplementedFunc);
/* 36 */ SyscallDesc("sync", unimplementedFunc);
/* 37 */ SyscallDesc("kill", unimplementedFunc);
/* 38 */ SyscallDesc("stat", unimplementedFunc);
/* 39 */ SyscallDesc("sendfile", unimplementedFunc);
/* 40 */ SyscallDesc("lstat", unimplementedFunc);
/* 41 */ SyscallDesc("dup", unimplementedFunc);
/* 42 */ SyscallDesc("pipe", pipePseudoFunc);
/* 43 */ SyscallDesc("times", unimplementedFunc);
/* 44 */ SyscallDesc("getuid32", unimplementedFunc);
/* 45 */ SyscallDesc("umount2", unimplementedFunc);
/* 46 */ SyscallDesc("setgid", unimplementedFunc);
/* 47 */ SyscallDesc("getgid", getgidFunc);
/* 48 */ SyscallDesc("signal", unimplementedFunc);
/* 49 */ SyscallDesc("geteuid", geteuidFunc);
/* 50 */ SyscallDesc("getegid", getegidFunc);
/* 51 */ SyscallDesc("acct", unimplementedFunc);
/* 52 */ SyscallDesc("memory_ordering", unimplementedFunc);
/* 53 */ SyscallDesc("getgid32", unimplementedFunc);
/* 54 */ SyscallDesc("ioctl", unimplementedFunc);
/* 55 */ SyscallDesc("reboot", unimplementedFunc);
/* 56 */ SyscallDesc("mmap2", unimplementedFunc);
/* 57 */ SyscallDesc("symlink", unimplementedFunc);
/* 58 */ SyscallDesc("readlink", unimplementedFunc);
/* 59 */ SyscallDesc("execve", unimplementedFunc);
/* 60 */ SyscallDesc("umask", unimplementedFunc);
/* 61 */ SyscallDesc("chroot", unimplementedFunc);
/* 62 */ SyscallDesc("fstat", unimplementedFunc);
/* 63 */ SyscallDesc("fstat64", unimplementedFunc);
/* 64 */ SyscallDesc("getpagesize", unimplementedFunc);
/* 65 */ SyscallDesc("msync", unimplementedFunc);
/* 66 */ SyscallDesc("vfork", unimplementedFunc);
/* 67 */ SyscallDesc("pread64", unimplementedFunc);
/* 68 */ SyscallDesc("pwrite64", unimplementedFunc);
/* 69 */ SyscallDesc("geteuid32", unimplementedFunc);
/* 70 */ SyscallDesc("getdgid32", unimplementedFunc);
/* 71 */ SyscallDesc("mmap", unimplementedFunc);
/* 72 */ SyscallDesc("setreuid32", unimplementedFunc);
/* 73 */ SyscallDesc("munmap", unimplementedFunc);
/* 74 */ SyscallDesc("mprotect", unimplementedFunc);
/* 75 */ SyscallDesc("madvise", unimplementedFunc);
/* 76 */ SyscallDesc("vhangup", unimplementedFunc);
/* 77 */ SyscallDesc("truncate64", unimplementedFunc);
/* 78 */ SyscallDesc("mincore", unimplementedFunc);
/* 79 */ SyscallDesc("getgroups", unimplementedFunc);
/* 80 */ SyscallDesc("setgroups", unimplementedFunc);
/* 81 */ SyscallDesc("getpgrp", unimplementedFunc);
/* 82 */ SyscallDesc("setgroups32", unimplementedFunc);
/* 83 */ SyscallDesc("setitimer", unimplementedFunc);
/* 84 */ SyscallDesc("ftruncate64", unimplementedFunc);
/* 85 */ SyscallDesc("swapon", unimplementedFunc);
/* 86 */ SyscallDesc("getitimer", unimplementedFunc);
/* 87 */ SyscallDesc("setuid32", unimplementedFunc);
/* 88 */ SyscallDesc("sethostname", unimplementedFunc);
/* 89 */ SyscallDesc("setgid32", unimplementedFunc);
/* 90 */ SyscallDesc("dup2", unimplementedFunc);
/* 91 */ SyscallDesc("setfsuid32", unimplementedFunc);
/* 92 */ SyscallDesc("fcntl", unimplementedFunc);
/* 93 */ SyscallDesc("select", unimplementedFunc);
/* 94 */ SyscallDesc("setfsgid32", unimplementedFunc);
/* 95 */ SyscallDesc("fsync", unimplementedFunc);
/* 96 */ SyscallDesc("setpriority", unimplementedFunc);
/* 97 */ SyscallDesc("socket", unimplementedFunc);
/* 98 */ SyscallDesc("connect", unimplementedFunc);
/* 99 */ SyscallDesc("accept", unimplementedFunc);
/* 100 */ SyscallDesc("getpriority", unimplementedFunc);
/* 101 */ SyscallDesc("rt_sigreturn", unimplementedFunc);
/* 102 */ SyscallDesc("rt_sigaction", unimplementedFunc);
/* 103 */ SyscallDesc("rt_sigprocmask", unimplementedFunc);
/* 104 */ SyscallDesc("rt_sigpending", unimplementedFunc);
/* 105 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc);
/* 106 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc);
/* 107 */ SyscallDesc("rt_sigsuspend", unimplementedFunc);
/* 108 */ SyscallDesc("setresuid", unimplementedFunc);
/* 109 */ SyscallDesc("getresuid", unimplementedFunc);
/* 110 */ SyscallDesc("setresgid", unimplementedFunc);
/* 111 */ SyscallDesc("getresgid", unimplementedFunc);
/* 112 */ SyscallDesc("setregid32", unimplementedFunc);
/* 113 */ SyscallDesc("recvmsg", unimplementedFunc);
/* 114 */ SyscallDesc("sendmsg", unimplementedFunc);
/* 115 */ SyscallDesc("getgroups32", unimplementedFunc);
/* 116 */ SyscallDesc("gettimeofday", unimplementedFunc);
/* 117 */ SyscallDesc("getrusage", unimplementedFunc);
/* 118 */ SyscallDesc("getsockopt", unimplementedFunc);
/* 119 */ SyscallDesc("getcwd", unimplementedFunc);
/* 120 */ SyscallDesc("readv", unimplementedFunc);
/* 121 */ SyscallDesc("writev", unimplementedFunc);
/* 122 */ SyscallDesc("settimeofday", unimplementedFunc);
/* 123 */ SyscallDesc("fchown", unimplementedFunc);
/* 124 */ SyscallDesc("fchmod", unimplementedFunc);
/* 125 */ SyscallDesc("recvfrom", unimplementedFunc);
/* 126 */ SyscallDesc("setreuid", unimplementedFunc);
/* 127 */ SyscallDesc("setregid", unimplementedFunc);
/* 128 */ SyscallDesc("rename", unimplementedFunc);
/* 129 */ SyscallDesc("truncate", unimplementedFunc);
/* 130 */ SyscallDesc("ftruncate", unimplementedFunc);
/* 131 */ SyscallDesc("flock", unimplementedFunc);
/* 132 */ SyscallDesc("lstat64", unimplementedFunc);
/* 133 */ SyscallDesc("sendto", unimplementedFunc);
/* 134 */ SyscallDesc("shutdown", unimplementedFunc);
/* 135 */ SyscallDesc("socketpair", unimplementedFunc);
/* 136 */ SyscallDesc("mkdir", unimplementedFunc);
/* 137 */ SyscallDesc("rmdir", unimplementedFunc);
/* 138 */ SyscallDesc("utimes", unimplementedFunc);
/* 139 */ SyscallDesc("stat64", unimplementedFunc);
/* 140 */ SyscallDesc("sendfile64", unimplementedFunc);
/* 141 */ SyscallDesc("getpeername", unimplementedFunc);
/* 142 */ SyscallDesc("futex", unimplementedFunc);
/* 143 */ SyscallDesc("gettid", unimplementedFunc);
/* 144 */ SyscallDesc("getrlimit", unimplementedFunc);
/* 145 */ SyscallDesc("setrlimit", unimplementedFunc);
/* 146 */ SyscallDesc("pivot_root", unimplementedFunc);
/* 147 */ SyscallDesc("prctl", unimplementedFunc);
/* 148 */ SyscallDesc("pciconfig_read", unimplementedFunc);
/* 149 */ SyscallDesc("pciconfig_write", unimplementedFunc);
/* 150 */ SyscallDesc("getsockname", unimplementedFunc);
/* 151 */ SyscallDesc("inotify_init", unimplementedFunc);
/* 152 */ SyscallDesc("inotify_add_watch", unimplementedFunc);
/* 153 */ SyscallDesc("poll", unimplementedFunc);
/* 154 */ SyscallDesc("getdents64", unimplementedFunc);
/* 155 */ SyscallDesc("fcntl64", unimplementedFunc);
/* 156 */ SyscallDesc("inotify_rm_watch", unimplementedFunc);
/* 157 */ SyscallDesc("statfs", unimplementedFunc);
/* 158 */ SyscallDesc("fstatfs", unimplementedFunc);
/* 159 */ SyscallDesc("umount", unimplementedFunc);
/* 160 */ SyscallDesc("sched_set_affinity", unimplementedFunc);
/* 161 */ SyscallDesc("sched_get_affinity", unimplementedFunc);
/* 162 */ SyscallDesc("getdomainname", unimplementedFunc);
/* 163 */ SyscallDesc("setdomainname", unimplementedFunc);
/* 164 */ SyscallDesc("utrap_install", unimplementedFunc);
/* 165 */ SyscallDesc("quotactl", unimplementedFunc);
/* 166 */ SyscallDesc("set_tid_address", unimplementedFunc);
/* 167 */ SyscallDesc("mount", unimplementedFunc);
/* 168 */ SyscallDesc("ustat", unimplementedFunc);
/* 169 */ SyscallDesc("setxattr", unimplementedFunc);
/* 170 */ SyscallDesc("lsetxattr", unimplementedFunc);
/* 171 */ SyscallDesc("fsetxattr", unimplementedFunc);
/* 172 */ SyscallDesc("getxattr", unimplementedFunc);
/* 173 */ SyscallDesc("lgetxattr", unimplementedFunc);
/* 174 */ SyscallDesc("getdents", unimplementedFunc);
/* 175 */ SyscallDesc("setsid", unimplementedFunc);
/* 176 */ SyscallDesc("fchdir", unimplementedFunc);
/* 177 */ SyscallDesc("fgetxattr", unimplementedFunc);
/* 178 */ SyscallDesc("listxattr", unimplementedFunc);
/* 179 */ SyscallDesc("llistxattr", unimplementedFunc);
/* 180 */ SyscallDesc("flistxattr", unimplementedFunc);
/* 181 */ SyscallDesc("removexattr", unimplementedFunc);
/* 182 */ SyscallDesc("lremovexattr", unimplementedFunc);
/* 183 */ SyscallDesc("sigpending", unimplementedFunc);
/* 184 */ SyscallDesc("query_module", unimplementedFunc);
/* 185 */ SyscallDesc("setpgid", unimplementedFunc);
/* 186 */ SyscallDesc("fremovexattr", unimplementedFunc);
/* 187 */ SyscallDesc("tkill", unimplementedFunc);
/* 188 */ SyscallDesc("exit_group", unimplementedFunc);
/* 189 */ SyscallDesc("uname", unameFunc);
/* 190 */ SyscallDesc("init_module", unimplementedFunc);
/* 191 */ SyscallDesc("personality", unimplementedFunc);
/* 192 */ SyscallDesc("remap_file_pages", unimplementedFunc);
/* 193 */ SyscallDesc("epoll_create", unimplementedFunc);
/* 194 */ SyscallDesc("epoll_ctl", unimplementedFunc);
/* 195 */ SyscallDesc("epoll_wait", unimplementedFunc);
/* 196 */ SyscallDesc("ioprio_set", unimplementedFunc);
/* 197 */ SyscallDesc("getppid", getppidFunc);
/* 198 */ SyscallDesc("sigaction", unimplementedFunc);
/* 199 */ SyscallDesc("sgetmask", unimplementedFunc);
/* 200 */ SyscallDesc("ssetmask", unimplementedFunc);
/* 201 */ SyscallDesc("sigsuspend", unimplementedFunc);
/* 202 */ SyscallDesc("oldlstat", unimplementedFunc);
/* 203 */ SyscallDesc("uselib", unimplementedFunc);
/* 204 */ SyscallDesc("readdir", unimplementedFunc);
/* 205 */ SyscallDesc("readahead", unimplementedFunc);
/* 206 */ SyscallDesc("socketcall", unimplementedFunc);
/* 207 */ SyscallDesc("syslog", unimplementedFunc);
/* 208 */ SyscallDesc("lookup_dcookie", unimplementedFunc);
/* 209 */ SyscallDesc("fadvise64", unimplementedFunc);
/* 210 */ SyscallDesc("fadvise64_64", unimplementedFunc);
/* 211 */ SyscallDesc("tgkill", unimplementedFunc);
/* 212 */ SyscallDesc("waitpid", unimplementedFunc);
/* 213 */ SyscallDesc("swapoff", unimplementedFunc);
/* 214 */ SyscallDesc("sysinfo", unimplementedFunc);
/* 215 */ SyscallDesc("ipc", unimplementedFunc);
/* 216 */ SyscallDesc("sigreturn", unimplementedFunc);
/* 217 */ SyscallDesc("clone", unimplementedFunc);
/* 218 */ SyscallDesc("ioprio_get", unimplementedFunc);
/* 219 */ SyscallDesc("adjtimex", unimplementedFunc);
/* 220 */ SyscallDesc("sigprocmask", unimplementedFunc);
/* 221 */ SyscallDesc("create_module", unimplementedFunc);
/* 222 */ SyscallDesc("delete_module", unimplementedFunc);
/* 223 */ SyscallDesc("get_kernel_syms", unimplementedFunc);
/* 224 */ SyscallDesc("getpgid", unimplementedFunc);
/* 225 */ SyscallDesc("bdflush", unimplementedFunc);
/* 226 */ SyscallDesc("sysfs", unimplementedFunc);
/* 227 */ SyscallDesc("afs_syscall", unimplementedFunc);
/* 228 */ SyscallDesc("setfsuid", unimplementedFunc);
/* 229 */ SyscallDesc("setfsgid", unimplementedFunc);
/* 230 */ SyscallDesc("_newselect", unimplementedFunc);
/* 231 */ SyscallDesc("time", unimplementedFunc);
/* 232 */ SyscallDesc("oldstat", unimplementedFunc);
/* 233 */ SyscallDesc("stime", unimplementedFunc);
/* 234 */ SyscallDesc("statfs64", unimplementedFunc);
/* 235 */ SyscallDesc("fstatfs64", unimplementedFunc);
/* 236 */ SyscallDesc("_llseek", unimplementedFunc);
/* 237 */ SyscallDesc("mlock", unimplementedFunc);
/* 238 */ SyscallDesc("munlock", unimplementedFunc);
/* 239 */ SyscallDesc("mlockall", unimplementedFunc);
/* 240 */ SyscallDesc("munlockall", unimplementedFunc);
/* 241 */ SyscallDesc("sched_setparam", unimplementedFunc);
/* 242 */ SyscallDesc("sched_getparam", unimplementedFunc);
/* 243 */ SyscallDesc("sched_setscheduler", unimplementedFunc);
/* 244 */ SyscallDesc("sched_getscheduler", unimplementedFunc);
/* 245 */ SyscallDesc("sched_yield", unimplementedFunc);
/* 246 */ SyscallDesc("sched_get_priority_max", unimplimented);
/* 247 */ SyscallDesc("sched_get_priority_min", unimplimented);
/* 248 */ SyscallDesc("sched_rr_get_interval", unimplimented);
/* 249 */ SyscallDesc("nanosleep", unimplementedFunc);
/* 250 */ SyscallDesc("mremap", unimplementedFunc);
/* 251 */ SyscallDesc("_sysctl", unimplementedFunc);
/* 252 */ SyscallDesc("getsid", unimplementedFunc);
/* 253 */ SyscallDesc("fdatasync", unimplementedFunc);
/* 254 */ SyscallDesc("nfsservctl", unimplementedFunc);
/* 255 */ SyscallDesc("aplib", unimplementedFunc);
/* 256 */ SyscallDesc("clock_settime", unimplementedFunc);
/* 257 */ SyscallDesc("clock_gettime", unimplementedFunc);
/* 258 */ SyscallDesc("clock_getres", unimplementedFunc);
/* 259 */ SyscallDesc("clock_nanosleep", unimplementedFunc);
/* 260 */ SyscallDesc("sched_getaffinity", unimplementedFunc);
/* 261 */ SyscallDesc("sched_setaffinity", unimplementedFunc);
/* 262 */ SyscallDesc("timer_settime", unimplementedFunc);
/* 263 */ SyscallDesc("timer_gettime", unimplementedFunc);
/* 264 */ SyscallDesc("timer_getoverrun", unimplementedFunc);
/* 265 */ SyscallDesc("timer_delete", unimplementedFunc);
/* 266 */ SyscallDesc("timer_create", unimplementedFunc);
/* 267 */ SyscallDesc("vserver", unimplementedFunc);
/* 268 */ SyscallDesc("io_setup", unimplementedFunc);
/* 269 */ SyscallDesc("io_destroy", unimplementedFunc);
/* 270 */ SyscallDesc("io_submit", unimplementedFunc);
/* 271 */ SyscallDesc("io_cancel", unimplementedFunc);
/* 272 */ SyscallDesc("io_getevents", unimplementedFunc);
/* 273 */ SyscallDesc("mq_open", unimplementedFunc);
/* 274 */ SyscallDesc("mq_unlink", unimplementedFunc);
/* 275 */ SyscallDesc("mq_timedsend", unimplementedFunc);
/* 276 */ SyscallDesc("mq_timedreceive", unimplementedFunc);
/* 277 */ SyscallDesc("mq_notify", unimplementedFunc);
/* 278 */ SyscallDesc("mq_getsetattr", unimplementedFunc);
/* 279 */ SyscallDesc("waitid", unimplementedFunc);
/* 280 */ SyscallDesc("sys_setaltroot", unimplementedFunc);
/* 281 */ SyscallDesc("add_key", unimplementedFunc);
/* 282 */ SyscallDesc("request_key", unimplementedFunc);
/* 283 */ SyscallDesc("keyctl", unimplementedFunc);
};
SparcLinuxProcess::SparcLinuxProcess(const std::string &name,
ObjectFile *objFile,
int stdin_fd,
int stdout_fd,
int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp)
: LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
{
// The sparc syscall table must be <= 283 entries because that is all there
// is space for.
assert(Num_Syscall_Descs <= 283);
init_regs->intRegFile[0] = 0;
}
SyscallDesc*
AlphaLinuxProcess::getDesc(int callnum)
{
if (callnum < 0 || callnum > Num_Syscall_Descs)
return NULL;
return &syscallDescs[callnum];
}

58
arch/sparc/linux/process.hh Normal file
View file

@ -0,0 +1,58 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPARC_LINUX_PROCESS_HH__
#define __SPARC_LINUX_PROCESS_HH__
#include "sim/process.hh"
/// A process with emulated SPARC/Linux syscalls.
class SparcLinuxProcess : public LiveProcess
{
public:
/// Constructor.
SparcLinuxProcess(const std::string &name,
ObjectFile *objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp);
virtual SyscallDesc* getDesc(int callnum);
/// The target system's hostname.
static const char *hostname;
/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
const int Num_Syscall_Descs;
};
#endif // __ALPHA_LINUX_PROCESS_HH__

56
arch/sparc/process.cc Normal file
View file

@ -0,0 +1,56 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/sparc/process.hh"
namespace SparcISA
{
LiveProcess *
createProcess(const string &nm, ObjectFile * objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
vector<string> &argv, vector<string> &envp)
{
LiveProcess * process = NULL;
if (objFile->getArch() != ObjectFile::SPARC)
fatal("Object file does not match architecture.");
switch (objFile->getOpSys()) {
case ObjectFile::Linux:
process = new SparcLinuxProcess(nm, objFile,
stdin_fd, stdout_fd, stderr_fd,
argv, envp);
break;
case ObjectFile::Solaris:
default:
fatal("Unknown/unsupported operating system.");
}
return process;
}
} // namespace SparcISA

45
arch/sparc/process.hh Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPARC_PROCESS_HH__
#define __SPARC_PROCESS_HH__
#include "arch/sparc/linux/process.hh"
#include "base/loader/object_file.hh"
namespace SparcISA
{
LiveProcess *
createProcess(const string &nm, ObjectFile * objFile,
int stdin_fd, int stdout_fd, int stderr_fd,
vector<string> &argv, vector<string> &envp);
} // namespace SparcISA
#endif // __SPARC_PROCESS_HH__

119
arch/sparc/stacktrace.hh Normal file
View file

@ -0,0 +1,119 @@
/*
* Copyright (c) 2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ALPHA_STACKTRACE_HH__
#define __ARCH_ALPHA_STACKTRACE_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
class ExecContext;
class StackTrace;
class ProcessInfo
{
private:
ExecContext *xc;
int thread_info_size;
int task_struct_size;
int task_off;
int pid_off;
int name_off;
public:
ProcessInfo(ExecContext *_xc);
Addr task(Addr ksp) const;
int pid(Addr ksp) const;
std::string name(Addr ksp) const;
};
class StackTrace
{
protected:
typedef TheISA::MachInst MachInst;
private:
ExecContext *xc;
std::vector<Addr> stack;
private:
bool isEntry(Addr addr);
bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
bool decodeSave(MachInst inst, int &reg, int &disp);
bool decodeStack(MachInst inst, int &disp);
void trace(ExecContext *xc, bool is_call);
public:
StackTrace();
StackTrace(ExecContext *xc, StaticInstPtr inst);
~StackTrace();
void clear()
{
xc = 0;
stack.clear();
}
bool valid() const { return xc != NULL; }
bool trace(ExecContext *xc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
static const int user = 1;
static const int console = 2;
static const int unknown = 3;
#if TRACING_ON
private:
void dump();
public:
void dprintf() { if (DTRACE(Stack)) dump(); }
#else
public:
void dprintf() {}
#endif
};
inline bool
StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
if (valid())
clear();
trace(xc, !inst->isReturn());
return true;
}
#endif // __ARCH_ALPHA_STACKTRACE_HH__

16
base/intmath.hh
View file

@ -145,22 +145,6 @@ floorLog2(long long x)
return floorLog2((unsigned long long)x);
}
#if defined(__APPLE__)
inline int
floorLog2(size_t x)
{
assert(x > 0);
assert(sizeof(size_t) == 4 || sizeof(size_t) == 8);
// It's my hope that this is optimized away?
if (sizeof(size_t) == 4)
return floorLog2((uint32_t)x);
else if (sizeof(size_t) == 8)
return floorLog2((uint64_t)x);
}
#endif
template <class T>
inline int
ceilLog2(T n)

94
base/loader/elf_object.cc
View file

@ -38,8 +38,8 @@
#define __LIBELF_NEED_LINK_H 0
#define __LIBELF_SYMBOL_VERSIONS 0
#include <libelf/libelf.h>
#include <libelf/gelf.h>
#include "libelf/libelf.h"
#include "libelf/gelf.h"
#include "base/loader/elf_object.hh"
@ -55,6 +55,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
{
Elf *elf;
GElf_Ehdr ehdr;
Arch arch = UnknownArch;
OpSys opSys = UnknownOpSys;
// check that header matches library version
if (elf_version(EV_CURRENT) == EV_NONE)
@ -72,17 +74,87 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
return NULL;
}
else {
if (ehdr.e_ident[EI_CLASS] == ELFCLASS32)
panic("32 bit ELF Binary, Not Supported");
/* @todo this emachine value isn't offical yet.
* so we probably shouldn't check it. */
// if (ehdr.e_machine != EM_ALPHA)
// panic("Non Alpha Binary, Not Supported");
//Detect the architecture
//Versioning issues in libelf need to be resolved to get the correct
//SPARC constants.
//If MIPS supports 32 bit executables, this may need to be changed.
//Also, there are other MIPS constants which may be used, like
//EM_MIPS_RS3_LE and EM_MIPS_X
//Since we don't know how to check for alpha right now, we'll
//just assume if it wasn't something else and it's 64 bit, that's
//what it must be.
if (ehdr.e_machine == EM_SPARC64 ||
ehdr.e_machine == EM_SPARC ||
ehdr.e_machine == EM_SPARCV9) {
arch = ObjectFile::SPARC;
} else if (ehdr.e_machine == EM_MIPS
&& ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = ObjectFile::MIPS;
} else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = ObjectFile::Alpha;
} else {
arch = ObjectFile::UnknownArch;
}
//Detect the operating system
switch (ehdr.e_ident[EI_OSABI])
{
case ELFOSABI_LINUX:
opSys = ObjectFile::Linux;
break;
case ELFOSABI_SOLARIS:
opSys = ObjectFile::Solaris;
break;
case ELFOSABI_TRU64:
opSys = ObjectFile::Tru64;
break;
default:
opSys = ObjectFile::UnknownOpSys;
}
//take a look at the .note.ABI section
//It can let us know what's what.
if (opSys == ObjectFile::UnknownOpSys)
{
Elf_Scn *section;
GElf_Shdr shdr;
Elf_Data *data;
uint32_t osAbi;;
int secIdx = 1;
// Get the first section
section = elf_getscn(elf, secIdx);
// While there are no more sections
while (section != NULL) {
gelf_getshdr(section, &shdr);
if (shdr.sh_type == SHT_NOTE && !strcmp(".note.ABI-tag",
elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name))) {
// we have found a ABI note section
// Check the 5th 32bit word for OS 0 == linux, 1 == hurd,
// 2 == solaris, 3 == freebsd
data = elf_rawdata(section, NULL);
assert(data->d_buf);
if(ehdr.e_ident[EI_DATA] == ELFDATA2LSB)
osAbi = htole(((uint32_t*)data->d_buf)[4]);
else
osAbi = htobe(((uint32_t*)data->d_buf)[4]);
switch(osAbi) {
case 0:
opSys = ObjectFile::Linux;
break;
case 2:
opSys = ObjectFile::Solaris;
break;
}
} // if section found
section = elf_getscn(elf, ++secIdx);
} // while sections
}
elf_end(elf);
return new ElfObject(fname, fd, len, data,
ObjectFile::Alpha, ObjectFile::Linux);
return new ElfObject(fname, fd, len, data, arch, opSys);
}
}

3
base/loader/exec_aout.h
View file

@ -55,6 +55,7 @@
(N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \
N_GETMAGIC(ex) != ZMAGIC)
#include "targetarch/aout_machdep.h"
//Only alpha will be able to load aout for now
#include "arch/alpha/aout_machdep.h"
#endif /* !_SYS_EXEC_AOUT_H_ */

Some files were not shown because too many files have changed in this diff Show more