last changes before big merge
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
set NNPC function
cpu/simple/cpu.cc:
use NNPC in determining what PC we are using
--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
This commit is contained in:
Korey Sewell
parent
9e304ed3e6
commit
a3aae21d03
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@ -200,6 +200,8 @@ extern const int reg_redir[NumIntRegs];
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MiscRegFile miscRegs; // control register file
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Addr pc; // program counter
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Addr npc; // next-cycle program counter
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Addr nnpc;
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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inline int instAsid()
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@ -65,7 +65,7 @@ namespace MipsISA
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NumIntRegs = 32,
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NumFloatRegs = 32,
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NumMiscRegs = 256,
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NumMiscRegs = 258, //account for hi,lo regs
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MaxRegsOfAnyType = 32,
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// Static instruction parameters
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@ -127,8 +127,50 @@ namespace MipsISA
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// cop-0/cop-1 system control register file
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typedef uint64_t MiscReg;
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typedef MiscReg MiscRegFile[NumMiscRegs];
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//typedef MiscReg MiscRegFile[NumMiscRegs];
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class MiscRegFile {
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public:
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MiscReg
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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MiscReg miscRegFile[NumMiscRegs];
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public:
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//These functions should be removed once the simplescalar cpu model
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//has been replaced.
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int getInstAsid();
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int getDataAsid();
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MiscReg readReg(int misc_reg)
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{ return miscRegFile[misc_reg]; }
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MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
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{ return miscRegFile[misc_reg];}
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Fault setReg(int misc_reg, const MiscReg &val)
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{ miscRegFile[misc_reg] = val; return NoFault; }
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Fault setRegWithEffect(int misc_reg, const MiscReg &val,
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ExecContext *xc)
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{ miscRegFile[misc_reg] = val; return NoFault; }
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#if FULL_SYSTEM
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void clearIprs() { };
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protected:
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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private:
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MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
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Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
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#endif
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friend class RegFile;
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};
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enum MiscRegTags {
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//Coprocessor 0 Registers
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@ -207,10 +249,10 @@ namespace MipsISA
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EPC = 105,//105-112 //14-0 Program counter at last exception
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PrId = 113//113-120, //15-0 Processor identification and revision
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PRId = 113//113-120, //15-0 Processor identification and revision
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EBase = 114, //15-1 Exception vector base register
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Config = 121,//121-128
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Config = 121,//Bank 16: 121-128
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Config1 = 122,
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Config2 = 123,
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Config3 = 124,
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@ -218,9 +260,9 @@ namespace MipsISA
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Config7 = 128,
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LLAddr = 129,//129-136
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LLAddr = 129,//Bank 17: 129-136
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WatchLo0 = 137,//137-144
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WatchLo0 = 137,//Bank 18: 137-144
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WatchLo1 = 138,
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WatchLo2 = 139,
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WatchLo3 = 140,
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@ -229,7 +271,7 @@ namespace MipsISA
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WatchLo6 = 143,
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WatchLo7 = 144,
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WatchHi0 = 145,//145-152
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WatchHi0 = 145,//Bank 19: 145-152
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WatchHi1 = 146,
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WatchHi2 = 147,
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WatchHi3 = 148,
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@ -238,21 +280,21 @@ namespace MipsISA
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WatchHi6 = 151,
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WatchHi7 = 152,
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XCContext64 = 153,//153-160
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XCContext64 = 153,//Bank 20: 153-160
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//161-168
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//Bank 21: 161-168
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//169-176
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//Bank 22: 169-176
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Debug = 177, //177-184
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Debug = 177, //Bank 23: 177-184
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TraceControl1 = 178,
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TraceControl2 = 179,
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UserTraceData = 180,
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TraceBPC = 181,
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DEPC = 185,//185-192
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DEPC = 185,//Bank 24: 185-192
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PerfCnt0 = 193,//193 - 200
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PerfCnt0 = 193,//Bank 25: 193 - 200
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PerfCnt1 = 194,
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PerfCnt2 = 195,
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PerfCnt3 = 196,
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@ -261,48 +303,47 @@ namespace MipsISA
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PerfCnt6 = 199,
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PerfCnt7 = 200,
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ErrCtl = 201, //201 - 208
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ErrCtl = 201, //Bank 26: 201 - 208
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CacheErr0 = 209, //209 - 216
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CacheErr0 = 209, //Bank 27: 209 - 216
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CacheErr1 = 210,
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CacheErr2 = 211,
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CacheErr3 = 212,
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TagLo0 = 217,//217 - 224
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TagLo0 = 217,//Bank 28: 217 - 224
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DataLo1 = 218,
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TagLo2 = 219,
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DataLo3 = 220,
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TagLo4 = 221,
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DataLo5 = 222,
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TagLo6 = 223,
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DataLo7 = 234,
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DataLo1 = 226,//225 - 232
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DataLo3 = 228,
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DataLo5 = 220,
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DataLo7 = 232,
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TagHi0 = 233,//233 - 240
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TagHi0 = 233,//Bank 29: 233 - 240
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DataHi1 = 234,
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TagHi2 = 235,
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DataHi3 = 236,
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TagHi4 = 237,
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DataHi5 = 238,
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TagHi6 = 239,
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DataHi7 = 240,
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DataHi0 = 241,//241 - 248
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DataHi2 = 243,
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DataHi4 = 245,
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DataHi6 = 247,
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ErrorEPC = 249,//249 - 256
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ErrorEPC = 249,//Bank 30: 241 - 248
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DESAVE = 257,
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DESAVE = 257,//Bank 31: 249-256
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//More Misc. Regs
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Hi,
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Lo,
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FCSR,
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FPCR,
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LockAddr,
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LockFlag,
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//Alpha Regs, but here now, for
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//compiling sake
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UNIQ
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UNIQ,
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LockAddr,
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LockFlag
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};
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extern const Addr PageShift;
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@ -409,6 +409,7 @@ namespace SparcISA
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Addr pc; // Program Counter
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Addr npc; // Next Program Counter
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Addr nnpc;
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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@ -422,6 +422,12 @@ class ExecContext
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regs.npc = val;
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}
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void setNextNPC(uint64_t val)
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{
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regs.nnpc = val;
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}
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MiscReg readMiscReg(int misc_reg)
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{
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return regs.miscRegs.readReg(misc_reg);
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@ -818,9 +818,17 @@ SimpleCPU::tick()
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#endif // FULL_SYSTEM
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}
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else {
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#if THE_ISA != MIPS_ISA
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// go to the next instruction
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xc->regs.pc = xc->regs.npc;
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xc->regs.npc += sizeof(MachInst);
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#else
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// go to the next instruction
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xc->regs.pc = xc->regs.npc;
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xc->regs.npc = xc->regs.nnpc;
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xc->regs.nnpc += sizeof(MachInst);
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#endif
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}
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#if FULL_SYSTEM
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