Ali Saidi cf94242539 clean up condition codes a little bit ... put back in Tcc code that was deleted in last merge arch/sparc/isa/bitfields.isa: clean up condition codes a little bit --HG-- extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa		2006-03-16 23:09:01 -05:00
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alpha	Merge m5.eecs.umich.edu:/bk/newmem	2006-03-16 14:08:31 -05:00
mips	fix to LiveProcess (this change got deleted somehow)	2006-03-16 19:01:09 -05:00
sparc	clean up condition codes a little bit	2006-03-16 23:09:01 -05:00
isa_parser.py	Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.	2006-03-14 15:55:00 -05:00
isa_specific.hh	Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu	2006-03-14 18:28:51 -05:00
SConscript	Moved registerfile.hh to regfile.hh	2006-03-14 16:05:44 -05:00