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Merge m5.eecs.umich.edu:/bk/newmem

Browse source 
into  ewok.(none):/home/gblack/m5/newmem

arch/sparc/isa/decoder.isa:
    SCCS merged

--HG--
extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0
This commit is contained in:
Gabe Black 2006-03-16 14:08:31 -05:00
commit 1d741c48af
16 changed files with 1010 additions and 761 deletions
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13
arch/alpha/types.hh
View file

@ -38,19 +38,6 @@ namespace AlphaISA
typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 40,
Ctrl_Base_DepTag = 72,
Fpcr_DepTag = 72, // floating point control register
Uniq_DepTag = 73,
Lock_Flag_DepTag = 74,
Lock_Addr_DepTag = 75,
IPR_Base_DepTag = 76
};
typedef uint64_t IntReg;
// floating point register file entry type

16
arch/sparc/faults.cc
View file

@ -89,10 +89,10 @@ TrapType IllegalInstruction::_trapType = 0x010;
FaultPriority IllegalInstruction::_priority = 7;
FaultStat IllegalInstruction::_count;
FaultName PrivelegedOpcode::_name = "priv_opcode";
TrapType PrivelegedOpcode::_trapType = 0x011;
FaultPriority PrivelegedOpcode::_priority = 6;
FaultStat PrivelegedOpcode::_count;
FaultName PrivilegedOpcode::_name = "priv_opcode";
TrapType PrivilegedOpcode::_trapType = 0x011;
FaultPriority PrivilegedOpcode::_priority = 6;
FaultStat PrivilegedOpcode::_count;
FaultName UnimplementedLDD::_name = "unimp_ldd";
TrapType UnimplementedLDD::_trapType = 0x012;
@ -159,10 +159,10 @@ TrapType STDFMemAddressNotAligned::_trapType = 0x036;
FaultPriority STDFMemAddressNotAligned::_priority = 10;
FaultStat STDFMemAddressNotAligned::_count;
FaultName PrivelegedAction::_name = "priv_action";
TrapType PrivelegedAction::_trapType = 0x037;
FaultPriority PrivelegedAction::_priority = 11;
FaultStat PrivelegedAction::_count;
FaultName PrivilegedAction::_name = "priv_action";
TrapType PrivilegedAction::_trapType = 0x037;
FaultPriority PrivilegedAction::_priority = 11;
FaultStat PrivilegedAction::_count;
FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf";
TrapType LDQFMemAddressNotAligned::_trapType = 0x038;

4
arch/sparc/faults.hh
View file

@ -216,7 +216,7 @@ class IllegalInstruction : public SparcFault
FaultStat & countStat() {return _count;}
};
class PrivelegedOpcode : public SparcFault
class PrivilegedOpcode : public SparcFault
{
private:
static FaultName _name;
@ -412,7 +412,7 @@ class STDFMemAddressNotAligned : public SparcFault
FaultStat & countStat() {return _count;}
};
class PrivelegedAction : public SparcFault
class PrivilegedAction : public SparcFault
{
private:
static FaultName _name;

15
arch/sparc/isa/base.isa
View file

@ -48,6 +48,8 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
void printReg(std::ostream &os, int reg) const;
};
bool passesCondition(condCodes codes, condTest condition);
@ -55,6 +57,17 @@ output header {{
output decoder {{
void
SparcStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
}
else {
ccprintf(os, "f%d", reg - FP_Base_DepTag);
}
}
std::string SparcStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
@ -124,6 +137,8 @@ output decoder {{
case OverflowSet:
return codes.v;
}
panic("Tried testing condition nonexistant "
"condition code %d", condition);
}
}};

1290
arch/sparc/isa/decoder.isa
View file

File diff suppressed because it is too large Load diff

11
arch/sparc/isa/formats.isa
View file

@ -5,12 +5,21 @@
//Include the integerOp and integerOpCc format
##include "m5/arch/sparc/isa/formats/integerop.isa"
//Include the mem format
//Include the memory format
##include "m5/arch/sparc/isa/formats/mem.isa"
//Include the compare and swap format
##include "m5/arch/sparc/isa/formats/cas.isa"
//Include the trap format
##include "m5/arch/sparc/isa/formats/trap.isa"
//Include the "unknown" format
##include "m5/arch/sparc/isa/formats/unknown.isa"
//Include the priveleged mode format
##include "m5/arch/sparc/isa/formats/priv.isa"
//Include the branch format
##include "m5/arch/sparc/isa/formats/branch.isa"

3
arch/sparc/isa/formats/branch.isa
View file

@ -34,7 +34,6 @@ def template BranchExecute {{
{
//Attempt to execute the instruction
Fault fault = NoFault;
checkPriv;
%(op_decl)s;
%(op_rd)s;
@ -57,6 +56,6 @@ def format Branch(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop)
}};

75
arch/sparc/isa/formats/integerop.isa
View file

@ -11,13 +11,13 @@ output header {{
{
protected:
// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
IntegerOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
const SymbolTable *symtab) const;
};
}};
@ -25,49 +25,40 @@ output decoder {{
std::string IntegerOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Integer instruction\n";
return "Integer instruction\n";
}
}};
def template IntegerExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//These are set to constants when the execute method
//is generated
bool useCc = ;
bool checkPriv = ;
Fault fault;
//These are set to constants when the execute method
//is generated
bool useCc = ;
//Attempt to execute the instruction
try
{
checkPriv;
%(op_decl)s;
%(op_rd)s;
%(code)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
}
//If we have an exception for some reason,
//deal with it
catch(SparcException except)
{
//Deal with exception
return No_Fault;
}
//Write the resulting state to the execution context
//Write the resulting state to the execution context
if(fault == NoFault)
{
%(op_wb)s;
if(useCc)
{
xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
CcrIccN = Rd & (1 << 63);
CcrIccZ = (Rd == 0);
CcrIccV = ivValue;
CcrIccC = icValue;
CcrXccN = Rd & (1 << 31);
CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
CcrXccV = xvValue;
CcrXccC = xcValue;
}
return No_Fault;
}
return fault;
}
}};
@ -75,19 +66,13 @@ def template IntegerExecute {{
def format IntegerOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
('xvValue', '0'), ('xcValue', '0')):
code.replace(marker, value)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = IntegerExecute.subst(iop)
}};
@ -95,18 +80,12 @@ def format IntegerOp(code, *opt_flags) {{
def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
('xvValue', xvValue), ('xcValue', xcValue)):
code.replace(marker, value)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = IntegerExecute.subst(iop)
}};

15
arch/sparc/isa/formats/mem.isa
View file

@ -12,7 +12,7 @@ output header {{
protected:
// Constructor
Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
@ -56,18 +56,7 @@ def format Mem(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = MemExecute.subst(iop)
exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
}};
def format Cas(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = MemExecute.subst(iop)
exec_output.replace('ea_code', 'EA = R1;');
}};

4
arch/sparc/isa/formats/noop.isa
View file

@ -11,7 +11,7 @@ output header {{
{
protected:
// Constructor
Noop(const char *mnem, MachInst _machInst, OpClass __opClass) :
Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
@ -45,6 +45,6 @@ def format Noop(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = NoopExecute.subst(iop)
}};

172
arch/sparc/isa/formats/priv.isa Normal file
View file

@ -0,0 +1,172 @@
////////////////////////////////////////////////////////////////////
//
// Privelege mode instructions
//
output header {{
/**
* Base class for privelege mode operations.
*/
class Priv : public SparcStaticInst
{
protected:
// Constructor
Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for user mode "tick" access.
*/
class PrivTick : public SparcStaticInst
{
protected:
// Constructor
PrivTick(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for privelege mode operations with immediates.
*/
class PrivImm : public Priv
{
protected:
// Constructor
PrivImm(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
Priv(mnem, _machInst, __opClass), imm(SIMM13)
{
}
uint32_t imm;
};
/**
* Base class for user mode "tick" access with immediates.
*/
class PrivTickImm : public PrivTick
{
protected:
// Constructor
PrivTickImm(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
{
}
uint32_t imm;
};
}};
output decoder {{
std::string Priv::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Privileged Instruction";
}
std::string PrivTick::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Regular access to Tick";
}
}};
def template PrivExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
//If the processor isn't in privileged mode, fault out right away
if(!pstate_priv)
return new PrivilegedOpCode
%(code)s;
%(op_wb)s;
}
}};
def template PrivTickExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
//If the processor isn't in privileged mode, fault out right away
if(!pstate_priv && tick_npt)
return new PrivilegedAction
%(code)s;
%(op_wb)s;
}
}};
def template Rb2OrImm13Decode {{
{
return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
: (SparcStaticInst *)(new %(class_name)s(machInst)));
}
}};
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
uses_imm = (code.find('Rs2_or_imm13') != -1)
if uses_imm:
orig_code = code
code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivExecute.subst(iop)
if uses_imm:
imm_cblk = CodeBlock(imm_code)
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivExecute.subst(imm_iop)
decode_block = Rb2OrImm13Decode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}};
// Primary format for integer operate instructions:
def format PrivTick(code, *opt_flags) {{
uses_imm = (code.find('Rs2_or_imm13') != -1)
if uses_imm:
orig_code = code
code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivTickExecute.subst(iop)
if uses_imm:
imm_cblk = CodeBlock(imm_code)
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivTickExecute.subst(imm_iop)
decode_block = Rb2OrImm13Decode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}};

13
arch/sparc/isa/formats/trap.isa
View file

@ -5,14 +5,15 @@
output header {{
/**
* Base class for integer operations.
* Base class for trap instructions,
* or instructions that always fault.
*/
class Trap : public SparcStaticInst
{
protected:
// Constructor
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) :
Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
@ -34,18 +35,18 @@ def template TrapExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//TODO: set up a software fault and return it.
return NoFault;
Fault fault = NoFault;
%(code)s
return fault;
}
}};
// Primary format for integer operate instructions:
def format Trap(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = TrapExecute.subst(iop)
}};

46
arch/sparc/isa/formats/unknown.isa Normal file
View file

@ -0,0 +1,46 @@
////////////////////////////////////////////////////////////////////
//
// Unknown instructions
//
output header {{
/**
* Class for Unknown/Illegal instructions
*/
class Unknown : public SparcStaticInst
{
public:
// Constructor
Unknown(ExtMachInst _machInst) :
SparcStaticInst("unknown", _machInst, No_OpClass)
{
}
%(BasicExecDeclare)s
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Unknown::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Unknown instruction\n";
}
}};
output exec {{
Fault Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
return new IllegalInstruction;
}
}};
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

2
arch/sparc/isa/includes.isa
View file

@ -39,5 +39,7 @@ output exec {{
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
using namespace SparcISA;
}};

81
arch/sparc/isa/operands.isa
View file

@ -27,5 +27,84 @@ def operands {{
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 1),
'R16': ('IntReg', 'udw', '16', None, 1)
'R16': ('IntReg', 'udw', '16', None, 1),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
#'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
#'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41),
'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
}};

11
arch/sparc/isa_traits.hh
View file

@ -83,6 +83,15 @@ class SyscallReturn
namespace SparcISA
{
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 96,
};
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
@ -142,7 +151,7 @@ namespace SparcISA
void unserialize(Checkpoint *cp, const std::string &section);
StaticInstPtr decodeInst(MachInst);
StaticInstPtr decodeInst(ExtMachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;