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Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.

Browse source 
arch/alpha/arguments.cc:
    Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
    Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
    Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
    Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
    Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
    Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
    Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
    Replaced setFloatRegDouble with setFloatReg

--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
This commit is contained in:
Gabe Black 2006-03-14 15:55:00 -05:00
parent 159cee1719
commit 8e4ec55703
18 changed files with 323 additions and 148 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/alpha/arguments.cc
View file

@ -54,7 +54,7 @@ AlphaArguments::getArg(bool fp)
{
if (number < 6) {
if (fp)
return xc->readFloatRegInt(16 + number);
return xc->readFloatRegBits(16 + number);
else
return xc->readIntReg(16 + number);
} else {

2
arch/alpha/ev5.cc
View file

@ -134,7 +134,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
cpu->cpuXC->setIntReg(ZeroReg, 0);
cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
}
Fault

66
arch/alpha/registerfile.hh
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ALPHA_REGISTERFILE_HH__
#define __ARCH_ALPHA_REGISTERFILE_HH__
#ifndef __ARCH_ALPHA_REGFILE_HH__
#define __ARCH_ALPHA_REGFILE_HH__
#include "arch/alpha/types.hh"
#include "arch/alpha/constants.hh"
@ -40,10 +40,64 @@ namespace AlphaISA
typedef IntReg IntRegFile[NumIntRegs];
typedef union {
uint64_t q[NumFloatRegs]; // integer qword view
double d[NumFloatRegs]; // double-precision floating point view
} FloatRegFile;
class FloatRegFile
{
protected:
union {
uint64_t q[NumFloatRegs]; // integer qword view
double d[NumFloatRegs]; // double-precision floating point view
};
public:
FloatReg readReg(int floatReg)
{
return d[floatReg];
}
FloatReg readReg(int floatReg, int width)
{
return readReg(floatReg);
}
FloatRegBits readRegBits(int floatReg)
{
return q[floatReg];
}
FloatRegBits readRegBits(int floatReg, int width)
{
return readRegBits(floatReg);
}
Fault setReg(int floatReg, const FloatReg &val)
{
d[floatReg] = val;
return NoFault;
}
Fault setReg(int floatReg, const FloatReg &val, int width)
{
return setReg(floatReg, val);
}
Fault setRegBits(int floatReg, const FloatRegBits &val)
{
q[floatReg] = val;
return NoFault;
}
Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
{
return setRegBits(floatReg, val);
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
class MiscRegFile {
protected:

6
arch/alpha/types.hh
View file

@ -54,10 +54,8 @@ namespace AlphaISA
typedef uint64_t IntReg;
// floating point register file entry type
typedef union {
uint64_t q;
double d;
} FloatReg;
typedef double FloatReg;
typedef uint64_t FloatRegBits;
// control register file contents
typedef uint64_t MiscReg;

34
arch/isa_parser.py
View file

@ -1217,16 +1217,23 @@ class FloatRegOperand(Operand):
def makeRead(self):
bit_select = 0
width = 0;
if (self.ctype == 'float'):
func = 'readFloatRegSingle'
func = 'readFloatReg'
width = 32;
elif (self.ctype == 'double'):
func = 'readFloatRegDouble'
func = 'readFloatReg'
width = 64;
else:
func = 'readFloatRegInt'
func = 'readFloatRegBits'
if (self.size != self.dflt_size):
bit_select = 1
base = 'xc->%s(this, %d)' % \
(func, self.src_reg_idx)
if width:
base = 'xc->%s(this, %d, %d)' % \
(func, self.src_reg_idx, width)
else:
base = 'xc->%s(this, %d)' % \
(func, self.src_reg_idx)
if bit_select:
return '%s = bits(%s, %d, 0);\n' % \
(self.base_name, base, self.size-1)
@ -1236,21 +1243,28 @@ class FloatRegOperand(Operand):
def makeWrite(self):
final_val = self.base_name
final_ctype = self.ctype
widthSpecifier = ''
width = 0
if (self.ctype == 'float'):
func = 'setFloatRegSingle'
width = 32
func = 'setFloatReg'
elif (self.ctype == 'double'):
func = 'setFloatRegDouble'
width = 64
func = 'setFloatReg'
else:
func = 'setFloatRegInt'
func = 'setFloatRegBits'
final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
if width:
widthSpecifier = ', %d' % width
wb = '''
{
%s final_val = %s;
xc->%s(this, %d, final_val);\n
xc->%s(this, %d, final_val%s);\n
if (traceData) { traceData->setData(final_val); }
}''' % (final_ctype, final_val, func, self.dest_reg_idx)
}''' % (final_ctype, final_val, func, self.dest_reg_idx,
widthSpecifier)
return wb
class ControlRegOperand(Operand):

4
base/remote_gdb.cc
View file

@ -440,7 +440,7 @@ RemoteGDB::getregs()
#ifdef KGDB_FP_REGS
for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
gdbregs[i + KGDB_REG_F0] = context->readFloatRegInt(i);
gdbregs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
}
#endif
}
@ -467,7 +467,7 @@ RemoteGDB::setregs()
#ifdef KGDB_FP_REGS
for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
context->setFloatRegInt(i, gdbregs[i + KGDB_REG_F0]);
context->setFloatRegBits(i, gdbregs[i + KGDB_REG_F0]);
}
#endif
context->setPC(gdbregs[KGDB_REG_PC]);

3
cpu/cpu_exec_context.cc
View file

@ -276,8 +276,7 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
setFloatRegDouble(i, xc->readFloatRegDouble(i));
setFloatRegInt(i, xc->readFloatRegInt(i));
setFloatRegBits(i, xc->readFloatRegBits(i));
}
// Copy misc. registers

36
cpu/cpu_exec_context.hh
View file

@ -70,6 +70,8 @@ class CPUExecContext
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
public:
typedef ExecContext::Status Status;
@ -374,19 +376,24 @@ class CPUExecContext
return regs.intRegFile[reg_idx];
}
float readFloatRegSingle(int reg_idx)
FloatReg readFloatReg(int reg_idx, int width)
{
return (float)regs.floatRegFile.d[reg_idx];
return regs.floatRegFile.readReg(reg_idx, width);
}
double readFloatRegDouble(int reg_idx)
FloatReg readFloatReg(int reg_idx)
{
return regs.floatRegFile.d[reg_idx];
return regs.floatRegFile.readReg(reg_idx);
}
uint64_t readFloatRegInt(int reg_idx)
FloatRegBits readFloatRegBits(int reg_idx, int width)
{
return regs.floatRegFile.q[reg_idx];
return regs.floatRegFile.readRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(int reg_idx)
{
return regs.floatRegFile.readRegBits(reg_idx);
}
void setIntReg(int reg_idx, uint64_t val)
@ -394,19 +401,24 @@ class CPUExecContext
regs.intRegFile[reg_idx] = val;
}
void setFloatRegSingle(int reg_idx, float val)
void setFloatReg(int reg_idx, FloatReg val, int width)
{
regs.floatRegFile.d[reg_idx] = (double)val;
regs.floatRegFile.setReg(reg_idx, val, width);
}
void setFloatRegDouble(int reg_idx, double val)
void setFloatReg(int reg_idx, FloatReg val)
{
regs.floatRegFile.d[reg_idx] = val;
regs.floatRegFile.setReg(reg_idx, val);
}
void setFloatRegInt(int reg_idx, uint64_t val)
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
regs.floatRegFile.q[reg_idx] = val;
regs.floatRegFile.setRegBits(reg_idx, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
regs.floatRegFile.setRegBits(reg_idx, val);
}
uint64_t readPC()

48
cpu/exec_context.hh
View file

@ -54,6 +54,8 @@ class ExecContext
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
public:
@ -165,19 +167,23 @@ class ExecContext
//
virtual uint64_t readIntReg(int reg_idx) = 0;
virtual float readFloatRegSingle(int reg_idx) = 0;
virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
virtual double readFloatRegDouble(int reg_idx) = 0;
virtual FloatReg readFloatReg(int reg_idx) = 0;
virtual uint64_t readFloatRegInt(int reg_idx) = 0;
virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, uint64_t val) = 0;
virtual void setFloatRegSingle(int reg_idx, float val) = 0;
virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
virtual void setFloatRegDouble(int reg_idx, double val) = 0;
virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
virtual void setFloatRegInt(int reg_idx, uint64_t val) = 0;
virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
virtual uint64_t readPC() = 0;
@ -333,26 +339,32 @@ class ProxyExecContext : public ExecContext
uint64_t readIntReg(int reg_idx)
{ return actualXC->readIntReg(reg_idx); }
float readFloatRegSingle(int reg_idx)
{ return actualXC->readFloatRegSingle(reg_idx); }
FloatReg readFloatReg(int reg_idx, int width)
{ return actualXC->readFloatReg(reg_idx, width); }
double readFloatRegDouble(int reg_idx)
{ return actualXC->readFloatRegDouble(reg_idx); }
FloatReg readFloatReg(int reg_idx)
{ return actualXC->readFloatReg(reg_idx); }
uint64_t readFloatRegInt(int reg_idx)
{ return actualXC->readFloatRegInt(reg_idx); }
FloatRegBits readFloatRegBits(int reg_idx, int width)
{ return actualXC->readFloatRegBits(reg_idx, width); }
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualXC->readFloatRegBits(reg_idx); }
void setIntReg(int reg_idx, uint64_t val)
{ actualXC->setIntReg(reg_idx, val); }
void setFloatRegSingle(int reg_idx, float val)
{ actualXC->setFloatRegSingle(reg_idx, val); }
void setFloatReg(int reg_idx, FloatReg val, int width)
{ actualXC->setFloatReg(reg_idx, val, width); }
void setFloatRegDouble(int reg_idx, double val)
{ actualXC->setFloatRegDouble(reg_idx, val); }
void setFloatReg(int reg_idx, FloatReg val)
{ actualXC->setFloatReg(reg_idx, val); }
void setFloatRegInt(int reg_idx, uint64_t val)
{ actualXC->setFloatRegInt(reg_idx, val); }
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{ actualXC->setFloatRegBits(reg_idx, val, width); }
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualXC->setFloatRegBits(reg_idx, val); }
uint64_t readPC() { return actualXC->readPC(); }

12
cpu/o3/alpha_cpu_impl.hh
View file

@ -175,10 +175,8 @@ AlphaFullCPU<Impl>::copyToXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
this->cpuXC->setFloatRegDouble(i,
this->regFile.readFloatRegDouble(renamed_reg));
this->cpuXC->setFloatRegInt(i,
this->regFile.readFloatRegInt(renamed_reg));
this->cpuXC->setFloatRegBits(i,
this->regFile.readFloatRegBits(renamed_reg));
}
this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag,
@ -223,10 +221,8 @@ AlphaFullCPU<Impl>::copyFromXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
this->regFile.setFloatRegDouble(renamed_reg,
this->cpuXC->readFloatRegDouble(i));
this->regFile.setFloatRegInt(renamed_reg,
this->cpuXC->readFloatRegInt(i));
this->regFile.setFloatRegBits(renamed_reg,
this->cpuXC->readFloatRegBits(i));
}
// Then loop through the misc registers.

36
cpu/o3/alpha_dyn_inst.hh
View file

@ -152,19 +152,24 @@ class AlphaDynInst : public BaseDynInst<Impl>
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
float readFloatRegSingle(const StaticInst *si, int idx)
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
double readFloatRegDouble(const StaticInst *si, int idx)
FloatReg readFloatReg(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
uint64_t readFloatRegInt(const StaticInst *si, int idx)
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
/** @todo: Make results into arrays so they can handle multiple dest
@ -176,21 +181,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
this->instResult.integer = val;
}
void setFloatRegSingle(const StaticInst *si, int idx, float val)
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
this->instResult.fp = val;
}
void setFloatRegDouble(const StaticInst *si, int idx, double val)
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
this->cpu->setFloatReg(_destRegIdx[idx], val);
this->instResult.dbl = val;
}
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
void setFloatRegBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{
this->cpu->setFloatRegInt(_destRegIdx[idx], val);
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
this->instResult.integer = val;
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
this->instResult.integer = val;
}

47
cpu/o3/cpu.cc
View file

@ -258,8 +258,7 @@ FullO3CPU<Impl>::init()
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i)
{
regFile.floatRegFile[i].d = src_xc->readFloatRegDouble(i);
regFile.floatRegFile[i].q = src_xc->readFloatRegInt(i);
regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i))
}
/*
// Then loop through the misc registers.
@ -348,24 +347,31 @@ FullO3CPU<Impl>::readIntReg(int reg_idx)
}
template <class Impl>
float
FullO3CPU<Impl>::readFloatRegSingle(int reg_idx)
FloatReg
FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
{
return regFile.readFloatRegSingle(reg_idx);
return regFile.readFloatReg(reg_idx, width);
}
template <class Impl>
double
FullO3CPU<Impl>::readFloatRegDouble(int reg_idx)
FloatReg
FullO3CPU<Impl>::readFloatReg(int reg_idx)
{
return regFile.readFloatRegDouble(reg_idx);
return regFile.readFloatReg(reg_idx);
}
template <class Impl>
uint64_t
FullO3CPU<Impl>::readFloatRegInt(int reg_idx)
FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
{
return regFile.readFloatRegInt(reg_idx);
return regFile.readFloatRegBits(reg_idx, width);
}
template <class Impl>
FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
{
return regFile.readFloatRegBits(reg_idx);
}
template <class Impl>
@ -377,23 +383,30 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
template <class Impl>
void
FullO3CPU<Impl>::setFloatRegSingle(int reg_idx, float val)
FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
{
regFile.setFloatRegSingle(reg_idx, val);
regFile.setFloatReg(reg_idx, val, width);
}
template <class Impl>
void
FullO3CPU<Impl>::setFloatRegDouble(int reg_idx, double val)
FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
regFile.setFloatRegDouble(reg_idx, val);
regFile.setFloatReg(reg_idx, val);
}
template <class Impl>
void
FullO3CPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
regFile.setFloatRegInt(reg_idx, val);
regFile.setFloatRegBits(reg_idx, val, width);
}
template <class Impl>
void
FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
regFile.setFloatRegBits(reg_idx, val);
}
template <class Impl>

16
cpu/o3/cpu.hh
View file

@ -170,19 +170,23 @@ class FullO3CPU : public BaseFullCPU
//
uint64_t readIntReg(int reg_idx);
float readFloatRegSingle(int reg_idx);
FloatReg readFloatReg(int reg_idx);
double readFloatRegDouble(int reg_idx);
FloatReg readFloatReg(int reg_idx, int width);
uint64_t readFloatRegInt(int reg_idx);
FloatRegBits readFloatRegBits(int reg_idx);
FloatRegBits readFloatRegBits(int reg_idx, int width);
void setIntReg(int reg_idx, uint64_t val);
void setFloatRegSingle(int reg_idx, float val);
void setFloatReg(int reg_idx, FloatReg val, int width);
void setFloatRegDouble(int reg_idx, double val);
void setFloatReg(int reg_idx, FloatReg val, int width);
void setFloatRegInt(int reg_idx, uint64_t val);
void setFloatRegBits(int reg_idx, FloatRegBits val);
void setFloatRegBits(int reg_idx, FloatRegBits val);
uint64_t readPC();

80
cpu/o3/regfile.hh
View file

@ -89,43 +89,64 @@ class PhysRegFile
return intRegFile[reg_idx];
}
float readFloatRegSingle(PhysRegIndex reg_idx)
FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to float register %i as single, has "
"data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
return (float)floatRegFile[reg_idx].d;
DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
"data %8.8d\n", int(reg_idx), (double)floatReg);
return floatReg;
}
double readFloatRegDouble(PhysRegIndex reg_idx)
FloatReg readFloatReg(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to float register %i as double, has "
" data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
FloatReg floatReg = floatRegFile.readReg(reg_idx);
return floatRegFile[reg_idx].d;
DPRINTF(IEW, "RegFile: Access to float register %i, has "
"data %8.8d\n", int(reg_idx), (double)floatReg);
return floatReg;
}
uint64_t readFloatRegInt(PhysRegIndex reg_idx)
FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to float register %i as int, has data "
"%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
return floatRegFile[reg_idx].q;
DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
"has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
return floatRegBits;
}
FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
DPRINTF(IEW, "RegFile: Access to float register %i as int, "
"has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
return floatRegBits;
}
void setIntReg(PhysRegIndex reg_idx, uint64_t val)
@ -138,33 +159,33 @@ class PhysRegFile
intRegFile[reg_idx] = val;
}
void setFloatRegSingle(PhysRegIndex reg_idx, float val)
void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
int(reg_idx), val);
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), (double)val);
floatRegFile[reg_idx].d = (double)val;
floatRegFile.setReg(reg_idx, val, width);
}
void setFloatRegDouble(PhysRegIndex reg_idx, double val)
void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
int(reg_idx), val);
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), (double)val);
floatRegFile[reg_idx].d = val;
floatRegFile.setReg(reg_idx, val);
}
void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val)
void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
@ -172,9 +193,22 @@ class PhysRegFile
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
int(reg_idx), val);
int(reg_idx), (uint64_t)val);
floatRegFile[reg_idx].q = val;
floatRegFile.setRegBits(reg_idx, val, width);
}
void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
int(reg_idx), (uint64_t)val);
floatRegFile.setRegBits(reg_idx, val);
}
uint64_t readPC()

36
cpu/ozone/cpu.hh
View file

@ -406,22 +406,28 @@ class OoOCPU : public BaseCPU
return xc->readIntReg(si->srcRegIdx(idx));
}
float readFloatRegSingle(StaticInst *si, int idx)
FloatReg readFloatReg(StaticInst *si, int idx, width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegSingle(reg_idx);
return xc->readFloatReg(reg_idx, width);
}
double readFloatRegDouble(StaticInst *si, int idx)
FloatReg readFloatReg(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegDouble(reg_idx);
return xc->readFloatReg(reg_idx);
}
uint64_t readFloatRegInt(StaticInst *si, int idx)
FloatRegBits readFloatRegBits(StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegInt(reg_idx);
return xc->readFloatRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegBits(reg_idx);
}
void setIntReg(StaticInst *si, int idx, uint64_t val)
@ -429,22 +435,28 @@ class OoOCPU : public BaseCPU
xc->setIntReg(si->destRegIdx(idx), val);
}
void setFloatRegSingle(StaticInst *si, int idx, float val)
void setFloatReg(StaticInst *si, int idx, FloatReg val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegSingle(reg_idx, val);
xc->setFloatReg(reg_idx, val, width);
}
void setFloatRegDouble(StaticInst *si, int idx, double val)
void setFloatReg(StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegDouble(reg_idx, val);
xc->setFloatReg(reg_idx, val);
}
void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegInt(reg_idx, val);
xc->setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegBits(reg_idx, val);
}
uint64_t readPC() { return PC; }

2
cpu/simple/cpu.cc
View file

@ -941,7 +941,7 @@ SimpleCPU::tick()
// maintain $r0 semantics
cpuXC->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
cpuXC->setFloatRegDouble(ZeroReg, 0.0);
cpuXC->setFloatReg(ZeroReg, 0.0);
#endif // ALPHA_ISA
if (status() == IcacheAccessComplete) {

39
cpu/simple/cpu.hh
View file

@ -80,6 +80,8 @@ class SimpleCPU : public BaseCPU
protected:
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
class CpuPort : public Port
{
@ -322,22 +324,28 @@ class SimpleCPU : public BaseCPU
return cpuXC->readIntReg(si->srcRegIdx(idx));
}
float readFloatRegSingle(const StaticInst *si, int idx)
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegSingle(reg_idx);
return cpuXC->readFloatReg(reg_idx, width);
}
double readFloatRegDouble(const StaticInst *si, int idx)
FloatReg readFloatReg(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegDouble(reg_idx);
return cpuXC->readFloatReg(reg_idx);
}
uint64_t readFloatRegInt(const StaticInst *si, int idx)
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegInt(reg_idx);
return cpuXC->readFloatRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegBits(reg_idx);
}
void setIntReg(const StaticInst *si, int idx, uint64_t val)
@ -345,22 +353,29 @@ class SimpleCPU : public BaseCPU
cpuXC->setIntReg(si->destRegIdx(idx), val);
}
void setFloatRegSingle(const StaticInst *si, int idx, float val)
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegSingle(reg_idx, val);
cpuXC->setFloatReg(reg_idx, val, width);
}
void setFloatRegDouble(const StaticInst *si, int idx, double val)
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegDouble(reg_idx, val);
cpuXC->setFloatReg(reg_idx, val);
}
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
void setFloatRegBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegInt(reg_idx, val);
cpuXC->setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegBits(reg_idx, val);
}
uint64_t readPC() { return cpuXC->readPC(); }

2
kern/tru64/tru64.hh
View file

@ -738,7 +738,7 @@ class Tru64 {
for (int i = 0; i < 31; ++i) {
xc->setIntReg(i, htog(sc->sc_regs[i]));
xc->setFloatRegInt(i, htog(sc->sc_fpregs[i]));
xc->setFloatRegBits(i, htog(sc->sc_fpregs[i]));
}
xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));