8e4ec55703
arch/alpha/arguments.cc:
Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
Replaced setFloatRegDouble with setFloatReg
--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
566 lines
14 KiB
C++
566 lines
14 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "config/full_system.hh"
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#if FULL_SYSTEM
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#include "sim/system.hh"
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#else
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#include "sim/process.hh"
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#endif
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#include "sim/root.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/o3/alpha_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "cpu/o3/cpu.hh"
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using namespace std;
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BaseFullCPU::BaseFullCPU(Params ¶ms)
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: BaseCPU(¶ms), cpu_id(0)
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{
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}
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template <class Impl>
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FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::TickEvent::process()
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{
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cpu->tick();
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}
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template <class Impl>
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const char *
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FullO3CPU<Impl>::TickEvent::description()
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{
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return "FullO3CPU tick event";
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}
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//Call constructor to all the pipeline stages here
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template <class Impl>
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FullO3CPU<Impl>::FullO3CPU(Params ¶ms)
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#if FULL_SYSTEM
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: BaseFullCPU(params),
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#else
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: BaseFullCPU(params),
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#endif // FULL_SYSTEM
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tickEvent(this),
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fetch(params),
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decode(params),
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rename(params),
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iew(params),
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commit(params),
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regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
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freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
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TheISA::NumFloatRegs, params.numPhysFloatRegs),
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renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
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TheISA::NumFloatRegs, params.numPhysFloatRegs,
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TheISA::NumMiscRegs,
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TheISA::ZeroReg,
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TheISA::ZeroReg + TheISA::NumIntRegs),
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rob(params.numROBEntries, params.squashWidth),
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// What to pass to these time buffers?
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// For now just have these time buffers be pretty big.
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timeBuffer(5, 5),
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fetchQueue(5, 5),
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decodeQueue(5, 5),
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renameQueue(5, 5),
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iewQueue(5, 5),
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cpuXC(NULL),
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globalSeqNum(1),
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#if FULL_SYSTEM
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system(params.system),
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memCtrl(system->memctrl),
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physmem(system->physmem),
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itb(params.itb),
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dtb(params.dtb),
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mem(params.mem),
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#else
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// Hardcoded for a single thread!!
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mem(params.workload[0]->getMemory()),
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#endif // FULL_SYSTEM
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icacheInterface(params.icacheInterface),
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dcacheInterface(params.dcacheInterface),
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deferRegistration(params.defReg),
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numInsts(0),
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funcExeInst(0)
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{
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_status = Idle;
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#if !FULL_SYSTEM
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thread.resize(this->number_of_threads);
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#endif
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for (int i = 0; i < this->number_of_threads; ++i) {
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#if FULL_SYSTEM
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assert(i == 0);
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thread[i] = new CPUExecContext(this, 0, system, itb, dtb, mem);
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system->execContexts[i] = thread[i]->getProxy();
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execContexts.push_back(system->execContexts[i]);
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#else
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if (i < params.workload.size()) {
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DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
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"process is %#x",
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i, params.workload[i]->prog_entry, thread[i]);
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thread[i] = new CPUExecContext(this, i, params.workload[i], i);
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}
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assert(params.workload[i]->getMemory() != NULL);
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assert(mem != NULL);
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execContexts.push_back(thread[i]->getProxy());
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#endif // !FULL_SYSTEM
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}
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// Note that this is a hack so that my code which still uses xc-> will
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// still work. I should remove this eventually
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cpuXC = thread[0];
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// The stages also need their CPU pointer setup. However this must be
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// done at the upper level CPU because they have pointers to the upper
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// level CPU, and not this FullO3CPU.
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// Give each of the stages the time buffer they will use.
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fetch.setTimeBuffer(&timeBuffer);
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decode.setTimeBuffer(&timeBuffer);
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rename.setTimeBuffer(&timeBuffer);
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iew.setTimeBuffer(&timeBuffer);
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commit.setTimeBuffer(&timeBuffer);
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// Also setup each of the stages' queues.
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fetch.setFetchQueue(&fetchQueue);
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decode.setFetchQueue(&fetchQueue);
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decode.setDecodeQueue(&decodeQueue);
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rename.setDecodeQueue(&decodeQueue);
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rename.setRenameQueue(&renameQueue);
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iew.setRenameQueue(&renameQueue);
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iew.setIEWQueue(&iewQueue);
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commit.setIEWQueue(&iewQueue);
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commit.setRenameQueue(&renameQueue);
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// Setup the rename map for whichever stages need it.
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rename.setRenameMap(&renameMap);
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iew.setRenameMap(&renameMap);
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// Setup the free list for whichever stages need it.
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rename.setFreeList(&freeList);
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renameMap.setFreeList(&freeList);
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// Setup the ROB for whichever stages need it.
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commit.setROB(&rob);
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}
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template <class Impl>
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FullO3CPU<Impl>::~FullO3CPU()
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{
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::fullCPURegStats()
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{
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// Register any of the FullCPU's stats here.
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::tick()
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{
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DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
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//Tick each of the stages if they're actually running.
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//Will want to figure out a way to unschedule itself if they're all
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//going to be idle for a long time.
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fetch.tick();
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decode.tick();
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rename.tick();
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iew.tick();
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commit.tick();
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// Now advance the time buffers, unless the stage is stalled.
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timeBuffer.advance();
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fetchQueue.advance();
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decodeQueue.advance();
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renameQueue.advance();
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iewQueue.advance();
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if (_status == Running && !tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::init()
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{
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if(!deferRegistration)
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{
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this->registerExecContexts();
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// Need to do a copy of the xc->regs into the CPU's regfile so
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// that it can start properly.
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#if FULL_SYSTEM
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ExecContext *src_xc = system->execContexts[0];
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TheISA::initCPU(src_xc, src_xc->readCpuId());
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#else
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ExecContext *src_xc = thread[0]->getProxy();
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#endif
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// First loop through the integer registers.
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for (int i = 0; i < TheISA::NumIntRegs; ++i)
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{
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regFile.intRegFile[i] = src_xc->readIntReg(i);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < TheISA::NumFloatRegs; ++i)
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{
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regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i))
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}
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/*
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// Then loop through the misc registers.
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regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
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regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
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regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
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regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
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*/
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// Then finally set the PC and the next PC.
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regFile.pc = src_xc->readPC();
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regFile.npc = src_xc->readNextPC();
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}
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::activateContext(int thread_num, int delay)
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{
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// Needs to set each stage to running as well.
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scheduleTickEvent(delay);
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_status = Running;
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::suspendContext(int thread_num)
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{
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panic("suspendContext unimplemented!");
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::deallocateContext(int thread_num)
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{
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panic("deallocateContext unimplemented!");
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::haltContext(int thread_num)
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{
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panic("haltContext unimplemented!");
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::switchOut()
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{
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panic("FullO3CPU does not have a switch out function.\n");
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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|
assert(!tickEvent.scheduled());
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|
|
// Set all status's to active, schedule the
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// CPU's tick event.
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|
for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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}
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template <class Impl>
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InstSeqNum
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FullO3CPU<Impl>::getAndIncrementInstSeq()
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{
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// Hopefully this works right.
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return globalSeqNum++;
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}
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template <class Impl>
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uint64_t
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FullO3CPU<Impl>::readIntReg(int reg_idx)
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{
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return regFile.readIntReg(reg_idx);
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}
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template <class Impl>
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FloatReg
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FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
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{
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return regFile.readFloatReg(reg_idx, width);
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}
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template <class Impl>
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FloatReg
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FullO3CPU<Impl>::readFloatReg(int reg_idx)
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{
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return regFile.readFloatReg(reg_idx);
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}
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template <class Impl>
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FloatRegBits
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FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
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{
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return regFile.readFloatRegBits(reg_idx, width);
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}
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template <class Impl>
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FloatRegBits
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FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
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{
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return regFile.readFloatRegBits(reg_idx);
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
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{
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regFile.setIntReg(reg_idx, val);
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
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{
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regFile.setFloatReg(reg_idx, val, width);
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
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{
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regFile.setFloatReg(reg_idx, val);
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}
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template <class Impl>
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void
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FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
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{
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regFile.setFloatRegBits(reg_idx, val, width);
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}
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|
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template <class Impl>
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void
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FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
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{
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regFile.setFloatRegBits(reg_idx, val);
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}
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template <class Impl>
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uint64_t
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FullO3CPU<Impl>::readPC()
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{
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return regFile.readPC();
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}
|
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|
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template <class Impl>
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void
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FullO3CPU<Impl>::setNextPC(uint64_t val)
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|
{
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regFile.setNextPC(val);
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}
|
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|
|
template <class Impl>
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void
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FullO3CPU<Impl>::setPC(Addr new_PC)
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{
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regFile.setPC(new_PC);
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}
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|
|
template <class Impl>
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void
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FullO3CPU<Impl>::addInst(DynInstPtr &inst)
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|
{
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|
instList.push_back(inst);
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|
}
|
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|
|
template <class Impl>
|
|
void
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|
FullO3CPU<Impl>::instDone()
|
|
{
|
|
// Keep an instruction count.
|
|
numInsts++;
|
|
|
|
// Check for instruction-count-based events.
|
|
comInstEventQueue[0]->serviceEvents(numInsts);
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|
}
|
|
|
|
template <class Impl>
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|
void
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|
FullO3CPU<Impl>::removeBackInst(DynInstPtr &inst)
|
|
{
|
|
DynInstPtr inst_to_delete;
|
|
|
|
// Walk through the instruction list, removing any instructions
|
|
// that were inserted after the given instruction, inst.
|
|
while (instList.back() != inst)
|
|
{
|
|
assert(!instList.empty());
|
|
|
|
// Obtain the pointer to the instruction.
|
|
inst_to_delete = instList.back();
|
|
|
|
DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n",
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|
inst_to_delete->seqNum, inst_to_delete->readPC());
|
|
|
|
// Remove the instruction from the list.
|
|
instList.pop_back();
|
|
|
|
// Mark it as squashed.
|
|
inst_to_delete->setSquashed();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
|
|
{
|
|
DynInstPtr inst_to_remove;
|
|
|
|
// The front instruction should be the same one being asked to be removed.
|
|
assert(instList.front() == inst);
|
|
|
|
// Remove the front instruction.
|
|
inst_to_remove = inst;
|
|
instList.pop_front();
|
|
|
|
DPRINTF(FullCPU, "FullCPU: Removing committed instruction %#x, PC %#x\n",
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|
inst_to_remove, inst_to_remove->readPC());
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|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FullO3CPU<Impl>::removeInstsNotInROB()
|
|
{
|
|
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
|
|
"list.\n");
|
|
|
|
DynInstPtr rob_tail = rob.readTailInst();
|
|
|
|
removeBackInst(rob_tail);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
|
|
{
|
|
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
|
|
"list.\n");
|
|
|
|
DynInstPtr inst_to_delete;
|
|
|
|
while (instList.back()->seqNum > seq_num) {
|
|
assert(!instList.empty());
|
|
|
|
// Obtain the pointer to the instruction.
|
|
inst_to_delete = instList.back();
|
|
|
|
DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n",
|
|
inst_to_delete->seqNum, inst_to_delete->readPC());
|
|
|
|
// Remove the instruction from the list.
|
|
instList.back() = NULL;
|
|
instList.pop_back();
|
|
|
|
// Mark it as squashed.
|
|
inst_to_delete->setSquashed();
|
|
}
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|
|
|
}
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|
|
|
template <class Impl>
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|
void
|
|
FullO3CPU<Impl>::removeAllInsts()
|
|
{
|
|
instList.clear();
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|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FullO3CPU<Impl>::dumpInsts()
|
|
{
|
|
int num = 0;
|
|
typename list<DynInstPtr>::iterator inst_list_it = instList.begin();
|
|
|
|
while (inst_list_it != instList.end())
|
|
{
|
|
cprintf("Instruction:%i\nPC:%#x\nSN:%lli\nIssued:%i\nSquashed:%i\n\n",
|
|
num, (*inst_list_it)->readPC(), (*inst_list_it)->seqNum,
|
|
(*inst_list_it)->isIssued(), (*inst_list_it)->isSquashed());
|
|
inst_list_it++;
|
|
++num;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
|
|
{
|
|
iew.wakeDependents(inst);
|
|
}
|
|
|
|
// Forward declaration of FullO3CPU.
|
|
template class FullO3CPU<AlphaSimpleImpl>;
|