gem5/arch
Korey Sewell bfd820f704 Update MiscReg enum and miscRegFile definition
update miscReg file access

arch/mips/isa/decoder.isa:
arch/mips/isa_traits.cc:
    update miscRegfile access
arch/mips/isa_traits.hh:
    Update MiscReg enum and miscRegFile definition

--HG--
extra : convert_revision : 9b6b9343d674e1e38e25bb9a4ffe4325142e7424
2006-03-08 04:36:55 -05:00
..
alpha Merge gblack@m5.eecs.umich.edu:/bk/multiarch 2006-03-07 04:42:06 -05:00
mips Update MiscReg enum and miscRegFile definition 2006-03-08 04:36:55 -05:00
sparc Changed the include paths to take advantage of the os specific directories. 2006-03-07 04:34:21 -05:00
isa_parser.py Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included. 2006-03-03 15:28:25 -05:00
isa_specific.hh Auto-generate arch/foo.hh "switch headers" in scons. 2006-02-22 22:22:06 -05:00
SConscript Filled out the object file loader so it can load object files for several OSs and architectures. 2006-03-04 03:09:23 -05:00