Steve Reinhardt 18ba0f8548 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 ... into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : a784e60b7f79d70b09052fc4a8ae35a821d307dc		2006-03-12 01:07:58 -05:00
..
alpha	Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5	2006-03-12 01:07:58 -05:00
mips	last changes before big merge	2006-03-09 03:27:51 -05:00
sparc	fix merging issues	2006-03-09 16:17:10 -05:00
isa_parser.py	Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.	2006-03-03 15:28:25 -05:00
isa_specific.hh	Auto-generate arch/foo.hh "switch headers" in scons.	2006-02-22 22:22:06 -05:00
SConscript	Work towards factoring isa_traits.hh into smaller, more specialized files.	2006-03-10 19:11:27 -05:00