Work towards factoring isa_traits.hh into smaller, more specialized files.

arch/SConscript:
    Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh.
arch/alpha/isa_traits.hh:
    Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore.
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
cpu/pc_event.hh:
cpu/static_inst.hh:
mem/port.hh:
sim/faults.cc:
sim/system.hh:
    base/misc.hh isn't included through isa_traits.hh anymore.
cpu/simple/cpu.cc:
    Added include for arch/utility.hh

--HG--
extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf

arch/SConscript

@@ -45,13 +45,17 @@ sources = []
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-	isa_traits.hh
-	tlb.hh
-	process.hh
 	arguments.hh
-	stacktrace.hh
-	vtophys.hh
+	constants.hh
 	faults.hh
+	isa_traits.hh
+	process.hh
+	registerfile.hh
+	stacktrace.hh
+	tlb.hh
+	types.hh
+	utility.hh
+	vtophys.hh
         ''')
 
 # Generate the header.  target[0] is the full path of the output

arch/alpha/isa_traits.hh

@@ -34,17 +34,10 @@ using namespace LittleEndianGuest;
 
 #include "arch/alpha/types.hh"
 #include "arch/alpha/constants.hh"
-#include "base/misc.hh"
+#include "arch/alpha/registerfile.hh"
 #include "config/full_system.hh"
 #include "sim/host.hh"
-#include "sim/faults.hh"
 
-class ExecContext;
-class FastCPU;
-class FullCPU;
-class Checkpoint;
-
-class StaticInst;
 class StaticInstPtr;
 
 #if !FULL_SYSTEM
@@ -86,13 +79,6 @@ class SyscallReturn {
 namespace AlphaISA
 {
 
-    typedef IntReg IntRegFile[NumIntRegs];
-
-    typedef union {
-        uint64_t q[NumFloatRegs];	// integer qword view
-        double d[NumFloatRegs];		// double-precision floating point view
-    } FloatRegFile;
-
 // redirected register map, really only used for the full system case.
 extern const int reg_redir[NumIntRegs];
 
@@ -101,130 +87,9 @@ extern const int reg_redir[NumIntRegs];
 #include "arch/alpha/isa_fullsys_traits.hh"
 
 #endif
-    class MiscRegFile {
-      protected:
-        uint64_t	fpcr;		// floating point condition codes
-        uint64_t	uniq;		// process-unique register
-        bool		lock_flag;	// lock flag for LL/SC
-        Addr		lock_addr;	// lock address for LL/SC
-
-      public:
-        MiscReg readReg(int misc_reg);
-
-        //These functions should be removed once the simplescalar cpu model
-        //has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
-
-        Fault setReg(int misc_reg, const MiscReg &val);
-
-        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
-                               ExecContext *xc);
-
-        void copyMiscRegs(ExecContext *xc);
-
-#if FULL_SYSTEM
-      protected:
-        typedef uint64_t InternalProcReg;
-
-        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
-      private:
-        InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
-
-        Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
-
-        void copyIprs(ExecContext *xc);
-#endif
-        friend class RegFile;
-    };
-
-    struct RegFile {
-        IntRegFile intRegFile;		// (signed) integer register file
-        FloatRegFile floatRegFile;	// floating point register file
-        MiscRegFile miscRegs;		// control register file
-        Addr pc;			// program counter
-        Addr npc;			// next-cycle program counter
-        Addr nnpc;
-
-#if FULL_SYSTEM
-        int intrflag;			// interrupt flag
-        inline int instAsid()
-        { return miscRegs.getInstAsid(); }
-        inline int dataAsid()
-        { return miscRegs.getDataAsid(); }
-#endif // FULL_SYSTEM
-
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-
-    static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
 
     StaticInstPtr decodeInst(ExtMachInst);
 
-    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
-    }
-
-    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return (reg >= 9 && reg <= 15);
-    }
-
-    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    static inline Addr alignAddress(const Addr &addr,
-                                         unsigned int nbytes) {
-        return (addr & ~(nbytes - 1));
-    }
-
-    // Instruction address compression hooks
-    static inline Addr realPCToFetchPC(const Addr &addr) {
-        return addr;
-    }
-
-    static inline Addr fetchPCToRealPC(const Addr &addr) {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    static inline size_t fetchInstSize() {
-        return sizeof(MachInst);
-    }
-
-    static inline MachInst makeRegisterCopy(int dest, int src) {
-        panic("makeRegisterCopy not implemented");
-        return 0;
-    }
-
-    // Machine operations
-
-    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
-                               int regnum);
-
-    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
-                                  int regnum);
-
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
-     */
-    template <class XC>
-    void zeroRegisters(XC *xc);
-
 #if !FULL_SYSTEM
     static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
     {
@@ -244,17 +109,4 @@ extern const int reg_redir[NumIntRegs];
 #endif
 };
 
-static inline AlphaISA::ExtMachInst
-AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
-#if FULL_SYSTEM
-    AlphaISA::ExtMachInst ext_inst = inst;
-    if (pc && 0x1)
-        return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
-    else
-        return ext_inst;
-#else
-    return AlphaISA::ExtMachInst(inst);
-#endif
-}
-
 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__

base/loader/ecoff_object.cc

@@ -29,6 +29,7 @@
 #include <string>
 
 #include "base/loader/ecoff_object.hh"
+#include "base/misc.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF

base/loader/elf_object.cc

@@ -42,6 +42,7 @@
 #include "libelf/gelf.h"
 
 #include "base/loader/elf_object.hh"
+#include "base/misc.hh"
 
 #include "base/loader/symtab.hh"
 

cpu/pc_event.hh

@@ -31,6 +31,8 @@
 
 #include <vector>
 
+#include "base/misc.hh"
+
 class ExecContext;
 class PCEventQueue;
 

cpu/simple/cpu.cc

@@ -35,6 +35,7 @@
 #include <sstream>
 #include <string>
 
+#include "arch/utility.hh"
 #include "base/cprintf.hh"
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"

cpu/static_inst.hh

@@ -33,6 +33,7 @@
 #include <string>
 
 #include "base/hashmap.hh"
+#include "base/misc.hh"
 #include "base/refcnt.hh"
 #include "cpu/op_class.hh"
 #include "sim/host.hh"

mem/port.hh

@@ -42,6 +42,7 @@
 #include <list>
 #include <inttypes.h>
 
+#include "base/misc.hh"
 #include "base/range.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"

sim/faults.cc

@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "base/misc.hh"
 #include "sim/faults.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/base.hh"

sim/system.hh

@@ -32,8 +32,9 @@
 #include <string>
 #include <vector>
 
-#include "base/statistics.hh"
 #include "base/loader/symtab.hh"
+#include "base/misc.hh"
+#include "base/statistics.hh"
 #include "cpu/pc_event.hh"
 #include "sim/sim_object.hh"
 #if FULL_SYSTEM