gem5/arch
Korey Sewell 0d8cfed042 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
2006-03-14 18:30:09 -05:00
..
alpha Fixed up after a hand merge. 2006-03-14 16:39:59 -05:00
mips Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu 2006-03-14 18:28:51 -05:00
sparc Fixed up after a hand merge. 2006-03-14 16:39:59 -05:00
isa_parser.py Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
isa_specific.hh Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu 2006-03-14 18:28:51 -05:00
SConscript Moved registerfile.hh to regfile.hh 2006-03-14 16:05:44 -05:00