Pushed ev5.hh out of the non-alpha code.

arch/SConscript:
    ev5 should now be contained within alpha specific code.
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed.
arch/sparc/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes.
cpu/o3/alpha_cpu.hh:
    Added typedefs which are required now that there isn't a using namespace EV5.
cpu/o3/alpha_cpu_impl.hh:
    Some small changes so that ev5.hh isn't needed directly.
cpu/o3/cpu.hh:
    Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile.
cpu/o3/regfile.hh:
    Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array.

--HG--
extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd

arch/SConscript

@@ -52,7 +52,6 @@ isa_switch_hdrs = Split('''
 	stacktrace.hh
 	vtophys.hh
 	faults.hh
-	ev5.hh
         ''')
 
 # Generate the header.  target[0] is the full path of the output

arch/alpha/ev5.cc

@@ -152,6 +152,18 @@ ExecContext::hwrei()
     return NoFault;
 }
 
+int
+AlphaISA::MiscRegFile::getInstAsid()
+{
+    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+}
+
+int
+AlphaISA::MiscRegFile::getDataAsid()
+{
+    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+}
+
 void
 AlphaISA::MiscRegFile::clearIprs()
 {

arch/alpha/isa_traits.hh

@@ -166,6 +166,11 @@ extern const int reg_redir[NumIntRegs];
       public:
         MiscReg readReg(int misc_reg);
 
+        //These functions should be removed once the simplescalar cpu model
+        //has been replaced.
+        int getInstAsid();
+        int getDataAsid();
+
         MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
 
         Fault setReg(int misc_reg, const MiscReg &val);

arch/sparc/isa_traits.hh

@@ -57,7 +57,7 @@ class StaticInstPtr;
 namespace SparcISA
 {
     typedef uint32_t MachInst;
-    typedef uint64_t Addr;
+    typedef uint64_t ExtMachInst;
     typedef uint8_t  RegIndex;
 
     enum
@@ -179,7 +179,7 @@ namespace SparcISA
     // The control registers, broken out into fields
     class MiscRegFile
     {
-      public:
+      private:
         union
         {
             uint16_t pstate;		// Process State Register
@@ -365,6 +365,16 @@ namespace SparcISA
             } fprsFields;
         };
 
+      public:
+        MiscReg readReg(int misc_reg);
+
+        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
+
+        Fault setReg(int misc_reg, const MiscReg &val);
+
+        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+                               ExecContext *xc);
+
         void serialize(std::ostream & os);
 
         void unserialize(Checkpoint * cp, std::string & section);

cpu/o3/alpha_cpu.hh

@@ -42,6 +42,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   protected:
     typedef TheISA::IntReg IntReg;
     typedef TheISA::MiscReg MiscReg;
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::MiscRegFile MiscRegFile;
 
   public:
     typedef typename Impl::Params Params;

cpu/o3/alpha_cpu_impl.hh

@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "arch/alpha/faults.hh"
 #include "base/cprintf.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
@@ -257,7 +258,7 @@ Fault
 AlphaFullCPU<Impl>::hwrei()
 {
     if (!inPalMode())
-        return new UnimplementedOpcodeFault;
+        return new AlphaISA::UnimplementedOpcodeFault;
 
     this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
 

cpu/o3/cpu.hh

@@ -49,11 +49,6 @@
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
-#if FULL_SYSTEM
-#include "arch/ev5.hh"
-using namespace EV5;
-#endif
-
 class FunctionalMemory;
 class Process;
 
@@ -152,11 +147,11 @@ class FullO3CPU : public BaseFullCPU
 
     /** Get instruction asid. */
     int getInstAsid()
-    { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
+    { return regFile.miscRegs.getInstAsid(); }
 
     /** Get data asid. */
     int getDataAsid()
-    { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
+    { return regFile.miscRegs.getDataAsid(); }
 #else
     bool validInstAddr(Addr addr)
     { return thread[0]->validInstAddr(addr); }

cpu/o3/regfile.hh

@@ -38,10 +38,8 @@
 #include "cpu/o3/comm.hh"
 
 #if FULL_SYSTEM
-#include "arch/ev5.hh"
 #include "kern/kernel_stats.hh"
 
-using namespace EV5;
 #endif
 
 // This really only depends on the ISA, and not the Impl.  It might be nicer
@@ -237,7 +235,6 @@ class PhysRegFile
   private:
     // This is ISA specifc stuff; remove it eventually once ISAImpl is used
 //    IntReg palregs[NumIntRegs];	// PAL shadow registers
-    InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
     int intrflag;			// interrupt flag
     bool pal_shadow;		// using pal_shadow registers
 #endif