Korey Sewell a3aae21d03 last changes before big merge ... arch/alpha/isa_traits.hh: arch/sparc/isa_traits.hh: add nnpc for compiling purposes in exec_context setNextNPC function cpu/exec_context.hh: set NNPC function cpu/simple/cpu.cc: use NNPC in determining what PC we are using --HG-- extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532		2006-03-09 03:27:51 -05:00
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alpha	last changes before big merge	2006-03-09 03:27:51 -05:00
mips	last changes before big merge	2006-03-09 03:27:51 -05:00
sparc	last changes before big merge	2006-03-09 03:27:51 -05:00
isa_parser.py	Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.	2006-03-03 15:28:25 -05:00
isa_specific.hh	Auto-generate arch/foo.hh "switch headers" in scons.	2006-02-22 22:22:06 -05:00
SConscript	Pushed ev5.hh out of the non-alpha code.	2006-03-07 14:08:01 -05:00