Clean up of the SPARC isa_traits. This still doesn't compile, but it's closer.
--HG-- extra : convert_revision : 7b22a4a4af5bcb13e2d9322ef93d3f582e8efa92
This commit is contained in:
Gabe Black
parent
9e43f70ac2
commit
547999eb1f
1 changed files with 412 additions and 435 deletions
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@ -29,22 +29,24 @@
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#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
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#define __ARCH_SPARC_ISA_TRAITS_HH__
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#include "arch/sparc/faults.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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//This makes sure the big endian versions of certain functions are used.
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namespace BigEndianGuest {}
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using namespace BigEndianGuest;
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#include "arch/sparc/faults.hh"
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#include "base/misc.hh"
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#include "sim/host.hh"
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class ExecContext;
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class FastCPU;
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//class FullCPU;
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//class Checkpoint;
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class Checkpoint;
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#define TARGET_SPARC
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template <class ISA> class StaticInst;
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template <class ISA> class StaticInstPtr;
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class StaticInst;
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class StaticInstPtr;
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//namespace EV5
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//{
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@ -52,479 +54,454 @@ template <class ISA> class StaticInstPtr;
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// int ITB_ASN_ASN(uint64_t reg);
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//}
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class SPARCISA
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namespace SparcISA
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{
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public:
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typedef uint32_t MachInst;
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typedef uint64_t Addr;
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typedef uint8_t RegIndex;
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typedef uint32_t MachInst;
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typedef uint64_t Addr;
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typedef uint8_t RegIndex;
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enum
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{
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MemoryEnd = 0xffffffffffffffffULL,
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enum
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{
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MemoryEnd = 0xffffffffffffffffULL,
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NumFloatRegs = 32,
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NumMiscRegs = 32,
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NumFloatRegs = 32,
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NumMiscRegs = 32,
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MaxRegsOfAnyType = 32,
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// Static instruction parameters
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MaxInstSrcRegs = 3,
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MaxInstDestRegs = 2,
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MaxRegsOfAnyType = 32,
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// Static instruction parameters
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MaxInstSrcRegs = 3,
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MaxInstDestRegs = 2,
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// Maximum trap level
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MaxTL = 4,
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// Maximum trap level
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MaxTL = 4
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// semantically meaningful register indices
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ZeroReg = 0 // architecturally meaningful
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// the rest of these depend on the ABI
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};
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typedef uint64_t IntReg;
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// semantically meaningful register indices
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ZeroReg = 0, // architecturally meaningful
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// the rest of these depend on the ABI
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}
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typedef uint64_t IntReg;
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class IntRegFile
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{
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class IntRegFile
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{
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private:
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//For right now, let's pretend the register file is static
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IntReg regs[32];
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//For right now, let's pretend the register file is static
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IntReg regs[32];
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public:
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IntReg & operator [] (RegIndex index)
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IntReg & operator [] (RegIndex index)
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{
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//Don't allow indexes outside of the 32 registers
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index &= 0x1F;
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return regs[index];
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}
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};
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void serialize(std::ostream & os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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class FloatRegFile
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{
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private:
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//By using the largest data type, we ensure everything
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//is aligned correctly in memory
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union
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{
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long double rawRegs[16];
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uint64_t regDump[32];
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};
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class QuadRegs
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{
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private:
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FloatRegFile * parent;
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public:
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QuadRegs(FloatRegFile * p) : parent(p) {;}
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long double & operator [] (RegIndex index)
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{
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//Quad floats are index by the single
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//precision register the start on,
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//and only 16 should be accessed
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index = (index >> 2) & 0xF;
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return parent->rawRegs[index];
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}
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};
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class DoubleRegs
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{
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private:
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FloatRegFile * parent;
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public:
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DoubleRegs(FloatRegFile * p) : parent(p) {;}
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double & operator [] (RegIndex index)
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{
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//Double floats are index by the single
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//precision register the start on,
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//and only 32 should be accessed
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index = (index >> 1) & 0x1F;
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return ((double *)parent->rawRegs)[index];
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}
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};
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class SingleRegs
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{
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private:
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FloatRegFile * parent;
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public:
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SingleRegs(FloatRegFile * p) : parent(p) {;}
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float & operator [] (RegIndex index)
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{
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//Only 32 single floats should be accessed
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index &= 0x1F;
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return ((float *)parent->rawRegs)[index];
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}
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};
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public:
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void serialize(std::ostream & os);
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void unserialize(Checkpoint * cp, std::string & section);
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QuadRegs quadRegs;
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DoubleRegs doubleRegs;
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SingleRegs singleRegs;
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FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
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{;}
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};
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// control register file contents
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typedef uint64_t MiscReg;
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// The control registers, broken out into fields
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class MiscRegFile
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{
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public:
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union
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{
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uint16_t pstate; // Process State Register
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struct
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{
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uint16_t ag:1; // Alternate Globals
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uint16_t ie:1; // Interrupt enable
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uint16_t priv:1; // Privelege mode
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uint16_t am:1; // Address mask
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uint16_t pef:1; // PSTATE enable floating-point
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uint16_t red:1; // RED (reset, error, debug) state
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uint16_t mm:2; // Memory Model
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uint16_t tle:1; // Trap little-endian
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uint16_t cle:1; // Current little-endian
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} pstateFields;
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};
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uint64_t tba; // Trap Base Address
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union
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{
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uint64_t y; // Y (used in obsolete multiplication)
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struct
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{
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uint64_t value:32; // The actual value stored in y
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const uint64_t :32; // reserved bits
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} yFields;
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};
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uint8_t pil; // Process Interrupt Register
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uint8_t cwp; // Current Window Pointer
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uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
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// on the previous level)
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union
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{
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uint8_t ccr; // Condition Code Register
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struct
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{
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union
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{
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//Don't allow indexes outside of the 32 registers
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index &= 0x1F
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return regs[index];
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}
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uint8_t icc:4; // 32-bit condition codes
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struct
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{
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} iccFields:4;
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} :4;
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union
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{
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uint8_t xcc:4; // 64-bit condition codes
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struct
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{
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} xccFields:4;
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} :4;
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} ccrFields;
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};
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uint8_t asi; // Address Space Identifier
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uint8_t tl; // Trap Level
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uint64_t tpc[MaxTL]; // Trap Program Counter (value from
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// previous trap level)
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uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
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// previous trap level)
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union
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{
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uint64_t tstate[MaxTL]; // Trap State
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struct
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{
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//Values are from previous trap level
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uint64_t cwp:5; // Current Window Pointer
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const uint64_t :2; // Reserved bits
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uint64_t pstate:10; // Process State
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const uint64_t :6; // Reserved bits
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uint64_t asi:8; // Address Space Identifier
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uint64_t ccr:8; // Condition Code Register
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} tstateFields[MaxTL];
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};
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union
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{
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uint64_t tick; // Hardware clock-tick counter
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struct
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{
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uint64_t counter:63; // Clock-tick count
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uint64_t npt:1; // Non-priveleged trap
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} tickFields;
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}
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uint8_t cansave; // Savable windows
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uint8_t canrestore; // Restorable windows
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uint8_t otherwin; // Other windows
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uint8_t cleanwin; // Clean windows
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union
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{
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uint8_t wstate; // Window State
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struct
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{
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uint8_t normal:3; // Bits TT<4:2> are set to on a normal
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// register window trap
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uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
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// register window trap
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} wstateFields;
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};
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union
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{
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uint64_t ver; // Version
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struct
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{
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uint64_t maxwin:5; // Max CWP value
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const uint64_t :2; // Reserved bits
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uint64_t maxtl:8; // Maximum trap level
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const uint64_t :8; // Reserved bits
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uint64_t mask:8; // Processor mask set revision number
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uint64_t impl:16; // Implementation identification number
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uint64_t manuf:16; // Manufacturer code
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} verFields;
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};
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union
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{
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uint64_t fsr; // Floating-Point State Register
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struct
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{
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union
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{
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uint64_t cexc:5; // Current excpetion
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struct
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{
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uint64_t nxc:1; // Inexact
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uint64_t dzc:1; // Divide by zero
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uint64_t ufc:1; // Underflow
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uint64_t ofc:1; // Overflow
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uint64_t nvc:1; // Invalid operand
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} cexecFields:5;
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} :5;
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union
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{
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uint64_t aexc:5; // Accrued exception
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struct
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{
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uint64_t nxc:1; // Inexact
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uint64_t dzc:1; // Divide by zero
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uint64_t ufc:1; // Underflow
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uint64_t ofc:1; // Overflow
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uint64_t nvc:1; // Invalid operand
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} aexecFields:5;
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} :5;
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uint64_t fcc0:2; // Floating-Point condtion codes
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const uint64_t :1; // Reserved bits
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uint64_t qne:1; // Deferred trap queue not empty
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// with no queue, it should read 0
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uint64_t ftt:3; // Floating-Point trap type
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uint64_t ver:3; // Version (of the FPU)
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const uint64_t :2; // Reserved bits
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uint64_t ns:1; // Nonstandard floating point
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union
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{
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uint64_t tem:5; // Trap Enable Mask
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struct
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{
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uint64_t nxm:1; // Inexact
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uint64_t dzm:1; // Divide by zero
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uint64_t ufm:1; // Underflow
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uint64_t ofm:1; // Overflow
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uint64_t nvm:1; // Invalid operand
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} temFields:5;
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} :5;
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const uint64_t :2; // Reserved bits
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uint64_t rd:2; // Rounding direction
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uint64_t fcc1:2; // Floating-Point condition codes
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uint64_t fcc2:2; // Floating-Point condition codes
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uint64_t fcc3:2; // Floating-Point condition codes
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const uint64_t :26; // Reserved bits
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} fsrFields;
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}
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union
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{
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uint8_t fprs; // Floating-Point Register State
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struct
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{
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uint8_t dl:1; // Dirty lower
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uint8_t du:1; // Dirty upper
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fef:1; // FPRS enable floating-Point
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} fprsFields;
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};
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void inline serialize(std::ostream & os)
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void serialize(std::ostream & os)
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{
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SERIALIZE_ARRAY(regs, 32);
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SERIALIZE_SCALAR(pstate);
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SERIAlIZE_SCALAR(tba);
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SERIALIZE_SCALAR(y);
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SERIALIZE_SCALAR(pil);
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SERIALIZE_SCALAR(cwp);
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SERIALIZE_ARRAY(tt, MaxTL);
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SERIALIZE_SCALAR(ccr);
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SERIALIZE_SCALAR(asi);
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SERIALIZE_SCALAR(tl);
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SERIALIZE_SCALAR(tpc);
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SERIALIZE_SCALAR(tnpc);
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SERIALIZE_ARRAY(tstate, MaxTL);
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SERIALIZE_SCALAR(tick);
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SERIALIZE_SCALAR(cansave);
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SERIALIZE_SCALAR(canrestore);
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SERIALIZE_SCALAR(otherwin);
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SERIALIZE_SCALAR(cleanwin);
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SERIALIZE_SCALAR(wstate);
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SERIALIZE_SCALAR(ver);
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SERIALIZE_SCALAR(fsr);
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SERIALIZE_SCALAR(fprs);
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}
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void inline unserialize(Checkpoint &*cp, const std::string §ion)
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void unserialize(Checkpoint &* cp, std::string & section)
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{
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UNSERIALIZE_ARRAY(regs, 32);
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UNSERIALIZE_SCALAR(pstate);
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UNSERIAlIZE_SCALAR(tba);
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UNSERIALIZE_SCALAR(y);
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UNSERIALIZE_SCALAR(pil);
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UNSERIALIZE_SCALAR(cwp);
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UNSERIALIZE_ARRAY(tt, MaxTL);
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UNSERIALIZE_SCALAR(ccr);
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UNSERIALIZE_SCALAR(asi);
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UNSERIALIZE_SCALAR(tl);
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UNSERIALIZE_SCALAR(tpc);
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UNSERIALIZE_SCALAR(tnpc);
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UNSERIALIZE_ARRAY(tstate, MaxTL);
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UNSERIALIZE_SCALAR(tick);
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UNSERIALIZE_SCALAR(cansave);
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UNSERIALIZE_SCALAR(canrestore);
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UNSERIALIZE_SCALAR(otherwin);
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UNSERIALIZE_SCALAR(cleanwin);
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UNSERIALIZE_SCALAR(wstate);
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UNSERIALIZE_SCALAR(ver);
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UNSERIALIZE_SCALAR(fsr);
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UNSERIALIZE_SCALAR(fprs);
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}
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};
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class FloatRegFile
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{
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private:
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//By using the largest data type, we ensure everything
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//is aligned correctly in memory
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union
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{
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double double rawRegs[16];
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uint64_t regDump[32];
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};
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class QuadRegs
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{
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private:
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FloatRegFile * parent;
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public:
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QuadRegs(FloatRegFile * p) : parent(p) {;}
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double double & operator [] (RegIndex index)
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{
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//Quad floats are index by the single
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//precision register the start on,
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//and only 16 should be accessed
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index = (index >> 2) & 0xF;
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return parent->rawRegs[index];
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}
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};
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class DoubleRegs
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{
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private:
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FloatRegFile * parent;
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public:
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DoubleRegs(FloatRegFile * p) : parent(p) {;}
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double & operator [] (RegIndex index)
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{
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//Double floats are index by the single
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//precision register the start on,
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//and only 32 should be accessed
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index = (index >> 1) & 0x1F
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return ((double [])parent->rawRegs)[index];
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}
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}
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class SingleRegs
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{
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private:
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FloatRegFile * parent;
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public:
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SingleRegs(FloatRegFile * p) : parent(p) {;}
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double & operator [] (RegFile index)
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{
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//Only 32 single floats should be accessed
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index &= 0x1F
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return ((float [])parent->rawRegs)[index];
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}
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}
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public:
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void inline serialize(std::ostream & os)
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{
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SERIALIZE_ARRAY(regDump, 32);
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}
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typedef union
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{
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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} AnyReg;
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void inline unserialize(Checkpoint &* cp, std::string & section)
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{
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UNSERIALIZE_ARRAY(regDump, 32);
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}
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struct RegFile
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{
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegFile; // control register file
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QuadRegs quadRegs;
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DoubleRegs doubleRegs;
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SingleRegs singleRegs;
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FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
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{;}
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};
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Addr pc; // Program Counter
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Addr npc; // Next Program Counter
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// control register file contents
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typedef uint64_t MiscReg;
|
||||
// The control registers, broken out into fields
|
||||
class MiscRegFile
|
||||
{
|
||||
public:
|
||||
union
|
||||
{
|
||||
uint16_t pstate; // Process State Register
|
||||
struct
|
||||
{
|
||||
uint16_t ag:1; // Alternate Globals
|
||||
uint16_t ie:1; // Interrupt enable
|
||||
uint16_t priv:1; // Privelege mode
|
||||
uint16_t am:1; // Address mask
|
||||
uint16_t pef:1; // PSTATE enable floating-point
|
||||
uint16_t red:1; // RED (reset, error, debug) state
|
||||
uint16_t mm:2; // Memory Model
|
||||
uint16_t tle:1; // Trap little-endian
|
||||
uint16_t cle:1; // Current little-endian
|
||||
} pstateFields;
|
||||
}
|
||||
uint64_t tba; // Trap Base Address
|
||||
union
|
||||
{
|
||||
uint64_t y; // Y (used in obsolete multiplication)
|
||||
struct
|
||||
{
|
||||
uint64_t value:32; // The actual value stored in y
|
||||
const uint64_t :32; // reserved bits
|
||||
} yFields;
|
||||
}
|
||||
uint8_t pil; // Process Interrupt Register
|
||||
uint8_t cwp; // Current Window Pointer
|
||||
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level)
|
||||
union
|
||||
{
|
||||
uint8_t ccr; // Condition Code Register
|
||||
struct
|
||||
{
|
||||
union
|
||||
{
|
||||
uint8_t icc:4; // 32-bit condition codes
|
||||
struct
|
||||
{
|
||||
uint8_t c:1; // Carry
|
||||
uint8_t v:1; // Overflow
|
||||
uint8_t z:1; // Zero
|
||||
uint8_t n:1; // Negative
|
||||
} iccFields:4;
|
||||
} :4;
|
||||
union
|
||||
{
|
||||
uint8_t xcc:4; // 64-bit condition codes
|
||||
struct
|
||||
{
|
||||
uint8_t c:1; // Carry
|
||||
uint8_t v:1; // Overflow
|
||||
uint8_t z:1; // Zero
|
||||
uint8_t n:1; // Negative
|
||||
} xccFields:4;
|
||||
} :4;
|
||||
} ccrFields;
|
||||
}
|
||||
uint8_t asi; // Address Space Identifier
|
||||
uint8_t tl; // Trap Level
|
||||
uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level)
|
||||
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level)
|
||||
union
|
||||
{
|
||||
uint64_t tstate[MaxTL]; // Trap State
|
||||
struct
|
||||
{
|
||||
//Values are from previous trap level
|
||||
uint64_t cwp:5; // Current Window Pointer
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t pstate:10; // Process State
|
||||
const uint64_t :6; // Reserved bits
|
||||
uint64_t asi:8; // Address Space Identifier
|
||||
uint64_t ccr:8; // Condition Code Register
|
||||
} tstateFields[MaxTL];
|
||||
}
|
||||
union
|
||||
{
|
||||
uint64_t tick; // Hardware clock-tick counter
|
||||
struct
|
||||
{
|
||||
uint64_t counter:63; // Clock-tick count
|
||||
uint64_t npt:1; // Non-priveleged trap
|
||||
} tickFields;
|
||||
}
|
||||
uint8_t cansave; // Savable windows
|
||||
uint8_t canrestore; // Restorable windows
|
||||
uint8_t otherwin; // Other windows
|
||||
uint8_t cleanwin; // Clean windows
|
||||
union
|
||||
{
|
||||
uint8_t wstate; // Window State
|
||||
struct
|
||||
{
|
||||
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
|
||||
// register window trap
|
||||
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
||||
// register window trap
|
||||
} wstateFields;
|
||||
}
|
||||
union
|
||||
{
|
||||
uint64_t ver; // Version
|
||||
struct
|
||||
{
|
||||
uint64_t maxwin:5; // Max CWP value
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t maxtl:8; // Maximum trap level
|
||||
const uint64_t :8; // Reserved bits
|
||||
uint64_t mask:8; // Processor mask set revision number
|
||||
uint64_t impl:16; // Implementation identification number
|
||||
uint64_t manuf:16; // Manufacturer code
|
||||
} verFields;
|
||||
}
|
||||
union
|
||||
{
|
||||
uint64_t fsr; // Floating-Point State Register
|
||||
struct
|
||||
{
|
||||
union
|
||||
{
|
||||
uint64_t cexc:5; // Current excpetion
|
||||
struct
|
||||
{
|
||||
uint64_t nxc:1; // Inexact
|
||||
uint64_t dzc:1; // Divide by zero
|
||||
uint64_t ufc:1; // Underflow
|
||||
uint64_t ofc:1; // Overflow
|
||||
uint64_t nvc:1; // Invalid operand
|
||||
} cexecFields:5;
|
||||
} :5;
|
||||
union
|
||||
{
|
||||
uint64_t aexc:5; // Accrued exception
|
||||
struct
|
||||
{
|
||||
uint64_t nxc:1; // Inexact
|
||||
uint64_t dzc:1; // Divide by zero
|
||||
uint64_t ufc:1; // Underflow
|
||||
uint64_t ofc:1; // Overflow
|
||||
uint64_t nvc:1; // Invalid operand
|
||||
} aexecFields:5;
|
||||
} :5;
|
||||
uint64_t fcc0:2; // Floating-Point condtion codes
|
||||
const uint64_t :1; // Reserved bits
|
||||
uint64_t qne:1; // Deferred trap queue not empty
|
||||
// with no queue, it should read 0
|
||||
uint64_t ftt:3; // Floating-Point trap type
|
||||
uint64_t ver:3; // Version (of the FPU)
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t ns:1; // Nonstandard floating point
|
||||
union
|
||||
{
|
||||
uint64_t tem:5; // Trap Enable Mask
|
||||
struct
|
||||
{
|
||||
uint64_t nxm:1; // Inexact
|
||||
uint64_t dzm:1; // Divide by zero
|
||||
uint64_t ufm:1; // Underflow
|
||||
uint64_t ofm:1; // Overflow
|
||||
uint64_t nvm:1; // Invalid operand
|
||||
} temFields:5;
|
||||
} :5;
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t rd:2; // Rounding direction
|
||||
uint64_t fcc1:2; // Floating-Point condition codes
|
||||
uint64_t fcc2:2; // Floating-Point condition codes
|
||||
uint64_t fcc3:2; // Floating-Point condition codes
|
||||
const uint64_t :26; // Reserved bits
|
||||
} fsrFields;
|
||||
}
|
||||
union
|
||||
{
|
||||
uint8_t fprs; // Floating-Point Register State
|
||||
struct
|
||||
{
|
||||
dl:1; // Dirty lower
|
||||
du:1; // Dirty upper
|
||||
fef:1; // FPRS enable floating-Point
|
||||
} fprsFields;
|
||||
};
|
||||
void serialize(std::ostream &os);
|
||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
|
||||
void serialize(std::ostream & os)
|
||||
{
|
||||
SERIALIZE_SCALAR(pstate);
|
||||
SERIAlIZE_SCALAR(tba);
|
||||
SERIALIZE_SCALAR(y);
|
||||
SERIALIZE_SCALAR(pil);
|
||||
SERIALIZE_SCALAR(cwp);
|
||||
SERIALIZE_ARRAY(tt, MaxTL);
|
||||
SERIALIZE_SCALAR(ccr);
|
||||
SERIALIZE_SCALAR(asi);
|
||||
SERIALIZE_SCALAR(tl);
|
||||
SERIALIZE_SCALAR(tpc);
|
||||
SERIALIZE_SCALAR(tnpc);
|
||||
SERIALIZE_ARRAY(tstate, MaxTL);
|
||||
SERIALIZE_SCALAR(tick);
|
||||
SERIALIZE_SCALAR(cansave);
|
||||
SERIALIZE_SCALAR(canrestore);
|
||||
SERIALIZE_SCALAR(otherwin);
|
||||
SERIALIZE_SCALAR(cleanwin);
|
||||
SERIALIZE_SCALAR(wstate);
|
||||
SERIALIZE_SCALAR(ver);
|
||||
SERIALIZE_SCALAR(fsr);
|
||||
SERIALIZE_SCALAR(fprs);
|
||||
}
|
||||
static StaticInstPtr decodeInst(MachInst);
|
||||
|
||||
void unserialize(Checkpoint &* cp, std::string & section)
|
||||
{
|
||||
UNSERIALIZE_SCALAR(pstate);
|
||||
UNSERIAlIZE_SCALAR(tba);
|
||||
UNSERIALIZE_SCALAR(y);
|
||||
UNSERIALIZE_SCALAR(pil);
|
||||
UNSERIALIZE_SCALAR(cwp);
|
||||
UNSERIALIZE_ARRAY(tt, MaxTL);
|
||||
UNSERIALIZE_SCALAR(ccr);
|
||||
UNSERIALIZE_SCALAR(asi);
|
||||
UNSERIALIZE_SCALAR(tl);
|
||||
UNSERIALIZE_SCALAR(tpc);
|
||||
UNSERIALIZE_SCALAR(tnpc);
|
||||
UNSERIALIZE_ARRAY(tstate, MaxTL);
|
||||
UNSERIALIZE_SCALAR(tick);
|
||||
UNSERIALIZE_SCALAR(cansave);
|
||||
UNSERIALIZE_SCALAR(canrestore);
|
||||
UNSERIALIZE_SCALAR(otherwin);
|
||||
UNSERIALIZE_SCALAR(cleanwin);
|
||||
UNSERIALIZE_SCALAR(wstate);
|
||||
UNSERIALIZE_SCALAR(ver);
|
||||
UNSERIALIZE_SCALAR(fsr);
|
||||
UNSERIALIZE_SCALAR(fprs);
|
||||
}
|
||||
};
|
||||
// return a no-op instruction... used for instruction fetch faults
|
||||
static const MachInst NoopMachInst;
|
||||
|
||||
typedef union
|
||||
{
|
||||
IntReg intreg;
|
||||
FloatReg fpreg;
|
||||
MiscReg ctrlreg;
|
||||
} AnyReg;
|
||||
// Instruction address compression hooks
|
||||
static inline Addr realPCToFetchPC(const Addr &addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
struct RegFile
|
||||
{
|
||||
IntRegFile intRegFile; // (signed) integer register file
|
||||
FloatRegFile floatRegFile; // floating point register file
|
||||
MiscRegFile miscRegFile; // control register file
|
||||
static inline Addr fetchPCToRealPC(const Addr &addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
Addr pc; // Program Counter
|
||||
Addr npc; // Next Program Counter
|
||||
// the size of "fetched" instructions (not necessarily the size
|
||||
// of real instructions for PISA)
|
||||
static inline size_t fetchInstSize()
|
||||
{
|
||||
return sizeof(MachInst);
|
||||
}
|
||||
|
||||
void serialize(std::ostream &os);
|
||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
|
||||
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
|
||||
|
||||
// return a no-op instruction... used for instruction fetch faults
|
||||
static const MachInst NoopMachInst;
|
||||
|
||||
// Instruction address compression hooks
|
||||
static inline Addr realPCToFetchPC(const Addr &addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline Addr fetchPCToRealPC(const Addr &addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
// the size of "fetched" instructions (not necessarily the size
|
||||
// of real instructions for PISA)
|
||||
static inline size_t fetchInstSize()
|
||||
{
|
||||
return sizeof(MachInst);
|
||||
}
|
||||
|
||||
/**
|
||||
* Function to insure ISA semantics about 0 registers.
|
||||
* @param xc The execution context.
|
||||
*/
|
||||
template <class XC>
|
||||
static void zeroRegisters(XC *xc);
|
||||
/**
|
||||
* Function to insure ISA semantics about 0 registers.
|
||||
* @param xc The execution context.
|
||||
*/
|
||||
template <class XC>
|
||||
static void zeroRegisters(XC *xc);
|
||||
};
|
||||
|
||||
|
||||
typedef SPARCISA TheISA;
|
||||
|
||||
typedef TheISA::MachInst MachInst;
|
||||
typedef TheISA::Addr Addr;
|
||||
typedef TheISA::RegIndex RegIndex;
|
||||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::IntRegFile IntRegFile;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegFile FloatRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::AnyReg AnyReg;
|
||||
typedef TheISA::RegFile RegFile;
|
||||
|
||||
const int VMPageSize = TheISA::VMPageSize;
|
||||
const int LogVMPageSize = TheISA::LogVMPageSize;
|
||||
const int ZeroReg = TheISA::ZeroReg;
|
||||
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
|
||||
const int MaxAddr = (Addr)-1;
|
||||
|
||||
#ifndef FULL_SYSTEM
|
||||
class SyscallReturn {
|
||||
public:
|
||||
template <class T>
|
||||
SyscallReturn(T v, bool s)
|
||||
{
|
||||
retval = (uint64_t)v;
|
||||
success = s;
|
||||
}
|
||||
#if !FULL_SYSTEM
|
||||
class SyscallReturn
|
||||
{
|
||||
public:
|
||||
template <class T>
|
||||
SyscallReturn(T v, bool s)
|
||||
{
|
||||
retval = (uint64_t)v;
|
||||
success = s;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
SyscallReturn(T v)
|
||||
{
|
||||
success = (v >= 0);
|
||||
retval = (uint64_t)v;
|
||||
}
|
||||
template <class T>
|
||||
SyscallReturn(T v)
|
||||
{
|
||||
success = (v >= 0);
|
||||
retval = (uint64_t)v;
|
||||
}
|
||||
|
||||
~SyscallReturn() {}
|
||||
~SyscallReturn() {}
|
||||
|
||||
SyscallReturn& operator=(const SyscallReturn& s) {
|
||||
retval = s.retval;
|
||||
success = s.success;
|
||||
return *this;
|
||||
}
|
||||
SyscallReturn& operator=(const SyscallReturn& s)
|
||||
{
|
||||
retval = s.retval;
|
||||
success = s.success;
|
||||
return *this;
|
||||
}
|
||||
|
||||
bool successful() { return success; }
|
||||
uint64_t value() { return retval; }
|
||||
bool successful() { return success; }
|
||||
uint64_t value() { return retval; }
|
||||
|
||||
|
||||
private:
|
||||
uint64_t retval;
|
||||
bool success;
|
||||
private:
|
||||
uint64_t retval;
|
||||
bool success;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef FULL_SYSTEM
|
||||
#if FULL_SYSTEM
|
||||
|
||||
#include "arch/alpha/ev5.hh"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue