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Merge ktlim@zizzer:/bk/m5

Browse source 
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

--HG--
extra : convert_revision : 979ab1fc4e1ea4d6a78ac9a2ec894f0be4feb01d
This commit is contained in:
Kevin Lim 2006-03-03 16:04:34 -05:00
parent 9ad9178587 14b6cd39aa
commit fc664f7ca6
16 changed files with 225 additions and 155 deletions
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62
arch/alpha/ev5.cc
View file

@ -44,27 +44,6 @@
using namespace EV5;
////////////////////////////////////////////////////////////////////////
//
//
//
void
AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
{
if (regs->pal_shadow == use_shadow)
panic("swap_palshadow: wrong PAL shadow state");
regs->pal_shadow = use_shadow;
for (int i = 0; i < NumIntRegs; i++) {
if (reg_redir[i]) {
IntReg temp = regs->intRegFile[i];
regs->intRegFile[i] = regs->palregs[i];
regs->palregs[i] = temp;
}
}
}
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
@ -73,8 +52,6 @@ void
AlphaISA::initCPU(RegFile *regs, int cpuId)
{
initIPRs(&regs->miscRegs, cpuId);
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
regs->intRegFile[16] = cpuId;
regs->intRegFile[0] = cpuId;
@ -83,12 +60,6 @@ AlphaISA::initCPU(RegFile *regs, int cpuId)
regs->npc = regs->pc + sizeof(MachInst);
}
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
/* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
////////////////////////////////////////////////////////////////////////
//
//
@ -186,42 +157,12 @@ ExecContext::ev5_temp_trap(Fault fault)
readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
(dynamic_cast<AlphaFault *>(fault.get()))->vect();
regs.npc = regs.pc + sizeof(MachInst);
}
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{
bool use_pc = (fault == NoFault);
if (fault->isA<ArithmeticFault>())
panic("arithmetic faults NYI...");
// compute exception restart address
if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
// traps... skip faulting instruction
regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
} else {
// fault, post fault at excepting instruction
regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
}
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
(dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
// that's it! (orders of magnitude less painful than x86)
}
Fault
ExecContext::hwrei()
{
@ -233,9 +174,6 @@ ExecContext::hwrei()
if (!misspeculating()) {
kernelStats->hwrei();
if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
AlphaISA::swap_palshadow(&regs, false);
cpu->checkInterrupts = true;
}

6
arch/alpha/isa/branch.isa
View file

@ -46,7 +46,7 @@ output header {{
mutable const SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, MachInst _machInst,
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
cachedPC(0), cachedSymtab(0)
@ -68,7 +68,7 @@ output header {{
int32_t disp;
/// Constructor.
Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(BRDISP << 2)
{
@ -93,7 +93,7 @@ output header {{
public:
/// Constructor
Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(BRDISP)
{

69
arch/alpha/isa/decoder.isa
View file

@ -681,7 +681,6 @@ decode OPCODE default Unknown::unknown() {
bool dopal = xc->simPalCheck(palFunc);
if (dopal) {
AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
}
@ -705,50 +704,56 @@ decode OPCODE default Unknown::unknown() {
#endif
#if FULL_SYSTEM
format HwLoad {
0x1b: decode HW_LDST_QUAD {
0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
0x1b: decode PALMODE {
0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD {
format HwLoad {
0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
}
}
}
format HwStore {
0x1f: decode HW_LDST_COND {
0: decode HW_LDST_QUAD {
0: hw_st({{ EA = (Rb + disp) & ~3; }},
{{ Mem.ul = Ra<31:0>; }}, L);
1: hw_st({{ EA = (Rb + disp) & ~7; }},
{{ Mem.uq = Ra.uq; }}, Q);
}
0x1f: decode PALMODE {
0: OpcdecFault::hw_st_cond();
format HwStore {
1: decode HW_LDST_COND {
0: decode HW_LDST_QUAD {
0: hw_st({{ EA = (Rb + disp) & ~3; }},
{{ Mem.ul = Ra<31:0>; }}, L);
1: hw_st({{ EA = (Rb + disp) & ~7; }},
{{ Mem.uq = Ra.uq; }}, Q);
}
1: FailUnimpl::hw_st_cond();
1: FailUnimpl::hw_st_cond();
}
}
}
format HwMoveIPR {
0x19: hw_mfpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
fault = new UnimplementedOpcodeFault;
}
else {
0x19: decode PALMODE {
0: OpcdecFault::hw_mfpr();
format HwMoveIPR {
1: hw_mfpr({{
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
}
}});
0x1d: hw_mtpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
fault = new UnimplementedOpcodeFault;
}
else {
}});
}
}
0x1d: decode PALMODE {
0: OpcdecFault::hw_mtpr();
format HwMoveIPR {
1: hw_mtpr({{
xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
}
}});
}});
}
}
format BasicOperate {
0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
}
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {

2
arch/alpha/isa/fp.isa
View file

@ -106,7 +106,7 @@ output header {{
mutable bool warnedOnTrapping;
/// Constructor
AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
roundingMode((enum RoundingMode)FP_ROUNDMODE),
trappingMode((enum TrappingMode)FP_TRAPMODE),

2
arch/alpha/isa/int.isa
View file

@ -37,7 +37,7 @@ output header {{
uint8_t imm;
/// Constructor
IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
{
}

21
arch/alpha/isa/main.isa
View file

@ -79,6 +79,7 @@ namespace AlphaISA;
//
// Universal (format-independent) fields
def bitfield PALMODE <32:32>;
def bitfield OPCODE <31:26>;
def bitfield RA <25:21>;
def bitfield RB <20:16>;
@ -153,9 +154,12 @@ def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
'IsInteger', 1),
'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
'IsInteger', 2),
'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
'IsInteger', 3),
'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
@ -200,7 +204,7 @@ output header {{
};
/// Constructor.
AlphaStaticInst(const char *mnem, MachInst _machInst,
AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: StaticInst(mnem, _machInst, __opClass)
{
@ -272,7 +276,7 @@ def template BasicDeclare {{
{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
%(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
};
@ -280,7 +284,7 @@ def template BasicDeclare {{
// Basic instruction class constructor template.
def template BasicConstructor {{
inline %(class_name)s::%(class_name)s(MachInst machInst)
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
@ -344,7 +348,7 @@ output header {{
public:
/// Constructor
Nop(const std::string _originalDisassembly, MachInst _machInst)
Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
: AlphaStaticInst("nop", _machInst, No_OpClass),
originalDisassembly(_originalDisassembly)
{
@ -428,6 +432,9 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
// PAL instruction templates, formats, etc.
##include "m5/arch/alpha/isa/pal.isa"
// Opcdec fault instruction templates, formats, etc.
##include "m5/arch/alpha/isa/opcdec.isa"
// Unimplemented instruction templates, formats, etc.
##include "m5/arch/alpha/isa/unimp.isa"

18
arch/alpha/isa/mem.isa
View file

@ -42,7 +42,7 @@ output header {{
const StaticInstPtr memAccPtr;
/// Constructor
Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: AlphaStaticInst(mnem, _machInst, __opClass),
@ -70,7 +70,7 @@ output header {{
int32_t disp;
/// Constructor.
MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
@ -89,7 +89,7 @@ output header {{
{
protected:
/// Constructor
MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
@ -141,7 +141,7 @@ def template LoadStoreDeclare {{
{
public:
/// Constructor
EAComp(MachInst machInst);
EAComp(ExtMachInst machInst);
%(BasicExecDeclare)s
};
@ -153,7 +153,7 @@ def template LoadStoreDeclare {{
{
public:
/// Constructor
MemAcc(MachInst machInst);
MemAcc(ExtMachInst machInst);
%(BasicExecDeclare)s
};
@ -161,7 +161,7 @@ def template LoadStoreDeclare {{
public:
/// Constructor.
%(class_name)s(MachInst machInst);
%(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
@ -186,19 +186,19 @@ def template LoadStoreConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
inline %(class_name)s::EAComp::EAComp(MachInst machInst)
inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(ea_constructor)s;
}
inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(memacc_constructor)s;
}
inline %(class_name)s::%(class_name)s(MachInst machInst)
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
{

72
arch/alpha/isa/opcdec.isa Normal file
View file

@ -0,0 +1,72 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
/**
* Static instruction class for instructions that cause an OPCDEC fault
* when executed. This is currently only for PAL mode instructions
* executed in non-PAL mode.
*/
class OpcdecFault : public AlphaStaticInst
{
public:
/// Constructor
OpcdecFault(ExtMachInst _machInst)
: AlphaStaticInst("opcdec fault", _machInst, No_OpClass)
{
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
" OPCDEC fault", machInst, OPCODE);
}
}};
output exec {{
Fault
OpcdecFault::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
return new UnimplementedOpcodeFault;
}
}};
def format OpcdecFault() {{
decode_block = 'return new OpcdecFault(machInst);\n'
}};

12
arch/alpha/isa/pal.isa
View file

@ -36,7 +36,7 @@ output header {{
protected:
/// Constructor.
EmulatedCallPal(const char *mnem, MachInst _machInst,
EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass)
{
@ -83,7 +83,7 @@ output header {{
bool palPriv; ///< is this call privileged?
/// Constructor.
CallPalBase(const char *mnem, MachInst _machInst,
CallPalBase(const char *mnem, ExtMachInst _machInst,
OpClass __opClass);
std::string
@ -93,7 +93,7 @@ output header {{
output decoder {{
inline
CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
palFunc(PALFUNC)
@ -148,7 +148,7 @@ output header {{
int16_t disp;
/// Constructor
HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr);
@ -160,7 +160,7 @@ output header {{
output decoder {{
inline
HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
OpClass __opClass,
StaticInstPtr _eaCompPtr,
StaticInstPtr _memAccPtr)
@ -231,7 +231,7 @@ output header {{
int ipr_index;
/// Constructor
HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass),
ipr_index(HW_IPR_IDX)
{

6
arch/alpha/isa/unimp.isa
View file

@ -38,7 +38,7 @@ output header {{
{
public:
/// Constructor
FailUnimplemented(const char *_mnemonic, MachInst _machInst)
FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a
@ -69,7 +69,7 @@ output header {{
public:
/// Constructor
WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
{
// don't call execute() (which panics) if we're on a
@ -148,7 +148,7 @@ output header {{
{
public:
/// Constructor
Unknown(MachInst _machInst)
Unknown(ExtMachInst _machInst)
: AlphaStaticInst("unknown", _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a

51
arch/alpha/isa_traits.hh
View file

@ -57,16 +57,18 @@ namespace AlphaISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
// typedef uint64_t Addr;
typedef uint8_t RegIndex;
enum {
MemoryEnd = 0xffffffffffffffffULL,
NumIntRegs = 32,
NumFloatRegs = 32,
NumIntArchRegs = 32,
NumPALShadowRegs = 8,
NumFloatArchRegs = 32,
// @todo: Figure out what this number really should be.
NumMiscRegs = 32,
NumMiscArchRegs = 32,
MaxRegsOfAnyType = 32,
// Static instruction parameters
@ -100,17 +102,23 @@ namespace AlphaISA
DepNA = 0,
};
enum {
NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
NumFloatRegs = NumFloatArchRegs,
NumMiscRegs = NumMiscArchRegs
};
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 64,
Fpcr_DepTag = 64, // floating point control register
Uniq_DepTag = 65,
Lock_Flag_DepTag = 66,
Lock_Addr_DepTag = 67,
IPR_Base_DepTag = 68
FP_Base_DepTag = 40,
Ctrl_Base_DepTag = 72,
Fpcr_DepTag = 72, // floating point control register
Uniq_DepTag = 73,
Lock_Flag_DepTag = 74,
Lock_Addr_DepTag = 75,
IPR_Base_DepTag = 76
};
typedef uint64_t IntReg;
@ -132,6 +140,9 @@ extern const Addr PageBytes;
extern const Addr PageMask;
extern const Addr PageOffset;
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];
#if FULL_SYSTEM
typedef uint64_t InternalProcReg;
@ -199,9 +210,7 @@ extern const Addr PageOffset;
Addr pc; // program counter
Addr npc; // next-cycle program counter
#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
inline int instAsid()
{ return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
inline int dataAsid()
@ -212,10 +221,12 @@ extern const Addr PageOffset;
void unserialize(Checkpoint *cp, const std::string &section);
};
StaticInstPtr decodeInst(MachInst);
static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
StaticInstPtr decodeInst(ExtMachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
extern const ExtMachInst NoopMachInst;
enum annotes {
ANNOTE_NONE = 0,
@ -362,6 +373,18 @@ class SyscallReturn {
#endif
static inline AlphaISA::ExtMachInst
AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
#if FULL_SYSTEM
AlphaISA::ExtMachInst ext_inst = inst;
if (pc && 0x1)
return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
else
return ext_inst;
#else
return AlphaISA::ExtMachInst(inst);
#endif
}
#if FULL_SYSTEM
//typedef TheISA::InternalProcReg InternalProcReg;

2
arch/isa_parser.py
View file

@ -225,7 +225,7 @@ def p_specification(t):
# wrap the decode block as a function definition
t[4].wrap_decode_block('''
StaticInstPtr
%(isa_name)s::decodeInst(%(isa_name)s::MachInst machInst)
%(isa_name)s::decodeInst(%(isa_name)s::ExtMachInst machInst)
{
using namespace %(namespace)s;
''' % vars(), '}')

39
base/remote_gdb.cc
View file

@ -424,12 +424,25 @@ void
RemoteGDB::getregs()
{
memset(gdbregs, 0, sizeof(gdbregs));
memcpy(&gdbregs[KGDB_REG_V0], context->regs.intRegFile, 32 * sizeof(uint64_t));
gdbregs[KGDB_REG_PC] = context->readPC();
// @todo: Currently this is very Alpha specific.
if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) {
for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
gdbregs[i] = context->readIntReg(AlphaISA::reg_redir[i]);
}
} else {
for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
gdbregs[i] = context->readIntReg(i);
}
}
#ifdef KGDB_FP_REGS
memcpy(&gdbregs[KGDB_REG_F0], context->regs.floatRegFile.q,
32 * sizeof(uint64_t));
for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
gdbregs[i + KGDB_REG_F0] = context->readFloatRegInt(i);
}
#endif
gdbregs[KGDB_REG_PC] = context->regs.pc;
}
///////////////////////////////////////////////////////////
@ -441,11 +454,21 @@ RemoteGDB::getregs()
void
RemoteGDB::setregs()
{
memcpy(context->regs.intRegFile, &gdbregs[KGDB_REG_V0],
32 * sizeof(uint64_t));
// @todo: Currently this is very Alpha specific.
if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) {
for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
context->setIntReg(AlphaISA::reg_redir[i], gdbregs[i]);
}
} else {
for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
context->setIntReg(i, gdbregs[i]);
}
}
#ifdef KGDB_FP_REGS
memcpy(context->regs.floatRegFile.q, &gdbregs[KGDB_REG_F0],
32 * sizeof(uint64_t));
for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
context->setFloatRegInt(i, gdbregs[i + KGDB_REG_F0]);
}
#endif
context->regs.pc = gdbregs[KGDB_REG_PC];
}

2
cpu/o3/regfile.hh
View file

@ -236,7 +236,7 @@ class PhysRegFile
#if FULL_SYSTEM
private:
// This is ISA specifc stuff; remove it eventually once ISAImpl is used
IntReg palregs[NumIntRegs]; // PAL shadow registers
// IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers

2
cpu/simple/cpu.cc
View file

@ -762,7 +762,7 @@ SimpleCPU::tick()
// decode the instruction
inst = gtoh(inst);
curStaticInst = StaticInst::decode(inst);
curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC()));
traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
xc->regs.pc);

14
cpu/static_inst.hh
View file

@ -231,6 +231,8 @@ class StaticInst : public StaticInstBase
/// Binary machine instruction type.
typedef TheISA::MachInst MachInst;
/// Binary extended machine instruction type.
typedef TheISA::ExtMachInst ExtMachInst;
/// Logical register index type.
typedef TheISA::RegIndex RegIndex;
@ -272,7 +274,7 @@ class StaticInst : public StaticInstBase
StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
const MachInst machInst;
const ExtMachInst machInst;
protected:
@ -302,7 +304,7 @@ class StaticInst : public StaticInstBase
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
: StaticInstBase(__opClass),
machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
{
@ -372,7 +374,7 @@ class StaticInst : public StaticInstBase
/// Decoded instruction cache type.
/// For now we're using a generic hash_map; this seems to work
/// pretty well.
typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache;
typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
/// A cache of decoded instruction objects.
static DecodeCache decodeCache;
@ -387,7 +389,7 @@ class StaticInst : public StaticInstBase
/// @param mach_inst The binary instruction to decode.
/// @retval A pointer to the corresponding StaticInst object.
//This is defined as inline below.
static StaticInstPtr decode(MachInst mach_inst);
static StaticInstPtr decode(ExtMachInst mach_inst);
};
typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
@ -418,7 +420,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst>
/// Construct directly from machine instruction.
/// Calls StaticInst::decode().
StaticInstPtr(TheISA::MachInst mach_inst)
StaticInstPtr(TheISA::ExtMachInst mach_inst)
: RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
{
}
@ -431,7 +433,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst>
};
inline StaticInstPtr
StaticInst::decode(StaticInst::MachInst mach_inst)
StaticInst::decode(StaticInst::ExtMachInst mach_inst)
{
#ifdef DECODE_CACHE_HASH_STATS
// Simple stats on decode hash_map. Turns out the default