Moved constants from isa_traits.hh into constants.hh.
arch/alpha/isa_traits.hh:
Moved constants from isa_traits.hh into constants.hh. Also removed the dependence on ev5.hh
--HG--
extra : convert_revision : f7a03c4ffb1394dcca5a5a96da468c3ff14e1974
This commit is contained in:
Gabe Black
parent
2952ea7c82
commit
03f9716a0a
1 changed files with 3 additions and 76 deletions
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@ -33,6 +33,7 @@ namespace LittleEndianGuest {}
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using namespace LittleEndianGuest;
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#include "arch/alpha/types.hh"
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#include "arch/alpha/constants.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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@ -46,11 +47,6 @@ class Checkpoint;
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class StaticInst;
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class StaticInstPtr;
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namespace EV5 {
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int DTB_ASN_ASN(uint64_t reg);
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int ITB_ASN_ASN(uint64_t reg);
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}
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#if !FULL_SYSTEM
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class SyscallReturn {
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public:
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@ -87,56 +83,9 @@ class SyscallReturn {
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#endif
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namespace AlphaISA
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{
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const int NumIntArchRegs = 32;
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const int NumPALShadowRegs = 8;
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const int NumFloatArchRegs = 32;
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// @todo: Figure out what this number really should be.
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const int NumMiscArchRegs = 32;
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// Static instruction parameters
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const int MaxInstSrcRegs = 3;
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const int MaxInstDestRegs = 2;
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// semantically meaningful register indices
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const int ZeroReg = 31; // architecturally meaningful
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// the rest of these depend on the ABI
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const int StackPointerReg = 30;
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const int GlobalPointerReg = 29;
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const int ProcedureValueReg = 27;
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const int ReturnAddressReg = 26;
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const int ReturnValueReg = 0;
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const int FramePointerReg = 15;
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const int ArgumentReg0 = 16;
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const int ArgumentReg1 = 17;
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const int ArgumentReg2 = 18;
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const int ArgumentReg3 = 19;
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const int ArgumentReg4 = 20;
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const int ArgumentReg5 = 21;
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const int SyscallNumReg = ReturnValueReg;
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const int SyscallPseudoReturnReg = ArgumentReg4;
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const int SyscallSuccessReg = 19;
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const int LogVMPageSize = 13; // 8K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
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const int NumFloatRegs = NumFloatArchRegs;
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const int NumMiscRegs = NumMiscArchRegs;
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typedef IntReg IntRegFile[NumIntRegs];
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typedef union {
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@ -144,11 +93,6 @@ namespace AlphaISA
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double d[NumFloatRegs]; // double-precision floating point view
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} FloatRegFile;
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extern const Addr PageShift;
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extern const Addr PageBytes;
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extern const Addr PageMask;
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extern const Addr PageOffset;
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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@ -156,8 +100,6 @@ extern const int reg_redir[NumIntRegs];
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#include "arch/alpha/isa_fullsys_traits.hh"
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#else
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const int NumInternalProcRegs = 0;
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#endif
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class MiscRegFile {
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protected:
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@ -199,11 +141,6 @@ extern const int reg_redir[NumIntRegs];
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friend class RegFile;
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};
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const int TotalNumRegs = NumIntRegs + NumFloatRegs +
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NumMiscRegs + NumInternalProcRegs;
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const int TotalDataRegs = NumIntRegs + NumFloatRegs;
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struct RegFile {
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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@ -215,9 +152,9 @@ extern const int reg_redir[NumIntRegs];
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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inline int instAsid()
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{ return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
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{ return miscRegs.getInstAsid(); }
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inline int dataAsid()
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{ return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
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{ return miscRegs.getDataAsid(); }
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#endif // FULL_SYSTEM
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void serialize(std::ostream &os);
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@ -228,9 +165,6 @@ extern const int reg_redir[NumIntRegs];
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StaticInstPtr decodeInst(ExtMachInst);
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// return a no-op instruction... used for instruction fetch faults
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extern const ExtMachInst NoopMachInst;
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static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
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@ -301,8 +235,6 @@ extern const int reg_redir[NumIntRegs];
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template <class XC>
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void zeroRegisters(XC *xc);
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const Addr MaxAddr = (Addr)-1;
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#if !FULL_SYSTEM
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static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
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{
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@ -335,9 +267,4 @@ AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
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#endif
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}
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#if FULL_SYSTEM
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#include "arch/alpha/ev5.hh"
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#endif
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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