Gabe Black 91545ac2bf Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 ... into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch cpu/simple/cpu.cc: Hand Merge --HG-- rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4		2006-03-09 15:15:55 -05:00
..
alpha	Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5	2006-03-09 15:15:55 -05:00
mips	last changes before big merge	2006-03-09 03:27:51 -05:00
sparc	last changes before big merge	2006-03-09 03:27:51 -05:00
isa_parser.py	Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.	2006-03-03 15:28:25 -05:00
isa_specific.hh	Auto-generate arch/foo.hh "switch headers" in scons.	2006-02-22 22:22:06 -05:00
SConscript	Pushed ev5.hh out of the non-alpha code.	2006-03-07 14:08:01 -05:00