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Merge gblack@m5.eecs.umich.edu:/bk/multiarch

Browse source 
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : f6db244a66431dd6b8c5ba251ed02d76cd509cff
This commit is contained in:
Gabe Black 2006-03-02 21:44:43 -05:00
parent 6b7d627903 0fed64a6a4
commit dd0d8e6287
11 changed files with 389 additions and 176 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
arch/alpha/isa/decoder.isa
View file

@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// Copyright (c) 2003-2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@ -758,6 +758,15 @@ decode OPCODE default Unknown::unknown() {
0x01: quiesce({{
AlphaPseudo::quiesce(xc->xcBase());
}}, IsNonSpeculative);
0x02: quiesceNs({{
AlphaPseudo::quiesceNs(xc->xcBase(), R16);
}}, IsNonSpeculative);
0x03: quiesceCycles({{
AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
}}, IsNonSpeculative);
0x04: quiesceTime({{
R0 = AlphaPseudo::quiesceTime(xc->xcBase());
}}, IsNonSpeculative);
0x10: ivlb({{
AlphaPseudo::ivlb(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
@ -795,6 +804,9 @@ decode OPCODE default Unknown::unknown() {
0x53: m5addsymbol({{
AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called.");
}}, IsNonSpeculative);
}
}

47
cpu/exec_context.cc
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -35,6 +35,7 @@
#include "base/callback.hh"
#include "base/cprintf.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/profile.hh"
#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
@ -53,10 +54,10 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
FunctionalMemory *_mem)
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys),
memctrl(_sys->memctrl), physmem(_sys->physmem),
cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
kernelBinning(system->kernelBinning), bin(kernelBinning->bin),
fnbin(kernelBinning->fnbin), profile(NULL),
fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this),
func_exe_inst(0), storeCondFailures(0)
{
kernelStats = new Kernel::Statistics(this);
@ -79,8 +80,8 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid)
: _status(ExecContext::Unallocated),
cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
process(_process), mem(process->getMemory()), asid(_asid),
cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
lastSuspend(0), process(_process), mem(process->getMemory()), asid(_asid),
func_exe_inst(0), storeCondFailures(0)
{
memset(&regs, 0, sizeof(RegFile));
@ -109,6 +110,23 @@ ExecContext::dumpFuncProfile()
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
profile->dump(this, *os);
}
ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
: Event(&mainEventQueue), xc(_xc)
{
}
void
ExecContext::EndQuiesceEvent::process()
{
xc->activate();
}
const char*
ExecContext::EndQuiesceEvent::description()
{
return "End Quiesce Event.";
}
#endif
void
@ -143,7 +161,12 @@ ExecContext::serialize(ostream &os)
SERIALIZE_SCALAR(inst);
#if FULL_SYSTEM
Tick quiesceEndTick = 0;
if (quiesceEvent.scheduled())
quiesceEndTick = quiesceEvent.when();
SERIALIZE_SCALAR(quiesceEndTick);
kernelStats->serialize(os);
#endif
}
@ -158,6 +181,11 @@ ExecContext::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(inst);
#if FULL_SYSTEM
Tick quiesceEndTick;
UNSERIALIZE_SCALAR(quiesceEndTick);
if (quiesceEndTick)
quiesceEvent.schedule(quiesceEndTick);
kernelStats->unserialize(cp, section);
#endif
}
@ -169,6 +197,8 @@ ExecContext::activate(int delay)
if (status() == Active)
return;
lastActivate = curTick;
_status = Active;
cpu->activateContext(thread_num, delay);
}
@ -179,6 +209,9 @@ ExecContext::suspend()
if (status() == Suspended)
return;
lastActivate = curTick;
lastSuspend = curTick;
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
@ -186,7 +219,7 @@ ExecContext::suspend()
return;
}
#endif
*/
_status = Suspended;
cpu->suspendContext(thread_num);
}

22
cpu/exec_context.hh
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -32,6 +32,7 @@
#include "config/full_system.hh"
#include "mem/functional/functional.hh"
#include "mem/mem_req.hh"
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
#include "arch/isa_traits.hh"
@ -132,6 +133,9 @@ class ExecContext
// it belongs. For full-system mode, this is the system CPU ID.
int cpu_id;
Tick lastActivate;
Tick lastSuspend;
#if FULL_SYSTEM
FunctionalMemory *mem;
AlphaITB *itb;
@ -154,6 +158,22 @@ class ExecContext
Addr profilePC;
void dumpFuncProfile();
/** Event for timing out quiesce instruction */
struct EndQuiesceEvent : public Event
{
/** A pointer to the execution context that is quiesced */
ExecContext *xc;
EndQuiesceEvent(ExecContext *_xc);
/** Event process to occur at interrupt*/
virtual void process();
/** Event description */
virtual const char *description();
};
EndQuiesceEvent quiesceEvent;
#else
Process *process;

9
cpu/simple/cpu.cc
View file

@ -347,12 +347,12 @@ SimpleCPU::copySrcTranslate(Addr src)
// translate to physical address
Fault fault = xc->translateDataReadReq(memReq);
assert(!fault->isAlignmentFault());
if (fault == NoFault) {
xc->copySrcAddr = src;
xc->copySrcPhysAddr = memReq->paddr + offset;
} else {
assert(!fault->isAlignmentFault());
xc->copySrcAddr = 0;
xc->copySrcPhysAddr = 0;
}
@ -382,8 +382,6 @@ SimpleCPU::copy(Addr dest)
// translate to physical address
Fault fault = xc->translateDataWriteReq(memReq);
assert(!fault->isAlignmentFault());
if (fault == NoFault) {
Addr dest_addr = memReq->paddr + offset;
// Need to read straight from memory since we have more than 8 bytes.
@ -402,6 +400,9 @@ SimpleCPU::copy(Addr dest)
dcacheInterface->access(memReq);
}
}
else
assert(!fault->isAlignmentFault());
return fault;
}

38
sim/pseudo_inst.cc
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -77,6 +77,42 @@ namespace AlphaPseudo
xc->kernelStats->quiesce();
}
void
quiesceNs(ExecContext *xc, uint64_t ns)
{
if (!doQuiesce || ns == 0)
return;
if (xc->quiesceEvent.scheduled())
xc->quiesceEvent.reschedule(curTick + Clock::Int::ns * ns);
else
xc->quiesceEvent.schedule(curTick + Clock::Int::ns * ns);
xc->suspend();
xc->kernelStats->quiesce();
}
void
quiesceCycles(ExecContext *xc, uint64_t cycles)
{
if (!doQuiesce || cycles == 0)
return;
if (xc->quiesceEvent.scheduled())
xc->quiesceEvent.reschedule(curTick + xc->cpu->cycles(cycles));
else
xc->quiesceEvent.schedule(curTick + xc->cpu->cycles(cycles));
xc->suspend();
xc->kernelStats->quiesce();
}
uint64_t
quiesceTime(ExecContext *xc)
{
return (xc->lastActivate - xc->lastSuspend) / Clock::Int::ns ;
}
void
ivlb(ExecContext *xc)
{

5
sim/pseudo_inst.hh
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -44,6 +44,9 @@ namespace AlphaPseudo
void arm(ExecContext *xc);
void quiesce(ExecContext *xc);
void quiesceNs(ExecContext *xc, uint64_t ns);
void quiesceCycles(ExecContext *xc, uint64_t cycles);
uint64_t quiesceTime(ExecContext *xc);
void ivlb(ExecContext *xc);
void ivle(ExecContext *xc);
void m5exit(ExecContext *xc, Tick delay);

64
util/m5/Makefile
View file

@ -1,26 +1,50 @@
AS=as
CC=cc
LD=cc
# Copyright (c) 2005-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
CCFLAGS=-O2
#LDFLAGS=-non_shared
### If we are not compiling on an alpha, we must use cross tools ###
ifneq ($(shell uname -m), alpha)
CROSS_COMPILE?=alpha-unknown-linux-gnu-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
CFLAGS=-O2
OBJS=m5.o m5op.o
all: m5
m5: m5op.o m5.o
$(LD) $(LDFLAGS) -o $@ $>
strip $@
%.o: %.S
$(CC) $(CFLAGS) -o $@ -c $<
%.o: %.c
$(CC) $(CFLAGS) -o $@ -c $<
m5: $(OBJS)
$(CC) -o $@ $(OBJS)
clean:
@rm -f m5 *.o *.d *~ .#*
.SUFFIXES:
.SUFFIXES:.o .c .s
# C Compilation
.c.o:
$(CC) $(CCFLAGS) -o $@ -c $<
# Assembly
.s.o:
$(AS) $(ASFLAGS) -o $@ $<
rm -f *.o m5

18
util/m5/m5.c
View file

@ -73,7 +73,7 @@ main(int argc, char *argv[])
usage();
arg1 = strtoul(argv[2], NULL, 0);
ivlb(arg1);
m5_ivlb(arg1);
return 0;
}
@ -82,7 +82,7 @@ main(int argc, char *argv[])
usage();
arg1 = strtoul(argv[2], NULL, 0);
ivle(arg1);
m5_ivle(arg1);
return 0;
}
@ -90,7 +90,7 @@ main(int argc, char *argv[])
if (argc != 2)
usage();
printf("%ld", initparam());
printf("%ld", m5_initparam());
return 0;
}
@ -98,7 +98,7 @@ main(int argc, char *argv[])
if (argc != 2)
usage();
param = initparam();
param = m5_initparam();
// run-time, rampup-time, rampdown-time, warmup-time, connections
printf("%d %d %d %d %d", (param >> 48) & 0xfff,
(param >> 36) & 0xfff, (param >> 24) & 0xfff,
@ -112,7 +112,7 @@ main(int argc, char *argv[])
case 3:
arg1 = strtoul(argv[2], NULL, 0);
case 2:
m5exit(arg1);
m5_exit(arg1);
return 0;
default:
@ -127,7 +127,7 @@ main(int argc, char *argv[])
case 3:
arg1 = strtoul(argv[2], NULL, 0);
case 2:
reset_stats(arg1, arg2);
m5_reset_stats(arg1, arg2);
return 0;
default:
@ -142,7 +142,7 @@ main(int argc, char *argv[])
case 3:
arg1 = strtoul(argv[2], NULL, 0);
case 2:
dump_stats(arg1, arg2);
m5_dump_stats(arg1, arg2);
return 0;
default:
@ -157,7 +157,7 @@ main(int argc, char *argv[])
case 3:
arg1 = strtoul(argv[2], NULL, 0);
case 2:
dumpreset_stats(arg1, arg2);
m5_dumpreset_stats(arg1, arg2);
return 0;
default:
@ -172,7 +172,7 @@ main(int argc, char *argv[])
case 3:
arg1 = strtoul(argv[2], NULL, 0);
case 2:
checkpoint(arg1, arg2);
m5_checkpoint(arg1, arg2);
return 0;
default:

196
util/m5/m5op.S Normal file
View file

@ -0,0 +1,196 @@
/*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define m5_op 0x01
#define arm_func 0x00
#define quiesce_func 0x01
#define quiescens_func 0x02
#define quiescecycle_func 0x03
#define quiescetime_func 0x04
#define ivlb_func 0x10
#define ivle_func 0x11
#define exit_old_func 0x20 // deprectated!
#define exit_func 0x21
#define initparam_func 0x30
#define resetstats_func 0x40
#define dumpstats_func 0x41
#define dumprststats_func 0x42
#define ckpt_func 0x43
#define readfile_func 0x50
#define debugbreak_func 0x51
#define switchcpu_func 0x52
#define addsymbol_func 0x53
#define panic_func 0x54
#define INST(op, ra, rb, func) \
.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
#define LEAF(func) \
.align 3; \
.globl func; \
.ent func; \
func:
#define RET \
ret ($26)
#define END(func) \
.end func
#define ARM(reg) INST(m5_op, reg, 0, arm_func)
#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func)
#define IVLE(reg) INST(m5_op, reg, 0, ivle_func)
#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
#define READFILE INST(m5_op, 0, 0, readfile_func)
#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
#define PANIC INST(m5_op, 0, 0, panic_func)
.set noreorder
.align 4
LEAF(arm)
ARM(16)
RET
END(arm)
.align 4
LEAF(quiesce)
QUIESCE
RET
END(quiesce)
.align 4
LEAF(quiesceNs)
QUIESCENS(16)
RET
END(quiesceNs)
.align 4
LEAF(quiesceCycle)
QUIESCECYC(16)
RET
END(quiesceCycle)
.align 4
LEAF(quiesceTime)
QUIESCETIME
RET
END(quiesceTime)
.align 4
LEAF(m5_ivlb)
IVLB(16)
RET
END(m5_ivlb)
.align 4
LEAF(m5_ivle)
IVLE(16)
RET
END(m5_ivle)
.align 4
LEAF(m5_exit)
M5EXIT(16)
RET
END(m5_exit)
.align 4
LEAF(m5_initparam)
INITPARAM(0)
RET
END(m5_initparam)
.align 4
LEAF(m5_reset_stats)
RESET_STATS(16, 17)
RET
END(m5_reset_stats)
.align 4
LEAF(m5_dump_stats)
DUMP_STATS(16, 17)
RET
END(m5_dump_stats)
.align 4
LEAF(m5_dumpreset_stats)
DUMPRST_STATS(16, 17)
RET
END(m5_dumpreset_stats)
.align 4
LEAF(m5_checkpoint)
CHECKPOINT(16, 17)
RET
END(m5_checkpoint)
.align 4
LEAF(m5_readfile)
READFILE
RET
END(m5_readfile)
.align 4
LEAF(m5_debugbreak)
DEBUGBREAK
RET
END(m5_debugbreak)
.align 4
LEAF(m5_switchcpu)
SWITCHCPU
RET
END(m5_switchcpu)
.align 4
LEAF(m5_addsymbol)
ADDSYMBOL(16, 17)
RET
END(m5_addsymbol)
.align 4
LEAF(m5_panic)
PANIC
RET
END(m5_panic)

31
util/m5/m5op.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -29,17 +29,26 @@
#ifndef __M5OP_H__
#define __M5OP_H__
#include <inttypes.h>
#include <asm/types.h>
void arm(uint64_t address);
void quiesce();
void ivlb(uint64_t interval);
void ivle(uint64_t interval);
void m5exit(uint64_t ns_delay);
uint64_t initparam();
void checkpoint(uint64_t ns_delay, uint64_t ns_period);
void reset_stats(uint64_t ns_delay, uint64_t ns_period);
void dump_stats(uint64_t ns_delay, uint64_t ns_period);
void dumpreset_stats(uint64_t ns_delay, uint64_t ns_period);
void quiesce(void);
void quiesceNs(uint64_t ns);
void quiesceCycle(uint64_t cycles);
uint64_t quiesceTime(void);
void m5_ivlb(uint64_t interval);
void m5_ivle(uint64_t interval);
void m5_exit(uint64_t ns_delay);
uint64_t m5_initparam(void);
void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period);
void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period);
void m5_dump_stats(uint64_t ns_delay, uint64_t ns_period);
void m5_dumpreset_stats(uint64_t ns_delay, uint64_t ns_period);
uint64_t m5_readfile(void *buffer, uint64_t len, uint64_t offset);
void m5_debugbreak(void);
void m5_switchcpu(void);
void m5_addsymbol(uint64_t addr, char *symbol);
void m5_panic(void);
#endif // __M5OP_H__

121
util/m5/m5op.s
View file

@ -1,121 +0,0 @@
/*
* Copyright (c) 2003, 2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <regdef.h>
#define m5_op 0x01
#define arm_func 0x00
#define quiesce_func 0x01
#define ivlb_func 0x10
#define ivle_func 0x11
#define exit_old_func 0x20 // deprectated!
#define exit_func 0x21
#define initparam_func 0x30
#define resetstats_func 0x40
#define dumpstats_func 0x41
#define dumprststats_func 0x42
#define ckpt_func 0x43
#define INST(op, ra, rb, func) \
.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
#define ARM(reg) INST(m5_op, reg, 0, arm_func)
#define QUIESCE() INST(m5_op, 0, 0, quiesce_func)
#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func)
#define IVLE(reg) INST(m5_op, reg, 0, ivle_func)
#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
.set noreorder
.align 4
LEAF(arm)
ARM(16)
RET
END(arm)
.align 4
LEAF(quiesce)
QUIESCE()
RET
END(quiesce)
.align 4
LEAF(ivlb)
IVLB(16)
RET
END(ivlb)
.align 4
LEAF(ivle)
IVLE(16)
RET
END(ivle)
.align 4
LEAF(m5exit)
M5EXIT(16)
RET
END(m5exit)
.align 4
LEAF(initparam)
INITPARAM(0)
RET
END(initparam)
.align 4
LEAF(reset_stats)
RESET_STATS(16, 17)
RET
END(reset_stats)
.align 4
LEAF(dump_stats)
DUMP_STATS(16, 17)
RET
END(dump_stats)
.align 4
LEAF(dumpreset_stats)
DUMPRST_STATS(16, 17)
RET
END(dumpreset_stats)
.align 4
LEAF(checkpoint)
CHECKPOINT(16, 17)
RET
END(checkpoint)